THERE is growing concern regarding power quality of ac

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1 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY Neural Network and Bandless Hysteresis Approach to Control Switched Capacitor Active Power Filter for Reduction of Harmonics Mohd Amran Mohd Radzi, Member, IEEE, and Nasrudin Abd. Rahim, Senior Member, IEEE Abstract This paper proposes a combination of neural network and a bandless hysteresis controller, for a switched capacitor active power filter (SCAPF), to improve line power factor and to reduce line current harmonics. The proposed active power filter controller forces the supply current to be sinusoidal, in phase with line voltage, and has low current harmonics. Two main controls are proposed for it: neural network detection of harmonics and bandless digital hysteresis switching algorithm. A mathematical algorithm and a suitable learning rate determine the filter s optimal operation. A digital signal controller (TMS320F2812) verifies the proposed SCAPF, implementing the neural network and bandless hysteresis algorithms. A laboratory SCAPF system is built to test its feasibility. Simulation and experimental results are provided to verify performance of the proposed SCAPF system. Index Terms Bandless hysteresis, harmonic, neural network, power factor, switched capacitor active power filter (SCAPF). I. INTRODUCTION THERE is growing concern regarding power quality of ac supply systems. The main problem is harmonic distortion; high usage of power electronic devices implemented in electricity supply networks increase it, and nonsinusoidal currents of the nonlinear loads affect the system. Compensation of the generated harmonics and correction of the load power factor are necessary. An active power filter (APF) is a main harmonic mitigating tool as it is developed from the advances of power electronic technology. Various topologies of APF are reported and inverter is commonly discussed [1] [3]. Various control methods to ensure expected performance are also discussed [4]. Several works offer switched capacitor APF topology [2], [5] [8]. The topology can be called as switched capacitor APF (SCAPF); it brings new dimension to APF as it reduces components and ratings (particularly capacitor) while performing at low switching frequency. Comparison of the SCAPF topology with other related APF topologies has been discussed in [2]. This paper proposes an improved control algorithm SCAPF. Various control strategies for APFs have been developed previ- Manuscript received July 10, 2008; revised January 5, First published February 6, 2009; current version published April 29, The authors are with the Center of Research for Power Electronics, Drives, Automation and Control, Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia ( amranmr@hotmail.com; nasrudin@um.edu.my). Digital Object Identifier /TIE ously [1], [4]. They can be classified into three main categories: reference generation (known also as harmonic detection or isolation method), current control (known also as switching strategy), and dc-bus voltage control (usually implemented in inverter-based control). This paper proposed differs slightly different from inverterbased topology; the third control is unnecessary, less complicating the whole system easy implementation of control algorithm in a small, limited speed and limited memory, embedded controller. As [4] explains, detection of harmonics can be implemented through methods of time domain, frequency domain, and heterodyne (which involves multiplying a distorted signal by a sinusoid), pattern learning and identification (which mainly reports on neural network technique), and instantaneous power compensation (which uses the definition of instantaneous active power and reactive power theory). In a previous development of SCAPF, the optimization algorithm extracted the harmonic component and directly created filter current switching pattern [5]. The method tends to complicate computation, and the convergence causes time delay. Genetic algorithm improved the convergence time, improving it [9]. However, the algorithm s complexity is a main issue in the system s development. Moreover, both algorithms are implemented as offline control, slowing performance. In [10], analog circuit extracted harmonics through principle of adaptive noise canceling. The topology has three bidirectional switches, two connected to capacitors for operation of their voltage polarity [8], another connected to an inductor. Thus, hysteresis current control can be used as online control for the filter. However, the control method needs analog and logic circuits, which complicates hardware development. This paper proposes, for extraction of harmonics, a fast and improved artificial neural network (ANN) control scheme. Previous works [11] [17] exist, particularly in inverterbased topology. It is widely developed, owing to its simplicity, and learning and generalization ability. Furthermore, possible control scheme modification through a weightsupdating algorithm will speed up extraction of harmonics, shortening adaptation time and realizing fast response of the SCAPF. This paper prefers the least-squares approach. Most popular is the least-mean-square (LMS) algorithm, known also as the delta rule or the Widrow Hoff (W H) rule; basically, it operates /$ IEEE

2 1478 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009 with a single linear neuron model. The algorithm can be used directly in an APF application as in [11] where two neural adaptive filters in notch and band configurations were developed. The algorithm is also applied directly to determine components of active, reactive, and harmonic currents, for selective compensation on priority with respect to the inverter s limited power capacity [12]. Other application works [13] [16] report their adaptation of the algorithm. A modified W H rule minimizes average square error between actual and estimated signals. An interesting work on ANN algorithm is the algorithm s modification; only the fundamental component with a proper learning-rate value is depended on [16]. Simulation work with it showed tremendous performance. Yet, challenges still exist in the experimental test implementation, and in lack of discussions on methods and ideas for a good range of learning rate value. This paper therefore proposes how the algorithm can be helpful in a SCAPF application and discusses a few considerations in selecting proper learning rate value. This paper implements digitally the ANN algorithm. A digital control system is preferable to an analog one as a digitalsystem tool can be fully optimized to process and analyze real-time signals. One of the best tools is digital signal processor (DSP), used in developing the hardware. With growing DSP use in various digital control applications, APFs also are not excluded of using the processor to miniaturize systems and perform at high speed. Previous works [18] [20] report the importance of DSP in implementing, and testing by experiment, the designed algorithms, in ensuring expected performance. The next stage is implementing switching algorithm; a hysteresis algorithm is proposed. This technique is widely used owing to its simplicity and robustness [8], [12], [16]. The switching pulse is produced when the real signal operates within an allowable band of reference signal; this sometimes causes problem in digital operation where high ripple is produced at the output and more time is required for algorithm operation. Therefore, this paper proposes an improved switching technique; it can be called a bandless digital hysteresis control. It just neglects to use a band control in hysteresis algorithm in determining the filter s switching pattern, directly reducing ripple component in the filter s current, simultaneously minimizing time required for calculation and for comparison tasks by the DSP. Section II of this paper describes the SCAPF s topology as an alternative APF. Section III discusses development of its control system, and Section IV presents simulated results. Section V presents experimental work and results validating the SCAPF s performance, ending in Section VI with a summary of the SCAPF s function and performance. II. SCAPF TOPOLOGY Fig. 1 shows a basic diagram of an APF system connected parallel to a nonlinear load. In nonlinear load without APF, the load current i L comprises a fundamental component i 1 and harmonic components i H, both present within the source current i S, polluting the power system. After APF is connected, Fig. 1. Fig. 2. Basic configuration of APF. SCAPF topology. it generates a filter current i F which then compensates harmonic current produced by the load, as shown by i S = i L + i F = i 1 + i H + i F. (1) Therefore, if i F = i H, the source current i S will only contain the fundamental component. Fig. 2 shows a block diagram of the SCAPF s topology, showing two capacitors in series with two main bidirectional switches connected parallel to the ac line. In the experiment, since both switches are considered to be applied with a small deadband during their transition period, a small resistor with another bidirectional switch is required to allow smooth transfer of current between both capacitor branches at that period. All switches are connected to the DSP, which performs digital control algorithm in the system. Two current sensors measuring load and filter currents are connected to the DSP. A small limiting inductor is connected between all branches and line to control the filter current. Switches S 1 and S 2 work in antiphase so that the filter current flows through the branches alternately. Another switch, S 3 will work during the transition period of S 1 and S 2. Both capacitors are charged and switching patterns are determined through a hysteresis algorithm explained later. The filter current s rate of change is controlled by a limiting inductor. The two capacitor branches make the circuit s operation more flexible, allowing switching at any instant and also at any switching frequency.

3 RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF 1479 III. CONTROL DEVELOPMENT A. Neural Network Detection As mentioned, extraction of harmonic component is through ANN algorithm; the principle of using the sum of sine and cosine components with an appropriate coefficient attached to each component to represent any periodic signals. For each sample k in digital operation with sampling time Δt and fundamental frequency ω, the nonlinear load current i L is represented by a fundamental component and a harmonic component as shown by i L (k) = N n=1,2,3,... [w 1n sin(nkωδt)+w 2n cos(nkωδt)] = w 11 sin(kωδt)+w 21 cos(kωδt) N + [w 1n sin(nkωδt)+w 2n cos(nkωδt)] n=2,3,... where w 1n and w 2n are the amplitudes of the sine and cosine parts of the measured nonlinear load current, an n is the number of harmonics, to N maximum number. Both terms can be represented in vectorial form as (2) i L (k) =W T X(k) (3) where the weight matrix W T =[w 11 w 21,...,w 1N w 2N ] and the sine and cosine vector. X(k) =.. sin(kωδt) cos(kωδt) sin(nkωδt) cos(nkωδt). The ANN algorithm is used to train W T to generate the right value of i L (k), as shown in Fig. 3. The heart of this algorithm extraction circuit is the weights updating algorithm block where the W H weights updating algorithm is used. The W H weights updating algorithm can minimize the average square error e(k) between the actual measured signal i L (k) and the estimated signal i est (k), which can be written as W (k +1)=W (k)+ e(k)x(k) X T (k)x(k) where e(k) =i L (k) i est (k) and X T (k)x(k) is the square of the norm of the vector X(k). However, the dimension of the weight matrix W T is updated according to the number of harmonic orders N, which (4) Fig. 3. Harmonic extraction by ANN. lengthens calculation time, relatively, a simplified algorithm [16] proposes that αe(k)y (k) W (k +1)=W (k)+ Y T (5) (k)y (k) [ ] where W T sin(kωδt) =[w 11 w 21 ], Y = and α is the cos(kωδt) learning rate. This modified W H algorithm needs only to update the two weights of the fundamental component, making it independent of the number of harmonic orders present. The modification is based on the mathematical relationship of the elements being orthogonal to each other. With this modification, the iteration speed is greatly enhanced, resulting in faster estimation. However, updating only the two weights results in a large e(k). Hence, a learning rate is added, as shown in (5), and Fig. 4 shows the modified version of proposed ANN algorithm. The next issue of implementing this method is the selection of suitable learning rate value. Previously, initial work was carried out with some range of learning rate [21] but, then,

4 1480 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009 Fig. 5. Normal hysteresis. Fig. 4. Modified ANN. this paper does not discuss selection of learning rate, and experimental work on the algorithm s implementation in handling harmonics existing in the system does not show encouraging results. Therefore, further study is needed to determine a good range of learning rate. From (4), if maximum number of harmonic N is decided, the square of the norm of the vector X(k) results in N, too. However, in (5), the square of the norm of the vector Y (k) is one as it contains only the fundamental component. Therefore, the learning rate can be chosen to be less than 1/N to ensure the algorithm s optimum performance. The harmonic current, i H (k) can be produced from load current deduction (from load current s fundamental sine part), or as follows: i H (k) =i L (k) w 11 sin(kωδt). (6) Fig. 6. Digital hysteresis. Two main considerations are proposed for the best learning rate value: how fast the algorithm can produce the harmonic current i H to be used in hysteresis algorithm later, and how good the algorithm can produce harmonic current i H to minimize THD of source current i S. B. Bandless Digital Hysteresis Current Control Hysteresis current control seems to be widely used since it is easy to be implemented than other switching methods are. In SCAPF application, this switching scheme has been used with analog scheme development [10]. However, digital hysteresis can be considered, too, since it will minimize hardware development complexities. As an introduction, from Fig. 5, normal hysteresis in an analog control operates when filter current i F reaches bandwidth ΔI of the reference current i REF before the switch state changes. The proper selection of ΔI together with a limiting inductor improves filter performance in produce smoother current. Through this method, the switching frequency varies according to the switch state. However, in digital control, sample time T must be considered, to determine whether the switch will change state. Fig. 6 shows an operational digital hysteresis control. Let the system be sampled at time T. The bandwidth ΔI is set for the hysteresis operation. Ideally, the switch changes its state when the filter current reaches the bandwidth, but as it is operated digitally, then it changes state only when it reaches sampling point after going through the bandwidth. Therefore, the switch changes its state at the desired sample rather than at the bandwidth limit, causing the filter current to exceed the bandwidth. Switching time is longer, resulting too low a switching frequency. The ripple is higher and a bigger inductor is needed to limit the ripple, directly increasing losses. Therefore, and to avoid use of bandwidth, this paper implements a modified digital hysteresis current control. Fig. 7 shows the proposed algorithm. The switch will change state at sampling point after i F is higher, or lower, than i REF.The algorithm can be explained as below. 1) When i F <i REF,S 1 is on. 2) When i F >i REF,S 1 is off. The ripple will be lower than it was before as long as an inductor of suitable value is selected. Switch operation is optimized, resulting in a smooth waveform. Although the switching frequency varies, the maximum value can be determined. If T

5 RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF 1481 Fig. 7. Bandless digital hysteresis. is sample time, then the switching period is in minimum value at double of sample time T. Maximum switching frequency can be determined from f switch (max) = 1 2T. (7) Therefore, sampling frequency or sample time must be properly selected when programming the DSP. Among the considerations, the DSP must have enough time to handle acquisition of data from sensor measurements, be capable in handling calculation of algorithm for harmonic detection at each sampling time, and be able to compare with the reference current, the filter current, in the hysteresis algorithm, at each sampling time. A high sampling frequency increases sensitivity of the controller s reaction to the signal, but will limit time to handle all algorithms. Those requirements are considered in the experiment s implementation. C. Implementation of Digital Control in DSP This paper chooses a DSP for its fast processing speed, which enables high sampling task, and for its capability to cover mathematical algorithm, considered the main element of the control. Its smallness provides advantage over the usual processor in running a specialized task. Configuration of SCAPF s control algorithm is therefore developed directly in the DSP. In digital control, data is based on sample time set through the controller. The DSP as the selected controller with the proper setting of sampling frequency captures continuously signals from measured points of sampling time. This paper uses sampling frequency in determine the number of samples acquired from sensors within one cycle, and to generate switching signal. The sampling frequency is set at 25 khz (40 μs in sampling time). For a 50-Hz operation, 500 samples can be captured. Equation (7) determines the maximum switching frequency 1 f switch (max) = =12.5kHz Fig. 8 shows the control block developed in the DSP. One voltage sensor and two current sensors are used at measurement. The voltage sensor measures voltage at the point of common coupling V pcc. One current sensor is connected to the load, measuring load current I L and another is connected to SCAPF, measuring filter current I F. A zero-crossing detector (ZCD) circuit is designed to generate signal to the DSP when a zero crossing voltage is detected at the point of common coupling. The measurement processed by DSP starts from the ZCD circuit s signal detection. The ZCD s input module program initializes starting time of the DSP s sampling operation. Measurement of I L and I F are processed by an analog-todigital (ADC) module in the DSP, analog values converted to digital ones. I L is processed by the harmonic detection algorithm, ANN, for harmonic current I H. This current is compared with I F in the hysteresis algorithm, to produce pulse signals equivalent to those of S 1 and S 2. IV. SIMULATION RESULT The circuit was developed and tested in MATLAB Simulink together with SimPowerSystems block. A control block implemented the ANN algorithm, performing the bandless digital hysteresis algorithm. The solver was configured by using discrete variable step to ensure the simulation s digital operation. Sampling time was set as 40 μs. The simulation s main purpose was to determine the best range of learning rate value for use in the experiment. The effectiveness of hysteresis control was also observed. Two types of nonlinear loads were developed by using a diode bridge rectifier, feeding a capacitive load comprising of a 470-μF capacitor and 50-Ω resistor, and feeding an inductive load comprising a 160-mH inductor and a 15-Ω resistor. Table I shows details of the proposed SCAPF s parameters. In the beginning, both circuits were simulated without connecting SCAPF. In capacitive load, the THD was 77.03%, and in inductive load, it was 33.19%. Then, the SCAPF was connected to both configurations of the circuit and learning rate values from to were chosen for testing. Table II presents observations on time taken for the algorithm to successfully form a stable i H, and the THD measurements when the learning range was changed. From Table II, the learning rate s optimum value was 0.003, where the time taken was only in two cycles, and the THD was measured within allowable limits for both types of nonlinear loads. Although the smaller value could reduce THD owing to production of good i H,it would cause slow increment of i H in each sample k value. Therefore, the stated value was selected as it would help the algorithm to produce a stable i H faster, and then minimize the THD to within allowable limits. Fig. 9 shows waveforms of harmonic current I H extracted by ANN algorithm through the best learning rate of for both capacitive and inductive loads. The ANN algorithm successfully produced a stable i H after two cycles. Figs. 10 and 11 show waveforms of the source voltage, the load current, the filter current, and the source current for capacitive load and for inductive load, respectively. From Table II and Fig. 10, in the capacitive load, the THD reading was recorded as 3.27%. Besides having a good i H, hysteresis control also helps in

6 1482 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009 Fig. 8. Control block developed in DSP. TABLE I PARAMETERS FOR PROPOSED SCAPF TABLE II OBSERVATION TIME TO OBTAIN STABLE I H AND THD MEASUREMENT FOR SPECIFIED LEARNING RATES Fig. 9. Harmonic extractions by ANN algorithm for both capacitive and inductive loads. minimizing allowable value of THD. At the same time, i S seemed to work in phase with V S, which led to a maximum power factor. In inductive load, the THD was 2.69%. The SCAPF also successfully compensated harmonic current (see Fig. 11). The ANN algorithm took two cycles to get a stable i H and i S seemed to work in phase with V S. V. E XPERIMENT RESULT The experiment setup is as shown in Fig. 12. The SCAPF sampling frequency was 25 khz. Three insulated gate bipolar transistors (1200 V, 41 A) and 12 fast recovery diodes (1200 V, 30 A) were used to develop bidirectional switches. Three bidirectional switches were developed, two connected to 120-μF capacitors, and one to a 15-Ω resistor. A diode bridge rectifier configuration feeding a capacitive load comprising a 470-μF capacitor and 50-Ω resistor was set up as a nonlinear load. The capacitor and the resistor were connected to a 5-mH limiting inductor. A DSP TMS320F2812 implemented the control algorithms. The DSP was selected as it has a 32-b CPU performing at 150 MHz. Among its interesting features, useful in this paper, were a 12-b ADC module handling 16 channels, and two onchip event manager peripherals providing a broad range of functions particularly useful in applications of control. The programming part for ANN algorithm and bandless digital hysteresis algorithm were developed and written in C language and then compiled in Code Composer Studio. The compiled program was downloaded onto the DSP. Sampling frequency was set at 25 khz. The ANN algorithm was configured by using a learning rate of 0.003, already determined in simulation to be the optimum value. Voltage source, load current, filter current, and source current were measured. THD was measured through a Power Quality Analyzer. To study this filter s effectiveness, power factor was also measured for both types of load configurations. Fig. 13 shows the results. Fig. 13 also shows the SCAPF to have functioned very well in compensating load harmonic current, with the source current

7 RADZI AND RAHIM: NEURAL NETWORK AND BANDLESS HYSTERESIS APPROACH TO CONTROL SCAPF 1483 Fig. 12. Configuration of experimental setup. Fig. 10. Simulated waveforms for the source voltage V S, the load current I L, the filter current I F, and the source current I S for capacitive load. Fig. 13. Experimental result for the source voltage V S (200 V/div), the load current I L (10 A/div), the filter current I F (10 A/div), and the source current I S (10 A/div) for capacitive load. digital hysteresis algorithms developed in the DSP were able to operate the filter in reducing the THD value, with reduced current harmonics. Fig. 14 shows results of the experiment when SCAPF was connected to the inductive load (160-mH inductor and 15-Ω resistor). Load current THD was 26.3% while that of source current was 4.6%. Power factor was The encouraging values show that this filter is able to reduce current harmonics. Fig. 11. Simulated waveforms for the source voltage V S, the load current I L, the filter current I F, and the source current I S for inductive load. waveform being almost sinusoidal. Load current THD was 58.6%, and that of the source current was 4.7%. The power factor was This means that the ANN and the bandless VI. CONCLUSION The SCAPF proves to be a plausible alternative in reducing harmonic distortion through capacitors connected to bidirectional switches. In the APF, a modified ANN and bandless digital hysteresis algorithms were proposed for its control. The ANN was designed and developed to detect harmonic component, and the bandless digital hysteresis was implemented to produce switching strategies for the filter. A suitable learning rate is important in implementing an ANN algorithm; therefore,

8 1484 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009 Fig. 14. Experimental result for the source voltage V S (200 V/div), the load current I L (10 A/div), the filter current I F (10 A/div), and the source current I S (10 A/div) for inductive load. the simulation found it. From the simulation, a laboratory prototype was implemented practically. From the experiment, current harmonics observed in the testing system, produced from nonlinear loads, was successfully reduced. At the same time, the source current was closely in phase with the voltage source where power factor was near to unity. [12] B. Singh, V. Verma, and J. Solanki, Neural network-based selective compensation of current quality problems in distribution system, IEEE Trans. Ind. Electron., vol. 54, no. 1, pp , Feb [13] D. O. Abdeslam, P. Wira, J. Mercklé, D. Flieller, and Y.-A. Chapuis, A unified artificial neural network architecture for active power filters, IEEE Trans. Ind. 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Power Appl., vol. 147, no. 1, pp , Jan [10] T. Kandil, L. Lopes, and W. Xu, Transient analysis of a per phase switched capacitor based load compensator, in Proc. 5th Int. Conf. Power Electron. Drive Syst., Singapore, 2003, vol. 1, pp [11] M. Cirrincione, M. Pucci, and G. Vitale, A single-phase DG generation unit with shunt active power filter capability by adaptive neural filtering, IEEE Trans. Ind. Electron., vol. 55, no. 5, pp , May Mohd Amran Mohd Radzi (M 01) was born in Kuala Lumpur, Malaysia, in He received the B.Eng. (Hons.) and M.Sc. degrees in electrical power engineering from Universiti Putra Malaysia (UPM), Serdang, Selangor, Malaysia, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree in the Center of Research for Power Electronics, Drives, Automation and Control, Department of Electrical Engineering, University of Malaya, Kuala Lumpur. He is a Lecturer with the Department of Electrical and Electronic Engineering, UPM. His research interests are power electronics, power quality, and embedded controller applications. Nasrudin Abd. Rahim (M 89 SM 08) was born in Johor, Malaysia, in He received the B.Sc. (Hons.) and M.Sc. degrees from the University of Strathclyde, Glasgow, U.K., and the Ph.D. degree in 1995 from Heriot Watt University, Edinburgh, U.K. He is currently a Professor with the Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia, and the Director of the Center of Research for Power Electronics, Drives, Automation and Control. Dr. Rahim is a Fellow of the Institution of Engineering and Technology, U.K., and a Chartered Engineer. He is also Chairman of the Working Group WG-8, covering reluctance motors, of the IEEE Motor Subcommittee under IEEE Power Engineering Society/Electric Machinery Committee. His research interests include power electronics, real-time control systems, and electrical drives.