CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
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1 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY AC Types Feature.-V to.-v Operation and Balanced Noise Immunity at % of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Coumption Designed Specifically for High-Speed Memory Decoders and Data-Tramission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception Balanced Propagation Delays ±-ma Output Drive Current Fanout to F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds -kv ESD Protection Per MIL-STD-88, Method CDAC8...F PACKAGE CDAC8...E OR M PACKAGE (TOP VIEW) A B C GA GB G Y GND 8 V CC Y Y Y Y Y Y Y description/ordering information The AC8 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applicatio that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This mea that the effective system delay introduced by the decoders is negligible. The conditio at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A -line decoder can be implemented without external inverters, and a -line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applicatio (see Application Information). TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP E Tube CDAC8E CDAC8E Tube CDAC8M C to C SOIC M AC8M Tape and reel CDAC8M CDIP F Tube CDAC8FA CDAC8FA Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Itruments Incorporated On products compliant to MIL-PRF-8, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS
2 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS G GA GB C B A Y Y Y Y Y Y Y Y X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic diagram (positive logic) A Y Y Select Inputs B Y Y C Y Data Outputs Y Y Enable Inputs GA GB G Y POST OFFICE BOX DALLAS, TEXAS
3 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to V Input clamp current, I IK (V I < V or V I > V CC ) (see Note ) ± ma Output clamp current, I OK (V O < V or V O > V CC ) (see Note ) ± ma Continuous output current, I O (V O > V or V O < V CC ) ± ma Continuous current through V CC or GND ± ma Package thermal impedance, θ JA (see Note ): E package C/W M package C/W Storage temperature range, T stg C to C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The package thermal impedance is calculated in accordance with JESD -. recommended operating conditio (see Note ) TA = C C to C C to 8 C UNIT MIN MAX MIN MAX MIN MAX Supply voltage V =. V... VIH High-level input voltage = V... V =. V =. V... VIL Low-level input voltage = V... V =. V... VI Input voltage V VO Output voltage V IOH High-level output current =. V to. V ma IOL Low-level output current =. V to. V ma t/ v NOTE : Input traition rise or fall rate =. V to V =. V to. V All unused inputs of the device must be held at or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA. /V POST OFFICE BOX DALLAS, TEXAS
4 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = C C to C C to 8 C UNIT MIN MAX MIN MAX MIN MAX. V... IOH = µa V.... V... VOH VI = VIH or VIL IOH = ma V.8..8 V IOH = ma. V...8 IOH = ma. V.8 IOH = ma. V.8. V... IOL = µa V.... V... VOL VI = VIH or VIL IOL = ma V... V IOL = ma. V... IOL = ma. V. IOL = ma. V. II VI = or GND. V ±. ± ± µa ICC VI = or GND, IO =. V 8 8 µa Ci pf Test one output at a time, not exceeding -second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum -Ω tramission-line drive capability at 8 C and -Ω tramission-line drive capability at C. switching characteristics over recommended operating free-air temperature range, V CC =. V, C L = pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) A, B, C Any Y G Any Y GA, GB Any Y C to C C to 8 C UNIT MIN MAX MIN MAX POST OFFICE BOX DALLAS, TEXAS
5 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY switching characteristics over recommended operating free-air temperature range, V CC =. V ±. V, C L = pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) A, B, C Any Y G Any Y GA, GB Any Y C to C C to 8 C UNIT MIN MAX MIN MAX switching characteristics over recommended operating free-air temperature range, V CC = V ±. V, C L = pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) A, B, C Any Y G Any Y GA, GB Any Y C to C C to 8 C UNIT MIN MAX MIN MAX operating characteristics, V CC = V, T A = C PARAMETER TYP UNIT Cpd Power dissipation capacitance pf POST OFFICE BOX DALLAS, TEXAS
6 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = pf (see Note A) R = Ω R = Ω S GND Open TEST / tplz/tpzl tphz/tpzh S Open GND When =. V, R = R = kω LOAD CIRCUIT Input % tw VOLTAGE WAVEFORMS PULSE DURATION % V CLR Input CLK % trec % V V Reference Input Data Input % % % tsu th % % tr V % % V tf VOLTAGE WAVEFORMS RECOVERY TIME VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Input In-Phase Output Out-of-Phase Output % % % % % % VOH % % VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr % % % % % tf V % VOH VOL tr Output Control Output Waveform S at (see Note B) Output Waveform S at GND (see Note B) tpzl tpzh % % tplz % % VOL % VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES tphz V VOH 8% V NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = Ω, tr =, tf =. Phase relatiohips between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at %. E. The outputs are measured one at a time with one input traition per measurement. F. and are the same as tpd. G. tpzl and tpzh are the same as ten. H. tplz and tphz are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS
7 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS APPLICATION INFORMATION SCHS8A JANUARY REVISED FEBRUARY CDAC8 BIN/OCT & EN CDAC8 A A A A A BIN/OCT & EN 8 CDAC8 BIN/OCT & EN 8 Figure. -Bit Decoding Scheme POST OFFICE BOX DALLAS, TEXAS
8 CDAC8, CDAC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS8A JANUARY REVISED FEBRUARY APPLICATION INFORMATION CDAC8 A A A A A BIN/OCT & EN CDAC8 BIN/OCT & EN 8 CDAC8 BIN/OCT & EN 8 CDAC8 BIN/OCT & EN 8 Figure. -Bit Decoding Scheme 8 POST OFFICE BOX DALLAS, TEXAS
9 PACKAGE OPTION ADDENDUM -Jun- PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pi Package Qty Eco Plan () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) Device Marking CDAC8FA ACTIVE CDIP J TBD A N / A for Pkg Type - to CDAC8FA (/) Samples CDAC8E ACTIVE PDIP N Pb-Free (RoHS) CDAC8EE ACTIVE PDIP N Pb-Free (RoHS) CDAC8M ACTIVE SOIC D Green (RoHS & no Sb/Br) CDAC8M ACTIVE SOIC D Green (RoHS & no Sb/Br) CDAC8ME ACTIVE SOIC D Green (RoHS & no Sb/Br) CDAC8MG ACTIVE SOIC D Green (RoHS & no Sb/Br) CDAC8ME ACTIVE SOIC D Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type - to CDAC8E CU NIPDAU N / A for Pkg Type - to CDAC8E CU NIPDAU Level--C-UNLIM - to AC8M CU NIPDAU Level--C-UNLIM - to AC8M CU NIPDAU Level--C-UNLIM - to AC8M CU NIPDAU Level--C-UNLIM - to AC8M CU NIPDAU Level--C-UNLIM - to AC8M () The marketing status values are defined as follows: ACTIVE: Product device recommended for new desig. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new desig. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise coidered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) () MSL, Peak Temp. - The Moisture Seitivity Level rating according to the JEDEC industry standard classificatio, and peak solder temperature. Addendum-Page
10 PACKAGE OPTION ADDENDUM -Jun- () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be iide parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish optio. Finish optio are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers coider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CDAC8, CDAC8 : Catalog: CDAC8 Military: CDAC8 NOTE: Qualified Version Definitio: Catalog - TI's standard catalog product Military - QML certified for Military and Defee Applicatio Addendum-Page
11 PACKAGE MATERIALS INFORMATION -Jan- TAPE AND REEL INFORMATION *All dimeio are nominal Device Package Type Package Drawing Pi SPQ Reel Diameter (mm) Reel Width W (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant CDAC8M SOIC D Q CDAC8M SOIC D Q Pack Materials-Page
12 PACKAGE MATERIALS INFORMATION -Jan- *All dimeio are nominal Device Package Type Package Drawing Pi SPQ Length (mm) Width (mm) Height (mm) CDAC8M SOIC D.. 8. CDAC8M SOIC D.. 8. Pack Materials-Page
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4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
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SLCS8A OCTOBER 979 REVISED OCTOBER 99 Fast Response Times Improved Gain and Accuracy Fanout to Series 5/7 TTL Loads Strobe Capability Short-Circuit and Surge Protection Designed to Be Interchangeable With
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SN54ALS09, SN74ALS09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS SDAS084B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up
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A Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Drivers for Indicator Lamps and Relays Inputs Fully Compatible With Most
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Carry Output for n-bit Cascading Buffer-Type Outputs Drive Bus Lines Directly Choice of Asynchronous or Synchronous Clearing and Loading Internal Look-Ahead Circuitry for Fast Cascading Package Optio Include
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Operating Voltage Range of 4.5 V to 5.5 V Low Power Consumption, 80-µA Max I CC Typical t pd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µa Max Inputs Are TTL-Voltage Compatible High-Current
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LT1030C QUADRUPLE LOW-POWER LINE DRIVER Low Supply Voltage... ±5 V to ±15 V Supply Current...500 µa Typical Zero Supply Current When Shut Down Outputs Can Be Driven ±30 V Output Open When Off (3-State)
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SDAS125B MARCH 1984 REVISED DECEMBER 1994 Fully Synchronous Operation for Counting and Programming Internal Carry Look-Ahead Circuitry for Fast Counting Carry Output for n-bit Cascading Fully Independent
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Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
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Parallel-to-Serial, Serial-to-Parallel Conversions Left or Right Shifts Parallel Synchronous Loading Direct Overriding Clear Temporary Data-Latching Capability Package Options Include Plastic Small-Outline
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5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications description/ordering information The SN74CBTD3861 provides ten bits of high-speed
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Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max I CC Typical t pd = 11 ns ±6-mA Output Drive at 5 V SN54HC652...JT
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2-V to 6-V V CC Operation Wide Operating Temperature Range of 55 C to 125 C Balanced Propagation Delays and Transition Times Standard Outputs Drive up to 15 LS-TTL Loads Significant Power Reduction Compared
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Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC ) Supports Unregulated Battery Operation Down to 2.7 V Typical V OLP (Output Ground Bounce)
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www.ti.com FEATURES SN74LV138AT 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCLS691 AUGUST 2005 Inputs Are TTL-Voltage Compatible I off Supports Partial-Power Down Mode 4.5-V to 5.5-V V Operation CC Operation
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µ SLVS060K JUNE 1976 REVISED APRIL 2005 3-Terminal Regulators Output Current Up To 500 ma No External Components High Power-Dissipation Capability Internal Short-Circuit Current Limiting Output Transistor
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Controlled Baseline One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of 40 C to 105 C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification
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SN74AHCT1G02 SINGLE 2-INPUT POSITIVE-NOR GATE SCLS341K APRIL 1996 REVISED FEBRUARY 2003 Operating Range of 4.5 V to 5.5 V Max t pd of 6.5 ns at 5 V Low Power Consumption, 10-µA Max I CC ±8-mA Output Drive
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Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed
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SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L NOVEMBER 1992 REVISED JANUARY 2004 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels description/ordering information The SN74CBT3384A provides
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SDAS074B APRIL 1982 REVISED JANUARY 1995 AS1004A Offer High Capacitive-Drive Capability Driver Version of ALS04B and AS04 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
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2-V to 6-V V CC Operation Inputs Accept Voltages to 6 V Max t pd of 9 ns at 5 V SN54AC86... J OR W PACKAGE SN74AC86... D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12
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Member of the Texas Itruments Widebus Family Supports the VME64 ETL Specification Reduced TTL-Compatible Input Threshold Range High-Drive Outputs (I OH = 60 ma, I OL = 90 ma) Support Equivalent 25-Ω Incident-Wave
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Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 ma 12-Bit Array Structure Suited for Bus-Oriented Systems description/ordering information This Schottky barrier diode bus-termination
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SDAS112B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These
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SCAS528D AUGUST 1995 REVISED OCTOBER 2003 2-V to 6-V V CC Operation Inputs Accept Voltages to 6 V Max t pd of 7.5 ns at 5 V SN54AC32...J OR W PACKAGE SN74AC32... D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
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3-Terminal Regulators Output Current Up To 100 ma No External Components Required Internal Thermal-Overload Protection Internal Short-Circuit Current Limiting Direct Replacement for Industry-Standard MC79L00
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