CMOS realization of voltage differencing gain amplifier (VDGA) and its application to biquad filter

Transcription

1 Indian Journal of Enineerin & Materials Sciences Vol. 0, December 013, pp CMOS realization of voltae differencin ain amplifier (VDGA) and its application to biquad filter Jetsdaporn Satansup a & Worapon Tansrirat b * a Faculty of Enineerin, Rajamanala University of Technoloy Rattanakosin (RMUTR), Nakhon Pathom 73170, Thailand b Faculty of Enineerin, Kin Monkut s Institute of Technoloy Ladkraban (KMITL), Bankok 1050, Thailand Received April 013; accepted 14 Auust 013 A circuit realization of the voltae differencin ain amplifier (VDGA) usin only tunable transconductance cells is described in this paper. The newly defined element is conceptually a combination of the voltae differencin unit and the current-controlled voltae amplifier. The advantae feature of the proposed element is that the important transfer characteristics are electronically tunable by means of external bias currents. As application example, the resistorless realization of voltae-mode biquad filter based on the proposed VDGA is also introduced. PSPICE simulation results of the proposed circuit and its application are iven to confirm the theoretical analysis. Keywords: Voltae differencin ain amplifier (VDGA), Biquad filter, Resistorless realization, Voltae-mode circuit It is well-known fact that active elements are very important in the synthesis of sinal processin circuits, such as active filters, sinusoidal oscillators and immittance function simulators etc. Up to now, different kinds of hih-performance active elements have been introduced 1. One of them is voltae differencin buffered amplifier (VDBA),3. This element is introduced as an alternative to the existin current differencin buffered amplifier (CDBA) 4. The difference between VDBA and CDBA is that the VDBA inputs are voltae as for the CDBA inputs are current. A number of analo sinal processin/sinal eneration circuit solutions based on VDBA element have also been presented. However, the output stae of the VDBA is composed of the voltae buffer, which does not offer electronic adjustment property. Therefore, if the conventional VDBA is modified such that the voltae buffer is replaced by the tunable voltae ain amplifier, the universality of the resultin element can considerably be ained. Accordinly, let us call this element voltae differencin ain amplifier (VDGA). In this paper, we present an alternative CMOS realization scheme of VDGA. The circuit is realized based on the employment of only tunable transconductance cells as fundamental circuits. The proposed VDGA is a simplified variant of the VDBA *Correspondin author ( drworapon@yahoo.com) element by replacin the unity-ain voltae amplifier with the current-controlled voltae amplifier. This element can, therefore, be thouht of as a combination of the voltae differencin unit and the voltae ain amplifier. As an application example, the resistorless realization of an electronically tunable voltae-mode biquad filter usin the proposed VDGAs as active elements is also discussed. Computer simulation results with TSMC 0.35-µm n-well CMOS real process parameters are iven to demonstrate the characteristics of the circuit and its biquad filter application, and verify the theory. Conception of the Proposed VDGA The schematic symbol of the proposed VDGA is shown in Fi. 1. The voltae-current characteristic of the model can be described by the followin set of the circuit equations: i i 0, i v v ) and v p n w v z z m ( p n β (1) Fi 1 Circuit symbol of the VDGA

2 458 INDIAN J ENG. MATER. SCI., DECEMBER 013 where m and β denote the transconductance and voltae ain of the VDGA, respectively. It is clearly seen from Eq. (1) that the VDGA has hih-impedance terminals p, n and z, and low-impedance terminal w. The difference of the v p and v n voltaes is transformed into current i z at the z-terminal usin the transconductance m. The voltae v z on this terminal is then amplified and also transferred into voltae v w at the w-terminal by the voltae ain β. This implies that the VDGA device consists essentially of the voltae differencin unit followed by the voltae amplifier. Realization of the Proposed VDGA Fiure shows the CMOS implementation and the symbolic representation of the basic tunable transconductance cell that will be used as a fundamental circuit for realizin the proposed VDGA. The circuit is obtained from the Arbel-Goldminz transconductances 5. For this cell, the transconductance ain ( m ) is determined by the transconductance of output transistors, which can be expressed as: i o m1 m + m3 m4 () m v1 v m1 + m m3 + m4 where µ C ( W L ) I is the mi ox i i transconductance value, I B is an external DC bias current, µ is the effective carrier mobility, C ox is the ate-oxide capacitance per unit area, and W and L are the effective channel width and lenth of the i th MOS transistor (i 1,, 3, 4), respectively. It is to be noted from Eq. () that the value of m can be adjusted by bias current I B. Fiure 3 shows the possible CMOS implementation of the proposed VDGA. It consists of only three tunable transconductance cells of Fi., where the m -value of each cell corresponds to Eq. () and can be rewritten as: m k m k + m k 1 3 m4k mk (3) m1k + mk m3k + m4k In Eq. (3), mk (k A, B, C) denotes the smallsinal transconductance ain of transistor M ik. Also note that the value of mk can be controlled by I Bk. From Fi. 3, the transconductance cell M 1A -M 4A acts as the differential-input voltae to current converter with the correspondin p, n and z terminals, i.e., m ma i z /(v p -v n ), which is electronically controllable via I BA. The pair of transconductance cells M 1B -M 4B B and M 1C -M 4C is connected such that it behaves the current-controlled voltae amplifier with z and w terminals (v w βv z ). Its voltae ain β can be controlled electronically as the followin relation: vw β mb (4) vz mc where mb and mc are the m -values of the transconductance cells M 1B -M 4B and M 1C -M 4C, respectively. Accordin to Eq. (), the voltae ain β between v w and v z can be set by means of I BB and I BC. Note that hih value of β will be obtained from moderate values of this ratio. Furthermore, with matched transconductances mnb m1b mb, mpb m3b m4b, mnc m1c mc and mpc m3c m4c, the maximum β-value for the proposed VDGA iven in Fi. 3 can therefore be assumed as: ( + ) mnb mpb max β max (5) ( mnc + mpc ) min The above expression reveals that the hihest achievable value of β can be realized by settin the values of mnb and mpb maximum, while keepin the Fi Tunable transconductance cell. (a) CMOS implementation (b) symbolic representation

3 SATANSUP & TANGSRIRAT: CMOS REALIZATION OF VOLTAGE DIFFERENCING GAIN AMPLIFIER 459 mnc and mpc values minimum. Consequently, it can be concluded from the above-describin relations that the defined element has the advantae feature of electronic tunin of its important parameters ( m and β) by means of external bias currents I BA, I BB and I BC. The small-sinal input resistance seen at terminal z is iven approximately by: ( m A + o 7A)( m 4A + o 9A) rz ( + ) (6) m A oa m4 A o9a + ( + ) m4 A o4a m A o7a + ( + ) m A m4 A oa o4a where mia and oia represent the transconductance value and output conductance of the transistor M ia, respectively. The output resistance at terminal w is iven by : r w m 1C mc m3c m4c ( + ) m1c mc m3c m4c + ( + ) m3c m4c m1c mc (7) Results and Discussion The performance of the proposed VDGA of Fi. 3 has been simulated by PSPICE proram with TSMC 0.35-µm n-well CMOS real process. The aspect ratios Fi 3 Possible CMOS implementation of the proposed VDGA (W/L) of the transistors were selected as: M 1k -M k 16.1µm/0.7µm, M 3k -M 4k 8µm/0.7µm, M 5k 7µm/0.7µm, M 6k -M 7k 8.5µm/0.7µm, M 8k -M 9k 1µm/0.7µm. In simulations, the supply voltaes were chosen as: +V -V 1.5 V. To demonstrate the electronic controllability of the value of mk (k A, B, C), the variations of the mk - value by adjustin I Bk from 0 to 00 µa are plotted in Fi. 4. The DC transfer characteristics of i z aainst v p - v n of the proposed VDGA for various values of I BA (i.e., I BA 10 µa, 0 µa, 40 µa and 80 µa) are provided by Fi. 5. This choice yields the transconductance values of the VDGA as: m 190 µa/v, 70 µa/v, 380 µa/v and 540 µa/v, respectively. It can be measured from the results that the notable offset currents ( I BA /I BA ) were found to be: 0. µa, 0.47 µa, 0.95 µa and 1.78 µa, respectively. These offsets are relative difference between the currents flowin throuh the two braches of the transconductance cell (M 1A -M 4A ) in Fi. 3. With the same settin, the frequency responses of the AC transfer characteristics of the transconductance ain ( m ) between i z and (v p -v n ) are also shown in Fi. 6. The 3-dB bandwidth of the input stae of the proposed VDGA in Fi. 3 is approximately found as 100 MHz.

4 460 INDIAN J ENG. MATER. SCI., DECEMBER 013 Fiure 7 depicts the simulated output voltae waveforms from the w-terminal (v w ) of the proposed VDGA in Fi. 3. These results are obtained for four different values of I BB (i.e., I BB 10 µa, 0 µa, 40 µa, 80 µa), while I BC 10 µa and v z (t) 10 sin (π 10 6 )t mv. This settin leads to obtain β 1.0, 1.4,.0 and.8, respectively. Fiure 8 shows the AC voltae transfer characteristics from z- to w- terminals (β v w /v z ) for the same component values iven in Fi. 7. The simulated results prove that the suested circuit can exhibit an electronically tunable voltae ain over a wide current rane. Also, it can be measured that the 3-dB bandwidth in a hih frequency as nearly as 100 MHz is achieved. Application to electronically tunable biquad filter The application example of the newly defined VDGA is demonstrated on the desin of three-input sinle-output electronically tunable voltae-mode biquadratic filter. As shown in Fi. 9, the desined filter is constructed usin only two VDGAs and two floatin capacitors. Note that the floatin capacitor can easily be implemented usin advanced interated circuit (IC) technoloies. These new IC technoloies offer a second poly layer (poly), which also enables the realization of floatin capacitors as double poly (poly1-poly) capacitors 6. They are standard today and are used very commonly in analo IC desins 7,8. Thus, by employin VDGAs as active components and floatin capacitors as passive components, the proposed electronically tunable voltae-mode biquadratic filter in Fi. 9 is advantaeous from the interation point of view. Routine circuit analysis Fi 6 Frequency responses of m for different values of I BA Fi 4 Variation of mk -value as a function of I Bk (k A, B, C) Fi 7 Time domain responses of v w for different values of I BB Fi 5 DC transfer characteristics between i z and (v p v n ) for different values of I BA Fi.8 AC voltae transfer characteristics for different values of I BB

5 SATANSUP & TANGSRIRAT: CMOS REALIZATION OF VOLTAGE DIFFERENCING GAIN AMPLIFIER 461 yields the output voltae V out of the circuit as the followin expression: β1β m β1β m1 m β + + s V3 sv V1 (8) V out C β s + C m C1C β1β m1 m s + C1C where mj and β j are the parameters m and β of the j th VDGA (j 1, ). By properly selectin the relevant input voltae, the filter of Fi. 9 can realize all the five standard biquadratic filterin functions, namely lowpass (LP), bandpass (BP), hihpass (HP), bandstop (BS) and allpass (AP) from the same circuit confiuration, indicated as follows: (i) If V 1 V in (an input voltae sinal) and V V 3 0 (rounded), the LP response can be realized with the passband ain H LP 1. (ii) If V V in and V 1 V 3 0, the BP response can be realized with the passband ain H BP β 1. (iii) If V 3 V in and V 1 V 0, the HP response can be realized with the passband ain H HP β. (iv) If V 1 V 3 V in, V 0 and β 1, the BS response can be realized with the passband ain H BS 1. (v) If V 1 -V V 3 V in and β 1 β 1, the AP response can be realized with the passband ain H AP 1. It may be noted that BS and AP filter realizations require the input-sinal matchin conditions. In case of the inequality, if V 1 > β V 3, the filter of Fi. 9 will perform a lowpass notch biquad. On the other hand, if V 1 < β V 3, the filter performs a hihpass notch biquad. In all responses, the natural anular frequency (ω 0 ) and the quality factor (Q) for β 1 mb1 / mc1 and β mb / mc can be iven respectively by: m1 m mb1 mb ω 0 (9) C C and Q mc1 m mc mc1 1 m1 mb1 mc (10) mb C C From Eqs (9) and (10), it can be clearly observed that the active and passive sensitivities are all halved in manitude. Moreover, by takin m m1 m, mh mb1 mc, ml mb mc1 and C C 1 C, Eqs (9) and (10) turn to: m ω 0 (11) C mh and Q (1) ml Note that the ω 0 can be tuned electronically by chanin m without disturbin Q. Analoously, the Q-value can be adjusted independently by controllin the transconductance ratio mh / ml. To verify the theoretical analyses, the circuit of Fi. 9 has been desined for f 0 ω 0 /π 3 MHz and Q 1, by takin the values of components: I BAk I BBk I BCk 40 µa ( mk 380 µa/v and β k 1) and C 1 C 0 pf. Fiure 10 presents the simulated LP, BP, 1 Fi 9 Electronically tunable biquadratic filter usin VDGAs Fi 10 Amplitude-frequency responses of LP, BP, HP and BS for the desined filter of Fi.9 Fi 11 Amplitude and phase-frequency responses for the AP filter in Fi.9

6 46 INDIAN J ENG. MATER. SCI., DECEMBER 013 HP and BS amplitude-frequency responses of the filter in Fi. 9. The simulated AP amplitude and phase-frequency responses are also shown in Fi. 11. The simulated f 0 is located at about.9 MHz. As can be seen, there is a close areement between simulation and theory. Fiure 1 shows the simulated BP response with f 0 - tunin (i.e., f MHz,.15 MHz, 3.03 MHz and 4.30 MHz). In this case, the bias currents I BA ( I BA1 I BA ) were adjusted to the values of 10 µa, 0 µa, 40 µa and 80 µa, respectively, while keepin I BB1 I BB I BC1 I BC 10 µa for Q 1. It can be seen that the f 0 is tuned by means of I BA. In Fi.13, the orthoonal controllability of the Q-value of the BP filter is demonstrated by keepin the values of I BA I BA1 I BA 40 µa (f MHz) and I BB I BC1 10 µa, and varyin only I BB1 I BC 10 µa (Q 1), 0 µa (Q 1.4), 40 µa (Q.0) and 80 µa (Q.8), respectively. As can be observed from both fiures, there are deviations occurred in the filter responses at hih frequency. This is due to the fact that, in case of BP filter realization, the input sinal voltae (V in ) is injected to the z-terminal of the VDGA1 throuh the floatin capacitor C 1. This capacitor toether with parasitic impedances at the correspondin z-terminal will introduced an extra parasitic pole. This can explain why the BP filter responses in Fis 1 and 13 have non-ideal ain responses at hih frequencies. However, this effect can be reduced by choosin smaller loadin capacitor. In addition, time domain simulation results for the BP response of the proposed filter in Fi. 9 are shown in Fi. 14, in which a 3-MHz sinusoidal input current sinal with 100 mv peak value is applied to the filter. Furthermore, the total harmonic distortion (THD) variations of BP response on the amplitude of the sinusoidal input current sinal at 3 MHz are plotted in Fi. 15. The results obtained indicate that the THD values of the circuit remain below 3% for sinusoidal input sinals up to 100 mv peak. In conclusion of this study, we have made a topoloy comparison amon the previously reported multi-input sinle-output (MISO) voltae-mode biquads 3,9-3 and the presented biquad in Fi. 9. The summarized results are iven in Table 1. From the table, it reveals that, amon the topoloies under comparison, the presented filter in Fi. 9 is the special one that simultaneously provides the followin benefit features: resistor-free and canonical structure, simultaneous realization of all the five standard Fi 1 Amplitude-frequency responses of the BP filter when f 0 is varied Fi 14 Time-domain response of the BP filter in Fi.9 at f 0 3 MHz Fi 13 Amplitude-frequency responses of the BP filter when Q is varied Fi 15 THD variation of the BP filter in Fi.9 at f 0 3 MHz

7 SATANSUP & TANGSRIRAT: CMOS REALIZATION OF VOLTAGE DIFFERENCING GAIN AMPLIFIER 463 Filters [Ref] Table 1 Comparison of the proposed filter with previously available MISO-type voltae-mode biquads No. of Active components No. of passive components Availability of LP, BP, HP, BS and AP responses Electronic tunin Properties Independent control of ω 0 and Q Technoloies Power supplies Power dissipation [3] VDBA C yes yes no TSMC 0.35µm ±1.5 V 0.97 Mw VDBA R 1, C yes yes yes (1 VDBA) [9] DDCC R, C yes no no 0.5 µm process ±3.3 V N/A [10] DDCC 3 R, C yes no no TSMC 0.35µm ±1.65 V N/A [11] CDBA R 4, C yes no no AD844 ±1 V N/A [1] FDCCII R, C yes no no N/A N/A N/A [13] DDCC C no yes no TSMC 0.35µm ±1.65 V 83 mw 1,OTA [14] DDCC 3 R, C yes no no TSMC 0.18µm ±1.5 V N/A [15] CCCDBA C yes yes no ALA400 ±3 V N/A [16] CFOA R 3, C yes no no AD844 ±1 V N/A [17] CFOA 4 R 5, C yes no yes AD844 ±5 V N/A [18] DVCC 3 R 3, C yes no yes TSMC 0.35µm ±1.5 V 3.47 mw [19] CCCII C yes yes no AMS 0.35µm ±.5 V N/A [0] DVCC 3 R 4, C yes no no TSMC 0.18µm ±1.5 V 4.7 mw [1] CFOA 3 R 5, C yes no yes AD844 ±5 V N/A [] CDBA 1 R 4, C yes no yes AD844 ±1 V N/A [3] CDBA R 4, C yes no yes AD844 ±1 V N/A Proposed VDGA C yes yes yes TSMC 0.35µm ±1.5 V.18 mw DDCC : Differential difference current conveyor, DVCC : Differential voltae current conveyor, FDCCII : Fully differential current conveyor, OTA : Operational transconductance amplifier, CCCDBA : Current-controlled CDBA, CFOA : Current-feedback operational amplifier. biquadratic filterin functions, and independent electronic tunin of ω 0 and Q. Conclusions A eneralized active buildin block for analo sinal processin, namely, VDGA is introduced in this work. The proposed block is implemented usin only tunable transconductance cells. The VDGAbased application on the three-input sinle-output voltae-mode biquadratic filter realization with electronically tunable and resistor-free features has also been presented. Two VDGAs toether with only two capacitors are used to realize the desined filter. It has been demonstrated that ω 0 and Q of the filter can be adjusted electronically throuh the parameters m and β of the VDGA. The feasibility of the VDGA and its application are verified by simulation results. Acknowledement This research work is financial supported by Rajamanala University of Technoloy Rattanakosin (RMUTR), Thailand. References 1 Biolek D, Senani R, Biolkova V & Kolka Z, Radioenineerin, 17 (008) Biolkova V, Kolka Z & Biolek D, Fully balanced voltae differencin buffered amplifier and its applications, Proc of The 5 nd MWSCAS, Cancun, Mexico, Kacar F, Yesil A & Noori A, Radioenineerin, 1 (01) Acar C & Ozouz S, Microelectron J, 30 (1999) Arbel A F & Goldminz L, Analo Inter Circ Si Process, (199) Baker R J, Li H W & Boyce D E, CMOS Circuit Desin, Layout, and Simulation, Chapter 3, (IEEE Press, New York, USA), Toker A, Ozcan S, Kuntman H & Cicekolu O, Int J Electron, 88 (001) Ibrahim M A, Kuntman H & Cicekolu O, Circuits Syst Sinal Process, (003) Chan C M & Chen H P, Int J Electron, 90 (003) Chiu W Y & Horn J W, IEEE Trans Circuits Syst II : Express Briefs, 54 (007) Tansrirat W, Pukkalanun T & Surakampontorn W, Active and Passive Electronic Components, 008 (008), Article ID 47171, 6 paes, doi: /008/ Chen H P, Int J Electron Commun (AEU), 6 (008) Lee W T & Liao Y Z, Int J Electron Commun (AEU), 6 (008) Horn J W, Circuits Syst Sinal Process, 7 (008) Tansrirat W, Indian J Pure & Appl Phys, 47 (009) Tansrirat W & Surakampontorn W, Int J Electron Commun (AEU), 63 (009) Nikoloudis S & Psychalinos C, Circuits Syst Sinal Process, 9 (010)

8 464 INDIAN J ENG. MATER. SCI., DECEMBER Minaei S & Yuce E, Circuits Syst Sinal Process, 9 (010) Ranjan A & Paul S, Active and Passive Electronic Components, 011 (011), Article ID 43905, 5 paes, doi: /011/ Horn J W, Hsu C H & Tsen C Y, Radioenineerin, 1 (01) Topalolu S, Sabas M & Anday F, Int J Electron Commun (AEU), 66 (01) Bashir S A & Shah N A, Circuits Syst, 3 (01) Pathak J K, Sinh A K & Senani R, ISRN Electronics, 013 (013), Article ID , 6 paes,