M48Z58 M48Z58Y. 5 V, 64 Kbit (8 Kbit x 8) ZEROPOWER SRAM. Features

Transcription

1 M48Z58 M48Z58Y 5 V, 64 Kbit (8 Kbit x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages: (V PFD = power-fail deselect voltage) M48Z58: V CC = 4.75 to 5.5 V; 4.5 V V PFD 4.75 V M48Z58Y: V CC = 4.5 to 5.5 V; 4.2 V V PFD 4.5 V Self-contained battery in the CAPHAT DIP package Packaging includes a 28-lead SOIC and SNAPHAT top (to be ordered separately) SOIC package provides direct connection for a SNAPHAT top which contains the battery Pin and function compatible with JEDEC standard 8 Kbit x 8 SRAMs RoHS compliant Lead-free second level interconnect 28 1 PCDIP28 battery CAPHAT 28 SNAPHAT battery 1 SOH28 June 2011 Doc ID 2559 Rev 11 1/24 1

2 Contents M48Z58, M48Z58Y Contents 1 Description Operating modes READ mode WRITE mode Data retention mode V CC noise and negative going transients Maximum ratings DC and AC parameters Package mechanical data Part numbering Environmental information Revision history /24 Doc ID 2559 Rev 11

3 M48Z58, M48Z58Y List of tables List of tables Table 1. Signal names Table 2. Operating modes Table 3. READ mode AC characteristics Table 4. WRITE mode AC characteristics Table 5. Absolute maximum ratings Table 6. Operating and AC measurement conditions Table 7. Capacitance Table 8. DC characteristics Table 9. Power down/up AC characteristics Table 10. Power down/up trip points DC characteristics Table 11. PCDIP28 28-pin plastic DIP, battery CAPHAT, pack. mech. data Table 12. SOH28 28-lead plastic small outline, battery SNAPHAT, pack. mech. data Table 13. SH 4-pin SNAPHAT housing for 48 mah battery, package mech. data Table 14. SH 4-pin SNAPHAT housing for 120 mah battery, pack. mech. data Table 15. Ordering information scheme Table 16. SNAPHAT battery table Table 17. Document revision history Doc ID 2559 Rev 11 3/24

4 List of figures M48Z58, M48Z58Y List of figures Figure 1. Logic diagram Figure 2. DIP connections Figure 3. SOIC connections Figure 4. Block diagram Figure 5. READ mode AC waveforms Figure 6. WRITE enable controlled, WRITE mode AC waveforms Figure 7. Chip enable controlled, WRITE mode AC waveforms Figure 8. Supply voltage protection Figure 9. AC measurement load circuit Figure 10. Power down/up mode AC waveforms Figure 11. PCDIP28 28-pin plastic DIP, battery CAPHAT, package outline Figure 12. SOH28 28-lead plastic small outline, battery SNAPHAT, pack. outline Figure 13. SH 4-pin SNAPHAT housing for 48 mah battery, package outline Figure 14. SH 4-pin SNAPHAT housing for 120 mah battery, package outline Figure 15. Recycling symbols /24 Doc ID 2559 Rev 11

5 M48Z58, M48Z58Y Description 1 Description The M48Z58/Y ZEROPOWER RAM is an 8 Kbit x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory solution. The M48Z58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600 mil DIP CAPHAT houses the M48Z58/Y silicon with a long life lithium button cell in a single package. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is M4Z28- BR00SH1. Figure 1. Logic diagram VCC A0-A DQ0-DQ7 W E M48Z58 M48Z58Y G V SS AI01176B Doc ID 2559 Rev 11 5/24

6 Description M48Z58, M48Z58Y Table 1. Signal names A0-A12 DQ0-DQ7 E G W V CC V SS NC Address inputs Data inputs / outputs Chip enable input Output enable input WRITE enable input Supply voltage Ground Not connected internally Figure 2. DIP connections NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS M48Z58 M48Z58Y VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI01177B Figure 3. SOIC connections NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS M48Z58Y VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI01178B 6/24 Doc ID 2559 Rev 11

7 M48Z58, M48Z58Y Description Figure 4. Block diagram A0-A12 LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY POWER V PFD 8K x 8 SRAM ARRAY DQ0-DQ7 E W G V CC V SS AI01394 Doc ID 2559 Rev 11 7/24

8 Operating modes M48Z58, M48Z58Y 2 Operating modes The M48Z58/Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V CC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V CC. As V CC falls below battery switchover voltage (V SO ), the control circuitry connects the battery which maintains data until valid power returns. Table 2. Operating modes Mode V CC E G W DQ0-DQ7 Power Deselect V IH X X High Z Standby 4.75 to 5.5 V WRITE V IL X V IL D IN Active or READ V 4.5 to 5.5 V IL V IL V IH D OUT Active READ V IL V IH V IH High Z Active Deselect V SO to V PFD (min) (1) X X X High Z CMOS standby Deselect (1) V SO X X X High Z Battery backup mode Note: 1. See Table 10 on page 16 for details. X = V IH or V IL ; V SO = Battery backup switchover voltage. 2.1 READ mode The M48Z58/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable) is low. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t AVQV ) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t ELQV ) or output enable access time (t GLQV ). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an indeterminate state until t AVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t AXQX ) but will go indeterminate until the next address access. 8/24 Doc ID 2559 Rev 11

9 M48Z58, M48Z58Y Operating modes Figure 5. READ mode AC waveforms tavav A0-A12 VALID tavqv telqv taxqx tehqz E telqx tglqv tghqz G tglqx DQ0-DQ7 VALID AI01385 Note: WRITE enable (W) = High. Table 3. READ mode AC characteristics Symbol Parameter (1) Min M48Z58/Y Max Unit t AVAV READ cycle time 70 ns t AVQV Address valid to output valid 70 ns t ELQV Chip enable low to output valid 70 ns t GLQV Output enable low to output valid 35 ns (2) t ELQX Chip enable low to output transition 5 ns (2) t GLQX Output enable low to output transition 5 ns (2) t EHQZ Chip enable high to output Hi-Z 25 ns t (2) GHQZ Output enable high to output Hi-Z 25 ns t AXQX Address transition to output transition 10 ns 1. Valid for ambient operating temperature: T A = 0 to 70 C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. C L = 5 pf (see Figure 9 on page 14). 2.2 WRITE mode The M48Z58/Y is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t EHAX from chip enable or t WHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t DVWH prior to the end of WRITE and remain valid for t WHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t WLQZ after W falls. Doc ID 2559 Rev 11 9/24

10 Operating modes M48Z58, M48Z58Y Figure 6. WRITE enable controlled, WRITE mode AC waveforms tavav A0-A12 VALID tavwh tavel twhax E twlwh tavwl W twlqz twhqx twhdx DQ0-DQ7 DATA INPUT tdvwh AI01386 Figure 7. Chip enable controlled, WRITE mode AC waveforms tavav A0-A12 VALID tavel taveh teleh tehax E tavwl W tehdx DQ0-DQ7 DATA INPUT tdveh AI01387B 10/24 Doc ID 2559 Rev 11

11 M48Z58, M48Z58Y Operating modes Table 4. WRITE mode AC characteristics Symbol Parameter (1) Min M48Z58/Y Max Unit t AVAV WRITE cycle time 70 ns t AVWL Address valid to WRITE enable low 0 ns t AVEL Address valid to chip enable low 0 ns t WLWH WRITE enable pulse width 50 ns t ELEH Chip enable low to chip enable high 55 ns t WHAX WRITE enable high to address transition 0 ns t EHAX Chip enable high to address transition 0 ns t DVWH Input valid to WRITE enable high 30 ns t DVEH Input valid to chip enable high 30 ns t WHDX WRITE enable high to input transition 5 ns t EHDX Chip enable high to input transition 5 ns (2)(3) t WLQZ WRITE enable low to output Hi-Z 25 ns t AVWH Address valid to WRITE enable high 60 ns t AVEH Address valid to chip enable high 60 ns t (2)(3) WHQX WRITE enable high to output transition 5 ns 1. Valid for ambient operating temperature: T A = 0 to 70 C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. C L = 5 pf (see Figure 9 on page 14). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 2.3 Data retention mode With valid V CC applied, the M48Z58/Y operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V CC falls within the V PFD (max), V PFD (min) window. All outputs become high impedance, and all inputs are treated as Don't care. Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V PFD (min), the user can be assured the memory will be in a write protected state, provided the V CC fall time is not less than t F. The M48Z58/Y may respond to transient noise spikes on V CC that reach into the deselect window during the time the device is sampling V CC. Therefore, decoupling of the power supply lines is recommended. When V CC drops below V SO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z58/Y for an accumulated period of at least 10 years when V CC is less than V SO. As system power returns and V CC rises above V SO, the battery is disconnected, and the power supply is switched to external V CC. Normal RAM operation can resume t rec after V CC exceeds V PFD (max). For more information on battery storage life refer to the application note AN1012. Doc ID 2559 Rev 11 11/24

12 Operating modes M48Z58, M48Z58Y 2.4 V CC noise and negative going transients I CC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V CC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µf (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from V CC to V SS (cathode connected to V CC, anode to V SS ). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 8. Supply voltage protection V CC V CC 0.1µF DEVICE V SS AI /24 Doc ID 2559 Rev 11

13 M48Z58, M48Z58Y Maximum ratings 3 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Value Unit T A Ambient operating temperature 0 to 70 C SNAPHAT top 40 to 85 C T STG Storage temperature (V CC off, oscillator off) CAPHAT DIP 40 to 85 C SOH28 55 to 125 C (1)(2) T SLD Lead solder temperature for 10 seconds 260 C V IO Input or output voltages 0.3 to 7.0 V V CC Supply voltage 0.3 to 7.0 V I O Output current 20 ma P D Power dissipation 1 W Caution: Caution: 1. For DIP package, soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. 2. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 C (the time above 255 C must not exceed 30 seconds). Negative undershoots below 0.3 V are not allowed on any pin while in the battery backup mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Doc ID 2559 Rev 11 13/24

14 DC and AC parameters M48Z58, M48Z58Y 4 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter M48Z58 M48Z58Y Unit Supply voltage (V CC ) 4.75 to to 5.5 V Ambient operating temperature (T A ) 0 to 70 0 to 70 C Load capacitance (C L ) pf Input rise and fall times 5 5 ns Input pulse voltages 0 to 3 0 to 3 V Input and output timing ref. voltages V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC measurement load circuit 5V 1.9kΩ DEVICE UNDER TEST OUT 1kΩ C L = 100pF or 5pF C L includes JIG capacitance AI01030 Table 7. Capacitance Symbol Parameter (1)(2) Min Max Unit C IN Input capacitance - 10 pf (3) C IO Input / output capacitance - 10 pf 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected. 14/24 Doc ID 2559 Rev 11

15 M48Z58, M48Z58Y DC and AC parameters Table 8. DC characteristics Symbol Parameter Test condition (1) Min Max Unit I LI Input leakage current 0 V V IN V CC ±1 µa (2) I LO Output leakage current 0 V V OUT V CC ±1 µa I CC Supply current Outputs open 50 ma I CC1 Supply current (standby) TTL E = V IH 3 ma I CC2 Supply current (standby) CMOS E = V CC 0.2 V 3 ma V IL Input low voltage V V IH Input high voltage 2.2 V CC V V OL Output low voltage I OL = 2.1 ma 0.4 V V OH Output high voltage I OH = 1 ma 2.4 V 1. Valid for ambient operating temperature: T A = 0 to 70 C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. Outputs deselected. Figure 10. Power down/up mode AC waveforms V CC V PFD (max) V PFD (min) V SO tpd tf tfb tdr trb tr trec INPUTS RECOGNIZED DON'T CARE RECOGNIZED OUTPUTS VALID HIGH-Z VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI01168C Doc ID 2559 Rev 11 15/24

16 DC and AC parameters M48Z58, M48Z58Y Table 9. Power down/up AC characteristics Symbol Parameter (1) Min Max Unit t PD E or W at V IH before power down 0 µs (2) t F V PFD (max) to V PFD (min) V CC fall time 300 µs (3) t FB V PFD (min) to V SS V CC fall time 10 µs t R V PFD (min) to V PFD (max) V CC rise time 10 µs t RB V SS to V PFD (min) V CC rise time 1 µs t rec V PFD (max) to inputs recognized ms 1. Valid for ambient operating temperature: T A = 0 to 70 C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. V PFD (max) to V PFD (min) fall time of less than t F may result in deselection/write protection not occurring until 200 µs after V CC passes V PFD (min). 3. V PFD (min) to V SS fall time of less than t FB may cause corruption of RAM data. Table 10. Power down/up trip points DC characteristics Symbol Parameter (1)(2) Min Typ Max Unit M48Z V V PFD Power-fail deselect voltage M48Z58Y V V SO Battery backup switchover voltage 3.0 V (3) t DR Expected data retention time 10 Years 1. All voltages referenced to V SS. 2. Valid for ambient operating temperature: T A = 0 to 70 C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 3. At 25 C, V CC = 0 V. 16/24 Doc ID 2559 Rev 11

17 M48Z58, M48Z58Y Package mechanical data 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. Figure 11. PCDIP28 28-pin plastic DIP, battery CAPHAT, package outline A2 A A1 L C B1 B e1 e3 ea D N E 1 PCDIP Note: Drawing is not to scale. Table 11. PCDIP28 28-pin plastic DIP, battery CAPHAT, pack. mech. data mm inches Symbol Typ Min Max Typ Min Max A A A B B C D E e e ea L N Doc ID 2559 Rev 11 17/24

18 Package mechanical data M48Z58, M48Z58Y Figure 12. SOH28 28-lead plastic small outline, battery SNAPHAT, pack. outline B e A2 CP A eb C N D E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 12. Symbol SOH28 28-lead plastic small outline, battery SNAPHAT, pack. mech. data mm inches Typ Min Max Typ Min Max A A A B C D E e eb H L a N CP /24 Doc ID 2559 Rev 11

19 M48Z58, M48Z58Y Package mechanical data Figure 13. SH 4-pin SNAPHAT housing for 48 mah battery, package outline A1 A A3 A2 ea D B eb L E SHZP-A Note: Drawing is not to scale. Table 13. SH 4-pin SNAPHAT housing for 48 mah battery, package mech. data mm inches Symbol Typ Min Max Typ Min Max A A A A B D E ea eb L Doc ID 2559 Rev 11 19/24

20 Package mechanical data M48Z58, M48Z58Y Figure 14. SH 4-pin SNAPHAT housing for 120 mah battery, package outline A1 A A3 A2 ea D B eb L E SHZP-A Note: Drawing is not to scale. Table 14. SH 4-pin SNAPHAT housing for 120 mah battery, pack. mech. data mm inches Symb Typ Min Max Typ Min Max A A A A B D E ea eb L /24 Doc ID 2559 Rev 11

21 M48Z58, M48Z58Y Part numbering 6 Part numbering Table 15. Ordering information scheme Example: M48Z 58Y 70 MH 1 E Device type M48Z Supply voltage and write protect voltage 58 (1) = V CC = 4.75 to 5.5 V; V PFD = 4.5 to 4.75 V 58Y = V CC = 4.5 to 5.5 V; V PFD = 4.2 to 4.5 V Speed 70 = 70 ns (for M48Z58/Y) Package PC = PCDIP28 MH (2) = SOH28 Temperature range 1 = 0 to 70 C Shipping method For SOH28: E = ECOPACK package, tubes F = ECOPACK package, tape & reel For PCDIP28: blank = ECOPACK package, tubes 1. The M48Z58 part is offered with the PCDIP28 (ie., CAPHAT ) package only. 2. The SOIC package (SOH28) requires the SNAPHAT battery package which is ordered separately under the part number M4Zxx-BR00SH1 in plastic tubes (see Table 16). Caution: Do not place the SNAPHAT battery package M4Zxx-BR00SH1 in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 16. SNAPHAT battery table Part number Description Package M4Z28-BR00SH1 Lithium battery (48 mah) SNAPHAT SH M4Z32-BR00SH1 Lithium battery (120 mah) SNAPHAT SH Doc ID 2559 Rev 11 21/24

22 Environmental information M48Z58, M48Z58Y 7 Environmental information Figure 15. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. 22/24 Doc ID 2559 Rev 11

23 M48Z58, M48Z58Y Revision history 8 Revision history Table 17. Document revision history Date Revision Changes March First issue 10-Feb socket SOH and 2-pin SH packages removed 22-Feb Data retention mode paragraph changed 14-Sep Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10) 29-May Modify reflow time and temperature footnotes (Table 5) 16-Sep Remove footnote from ordering information (Table 15) 02-Apr v2.2 template applied; test condition updated (Table 10) 23-Mar Reformatted; updated lead-free information (Table 5, 15) 23-Nov Remove references to industrial temperature grade (Table 3, 4, 5, 6, 8, 9, 10, 15) 09-Jun Removal of SNAPHAT, industrial temperature sales types (Table 3, 4, 5, 6, 7, 8, 10, 15) 14-Dec Updated lead-free text (Table 15) 06-Nov Reformatted; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table 5, 15, Mar Updated Table 5, text in Section 5: Package mechanical data; added Section 7: Environmental information; minor reformatting. 14-Oct Updated Section 3, Table 11; reformatted document. 07-Jun Updated footnote 1 of Table 5: Absolute maximum ratings; updated Section 7: Environmental information. Doc ID 2559 Rev 11 23/24

24 M48Z58, M48Z58Y Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 24/24 Doc ID 2559 Rev 11