PI6LC4830. HiFlex TM Network Clock Generator. Features. Description. Pin Configuration. Block Diagram
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1 IN_SEL PI6LC4830 Features ÎÎ3.3V supply voltage ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function ÎÎ1 LVCMOS 100/50MHz selectable ÎÎ25MHz crystal or differential input ÎÎLow 1ps RMS max integrated phase noise design ÎÎPLL Bypass mode for test ÎÎ32 lead 5x5mm TQFN package Description The PI6LC4830 is an LC VCO based low phase noise design intended for the most demanding PCIe 2.0 applications. Use of the ultra-low noise LC VCO allows for much greater noise margins than traditional solutions. This is ideal for noisy environments. Pin Configuration VDDA_PLL VDD QA_OE VDD_Out IREF QA0+ QA0- GND PLL_Byps 1 24 QA1+ REF_OUT_OE 2 23 QA1- QB_OE QB_DIV2 VDD_PLL GND VDD_Out QA2+ QA2- IN GND IN- VDD_REF_Out QA_CMOS VDD_OutA_SE Block Diagram REF_OUT+ REF_OUT- X1 X2 VDD_OSC VDD_OutB_SE QB_CMOS PLL_Byps REF_OUT_OE REF_OUT IN_SEL QA0:QA2 100MHz HCSL Outputs OSC IN+ IN- PLL /R QA_CMOS QA_OE /2 QB_CMOS QB_DIV2 QB_OE 1
2 Pin Description Pin Number Pin Name Type Description 20, 21, 23, 24, 26, 27 QA0+, QA0-, QA1+, QA1-, QA2+, QA2- Output (HCSL) 9, 10 REF_Out+, REF_Out- Output (LVPECL) 100MHz HCSL Outputs 12 X1 Input Crystal input pin 13 X2 Output Oscillator output pin 25MHz LVPECL output from fundamental oscillator core 6, 7 IN+, IN- Input (Differential) HCSL/LVPECL/LVDS inputs 11 IN_SEL Input (LVCMOS) 1 PLL_Byps Input (LVCMOS) 30, 3 QA_OE, QB_OE Input (LVCMOS) 14 V DD _OSC Power Power for xtal Osc core Low selects X1 and X2, High selects In+, In-. Internal pull up is 100k Ohms If Low, output buffers are switched to the PLL. If High, output buffers are switched to the input mux. Internal 100K-Ohm pulldown. Low enables outputs, High selects high impedance mode. Internal 100K-Ohm pulldown 5 V DD _PLL Power Power for digital portion of PLL circuitry 22, 29 V DD _Out Power Power for output buffers 32 V DDA _PLL Power Power for analog core of PLL 19, 25 GND Power Ground 18 QA_CMOS Output (LVCMOS) 100MHz LVCMOS Output 16 QB_CMOS Output (LVCMOS) 100/50MHz Selectable LVCMOS Output 17 V DD _OutA_SE Power Bank A LVCMOS Power 15 V DD _OutB_SE Power Bank B LVCMOS Power 4 QB_DIV2 Input (LVCMOS) High selects 50MHz, Low selects 100MHz. Internal 100K-Ohm pull-up 28 I REF Output External resistor connection for internal current reference 8 V DD _REF_OUT Power Power for reference output 2 REF_OUT_OE Input (LVCMOS) Low enables outputs, High selects high impedance mode. Internal 100K-Ohm pull-down. 31 V DD Power Power for Core 2
3 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Stresses greater than those listed under MAXIMUM Storage temperature ºC to +155ºC RATINGS may cause permanent damage to the device. This 3.3V Analog Supply Voltage to +4.6V is a stress rating only and functional operation of the device ESD Protection (HBM) V at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Conditions (Over Operating Conditions) Symbol Parameters Conditions Min. Max. Units V DD_PLL PLL Power Supply Voltage V DD_REF_Out Power Supply for Reference Out V DD_OSC Power Supply Voltage for oscillator core V DD_OutA, OutB Power Supply Voltage for Bank A V and Bank B V DD_Out Power Supply Voltage for Output Buffer V DD 3.3V General Power Supply Voltage V DDA_PLL Analog PLL Power Supply Voltage T A Ambient Temperature C I DD_PLL PLL Power Supply Current At 3.6V, loaded 10 I DD_REF_OUT Current for Reference Out At 3.6V, loaded 36 I DD_OSC Current for Oscillator At 3.6V, loaded 12 I DD_OUTA, OUTB Current for Bank A and Bank B At 3.6V, loaded 11 I DD_OUT Current for Output Buffer At 3.6V, loaded 76 ma I DDA _PLL Analog PLL Current, V DDA_PLL At 3.6V, loaded 35 No load (Analog PLL Current Included) 85 I DD Total Power Supply Current All outputs loaded (Analog PLL Current Included) 180 P Diss Power Dissipation All outputs loaded 0.65 W 3
4 LVCMOS DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Conditions Min. Typ. Max. Units V IH Input High Voltage 2 V DD V IL Input Low Voltage V OH Output High Voltage I OH = -8mA V DD V OL Output Low Voltage I OL = 8mA 0.4 I IH I IL Input High Current for QA_OE, QB_OE, REF_OUT_OE, PLL_Byps V IN = V DD 45 IN_SEL, QB_DIV2 5 Input Low Current for QA_OE, QB_OE, REF_OUT_OE, PLL_Byps V IN = 0V -5 IN_SEL, QB_DIV2-45 R pu Internal pull up resistance 105 kohm R dn Internal pull down resistance 105 kohm Z O Output Impedance 30 Ohm C IN Input Capacitance for X1, X2 inputs 4 pf V μa LVCMOS AC Characteristics (Over Operating Conditions) Symbol Parameter Conditions Min. Typ. Max. Units f error Frequency Synthesis Error 0 ppm T r /T f Output Rise/Fall time 20% to 80%, C L = 10pF ns T DC Output Duty Cycle t DC = t H /t CY, t H = High Pulse Width, t CY = Output Cycle V DD / % J CC Jitter, Cycle-to-Cycle 175 J phase Rms Phase jitter from 12kHz - 20MHz ps T EN/DIS Output enable/disable time 80 ns T LOCK PLL Lock Time 5 ms 4
5 Differential DC Input Characteristics (Over Operating Conditions) Symbol Parameters Conditions Min. Typ. Max. Units I IH Input High IN- V IN = V DD = 3.465V 5 Current IN+ V IN = V DD = 3.465V 45 I IL Input Low IN- V IN = 0V -45 Current IN+ V IN = 0V -5 V CMR Common Mode Voltage Range 0.5 V DD V V PP Peak-to-Peak Input Voltage Swing ua V HCSL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Condition Min. Typ. Max. Units V OH Output High Voltage VDD_OUT = V DD -0.15V (1) V OL Output Low Voltage 150 V CROSS Absolute Crossing Point Voltages mv D V CROSS Total variation of V CROSS overall edges 140 IOH Output High Current w/ 475-Ohm resistor. Connected between IREF pin and GND 14 ma Note: 1. This voltage drop is to account for the voltage across the series resistor in the layout guidelines. HCSL AC Output Switching Characteristics(1,2,3) (Over Operating Conditions) Symbol Parameters Min Typ Max. Units Notes f error Frequency Synthesis Error 0 ppm T rise / T fall Rise and Fall Time (measured between 0.175V to 0.525V) ΔT rise / ΔT fall Rise and Fall Time Variation ps 2 T skew Output-to-Output Skew T DC Duty Cycle (Measured at 100 MHz) % 3 J phase RMS phase jitter from 12kHz - 20MHz ps T HF-RMS >1.5MHz - 50MHz RMS jitter applying PCIE G2 jitter mask PSR Power Supply Rejection with -30dBm input sine wave 100kHz to 600kHz -46 dbc 2 T EN/DIS Output enable/disable time 80 ns T LOCK PLL Lock Time 5 ms Notes: 1. Test configuration is RS = 33Ω, Rp = 49.9Ω with 2pF load. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform. 5
6 LVPECL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Condition Min. Typ. Max. Units V PP Output peak-peak Voltage V DD_REF_Out = 3.3± 5% V OH Output High Voltage V DD_REF_Out = 3.3± 5% V DD -1.4 V DD -0.9 V V OL Output Low Voltage V DD_REF_Out = 3.3± 5% V DD -2.0 V DD -1.7 AC LVPECL Switching Characteristics Symbol Parameters Condition Min. Typ. Max. Units T rise / T fall Rise and Fall Time 20% to 80%, singleended ps T DC Duty Cycle Differential % T EN/DIS Output enable/disable time 100 ns Crystal Characteristic (link to " for more detailed crystal specifications) Parameters Description Min Typ Max. Units OSCmode Mode of Oscillation Fundamental FREQ Frequency 25 MHz ESR (1) Equivalent Series Resistance 50 Ohm Cload Load Capacitance 18 Cshunt Shunt Capacitance 7 pf DRIVE level 1 mw Note: 1. ESR value is dependent upon frequency of oscillation Application Notes Crystal circuit connection The following diagram shows PI6LC4830 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit C1 27pF XTAL_IN Crystal (C L = 18pF) C2 33pF XTAL_OUT 6
7 Recommended Crystal Specification Pericom recommends: a) GC XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, b) FY , SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, c) FL , SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, HCSL output buffer characteristics V DD R O Slope ~ 1/Rs I OUT R OS Iout V OUT = 0.90V max 0V 0.90V Figure 9. Simplified diagram of current-mode output buffer HCSL Buffer characteristics Symbol Minimum Maximum R O 3000Ω N/A R OS unspecified unspecified V OUT N/A 900mV Current Accuracy (IREF pin) Symbol Conditions Configuration Load Min. Max. I OUT V DD = 3.30 ±5% R REF = 475Ω 1% I REF = 2.32mA Nominal test load for given configuration Note: 1. I NOMINAL refers to the expected current based on the configuration of the device. -12% I NOMINAL +12% I NOMINAL Differential Clock Output Current Board Target Trace/Term Z Reference R, Iref = V DD /(3xRr) Output Current V Z 100Ω (100Ω differential 15% coupling ratio) R REF = 475Ω 1%, I REF = 2.32mA I OH = 6 x I REF 50 7
8 Typical HCSL Output Phase Noise (3.3V, 25 C) Typical LVCMOS Output Phase Noise (3.3V, 25 C) 8
9 Configuration Test Load Board Termination for HCSL outputs PI6LC4830 Rs 33Ω 5% Rs 33Ω 5% TLA TLB Clock Clock# 475Ω 1% Rp 49.9Ω 1% Rp 49.9Ω 1% 2pF 5% 2pF 5% Configuration Test Load Board Termination for LVPECL outputs V DD Z O = 50-Ohm TLA L = 0 ~ 10 in. 100-Ohm 150-Ohm 150-Ohm TLB Z O = 50-Ohm 9
10 Configuration CMOS Output V DD =+3.3V C (10pF) L Power Supply Filter V DDQx 4.7Ω 3.3V ± 5% 0.1µF V DDA_PLL 0.1µF 10µF 10
11 Packaging Mechanical: 32-Pin TQFN (ZH) Notes: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO Recommended land pattern is for reference only. 5. Thermal pad soldering area (mesh stencile design is recommended) DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH32 DOCUMENT CONTROL #: PD-2070 DATE: 06/30/11 REVISION: B Note: For latest package info, please check: Ordering Information (1-3) Ordering Code Package Code Package Description PI6LC4830ZHE ZH 32-Pin, Pb-free & Green (TQFN) Notes: 1. Thermal characteristics can be found on the company web site at 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation All trademarks are property of their respective owners. 11
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CKIN- IREF PI2EQX3232A Features Supports data rates up to 3.2Gbps on each lane Adjustable Transmiter De-Emphasis & Amplitude Adjustable Receiver Equalization Spectrum Reference Clock Buffer Output Optimized
19MHz to 250MHz Low Phase-Noise XO PAD CONFIGURATION
FEATURES < 0.6ps RMS phase jitter (12kHz to 20MHz) at 155.52MHz 30ps max peak to peak period jitter 8bit Switch Capacitor for ±50PPM crystal CLoad tuning о Load Capacitance Tuning Range: 8pF to 12pF Ultra
XR81112 Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer
Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer General Description The XR81112 is a family of Universal Clock synthesizer devices in a compact FN-12 package. The devices generate
ICS NETWORKING CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET Description The generates four high-quality, high-frequency clock outputs. It is designed to replace multiple crystals and crystal oscillators in networking applications. Using ICS patented Phase-Locked
2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
FemtoClock Crystal-to-LVDS Clock Generator ICS DATA SHEET. Features. General Description. Pin Assignment. Block Diagram
FemtoClock Crystal-to-LVDS Clock Generator ICS844011 DATA SHEET General Description The ICS844011 is a Fibre Channel Clock Generator. The ICS844011 uses an 18pF parallel resonant crystal. For Fibre Channel
MK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET MK1413 Description The MK1413 is the ideal way to generate clocks for MPEG audio devices in computers. The device uses IDT s proprietary mixture of analog and digital Phase-Locked Loop (PLL)
Low Skew, 1-to-6, Crystal-to-LVDS Fanout Buffer ICS DATA SHEET. General Description. Features. Block Diagram. Pin Assignment ICS
Low Skew, 1-to-6, Crystal-to-LVDS Fanout Buffer ICS8546-01 DATA SHEET General Description The ICS8546-01 is a low skew, high performance 1-to-6 Crystal Oscillator-to-LVDS Fanout Buffer. The ICS8546-01
ICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET
DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase
Low-Jitter, 8kHz Reference Clock Synthesizer Outputs MHz
19-3530; Rev 0; 1/05 Low-Jitter, 8kHz Reference General Description The low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz.
ICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET
DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate
PI2EQX4432D 2.5 Gbps x2 Lane PCI Express Repeater/Equalizer with Signal Detect and Flow-Through Pinout
Features Two High Speed PC Express lanes Supports PC Express data rates (2.5 Gbps) on each lane Adjustable Receiver Equalization nput Signal Level Detect & Output Squelch on all Channels Output De-emphasis
MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET
DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage
PI6C V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram
Features Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, n CLK pair accepts LVDS, LVPECL,
ICS HIGH PERFORMANCE VCXO. Features. Description. Block Diagram DATASHEET
DATASHEET ICS3726-02 Description The ICS3726-02 is a low cost, low-jitter, high-performance designed to replace expensive discrete s modules. The ICS3726-02 offers a wid operating frequency range and high
PI3USB223. USB 2.0 High-Speed and Audio Switches with Negative Signal Capability D+/R D-/L V DD ASEL GND VBUS. Description. Features.
with Negative Signal Capability Features Single +2.7V to +4.4V Supply Voltage Low 50µA Supply Current -3dB Bandwidth: 1500MHz (typ) Low 2.5Ω(typ)On-Resistance THD+N: 0.02% Shorting D+/R and D-/L to Vbus
PI3VDP411LSR. Dual Mode DisplayPort to DVI/HDMI Electrical Bridge (Level Shifter) Description. Features. Pin Configuration (48-Pin TQFN) GND
Features ÎÎConverts low-swing AC coupled differential input to HDMI rev 1.3 compliant open-drain current steering Rx terminated differential output ÎÎHDMI Level shifting operation up to 2.5Gbps per lane
MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.
ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET
DATASHEET ICS722 Description The ICS722 is a low cost, low-jitter, high-performance 3.3 volt designed to replace expensive discrete s modules. The on-chip Voltage Controlled Crystal Oscillator accepts
LOW PHASE NOISE CLOCK MULTIPLIER. Features
DATASHEET Description The is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase noise multiplier. Using
S Low Phase Jitter 0.34psRMS (12kHz to 20MHz) 0.14psRMS (1.875MHz to 20MHz)
19-55; Rev 1; 6/1 Low-Jitter Clock Generator General Description The is a high-performance, precision phaselocked loop (PLL) clock generator optimized for nextgeneration high-speed Ethernet applications
FemtoClock Crystal-to-LVDS Frequency Synthesizer w/integrated Fanout Buffer
FemtoClock Crystal-to-LVDS Frequency Synthesizer w/integrated Fanout Buffer ICS844256DI DATA SHEET General Description Features The ICS844256DI is a Crystal-to-LVDS Clock Synthesizer/Fanout Buffer designed
MK VCXO AND SET-TOP CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2771-16 Description The MK2771-16 is a low-cost, low-jitter, high-performance VCXO and clock synthesizer designed for set-top boxes. The on-chip Voltage Controlled Crystal Oscillator accepts
ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
ICS FemtoClock Crystal-to-3.3V LVPECL Clock Generator DATA SHEET. General Description. Features. Block Diagram. Pin Assignment.
FemtoClock Crystal-to-3.3V LVPECL Clock Generator ICS843051 DATA SHEET General Description The ICS843051 is a Gigabit Ethernet Clock Generator. The ICS843051can synthesize 10 Gigabit Ethernet, SONET, or
ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
Low Phase Noise, LVPECL VCXO (for 150MHz to 160MHz Fundamental Crystals) FEATURES. * Internal 60KΩ pull-up resistor
0.952mm VDD QB PL586-55/-58 FEATURES DIE CONFIGURATION Advanced non multiplier VCXO Design for High Performance Crystal Oscillators Input/Output Range: 150MHz to 160MHz Phase Noise Optimized for 155.52MHz:
FemtoClock Crystal-to-LVDS Clock Generator
FemtoClock Crystal-to-LDS Clock Generator 844021-01 DATA SHEET GENERAL DESCRIPTION The 844021-01 is an Ethernet Clock Generator. The 844021-01 uses an 18pF parallel resonant crystal over the range of 24.5MHz
ICS309 SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH. Description. Features. Block Diagram DATASHEET
DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different
ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET ICS662-03 Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior
PI3HDMI412FT. 4-Differential Channel, 2:1 Mux/DeMux, DVI/HDMI Compliant Signal Switch with Flow-through Pin Out
Features 4-Differential Channel 2:1 Mux/DeMux DVI, HDMI rev 1.1, and HDMI rev 1.2 signal compatible -3dB BW = 1.5 GHz (3.0Gbps) Crosstalk: -35dB@1.65Gbps Switching speed: 4ns Isolation: -37dB@1.65Gbps
Features. EXTERNAL PULLABLE CRYSTAL (external loop filter) FREQUENCY MULTIPLYING PLL 2
DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL MK2049-34A Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 khz
NOT RECOMMENDED FOR NEW DESIGNS
3.3V, PCI Express 3.0 2-Lane, 2:1 Mux/DeMux Switch Features ÎÎ4 Differential Channel, 2:1 Mux/DeMux ÎÎPCI Express 3.0 Performance, 8.0Gbps ÎÎPinout optimized for placement between two PCIe slots ÎÎBi-directional
ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS276 Description The ICS276 field programmable VCXO clock synthesizer generates up to three high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer ICS8535I-31 General Description The ICS8535I-31 is a low skew, high performance ICS 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
PI6CG Description. Features. Pin Configuration. A product Line of. Diodes Incorporated
Very Low Power 8-Output PCIe Clock Generator With On-chip Termination Features ÎÎ1.8V Supply Voltage ÎÎCrystal/CMOS input: 25 MHz ÎÎ8 Differential low power HCSL outputs with on-chip termination ÎÎIndividual
PI3USB V USB 3.0 SuperSpeed Dual 2:1 Mux/DeMux Switch with Enable. Description. Features. Application Routing USB 3.0 SuperSpeed signals.
Features Dual 2:1 USB 3.0 Switch Bi-directional Operation 5 Gbps Performance Very high -3 db bandwidth: 8.2 GHz Low Insertion Loss: -1dB @ 2.5 GHz Excellent Return Loss: -29 db @ 2.5 GHz Low Crosstalk:
PI3VDP411LSA. Dual Mode DisplayPort to DVI/HDMI Electrical bridge (Level Shifter) Features. Description. Pin Configuration (48-Pin TQFN) GND
Features ÎÎConverts low-swing AC coupled differential input to HDMI rev 1.3 compliant open-drain current steering Rx terminated differential output ÎÎHDMI Level shifting operation up to 2.5Gbps per lane
FemtoClock Crystal-to-3.3V LVPECL Clock Generator ICS843011C
FemtoClock Crystal-to-3.3V LVPECL Clock Generator ICS843011C DATA SHEET GENERAL DESCRIPTION The ICS843011C is a Fibre Channel Clock Generator. The ICS843011C uses a 26.5625MHz crystal to synthesize 106.25MHz