Unit 7. Gates. Checkers / Decoders. Fundamental Digital Building Blocks: Decoders & Multiplexers CHECKERS / DECODERS

Transcription

1 Unit 7 undamental Digital Building Block: Decoder & Multipleer CHECKER / DECODER Gate Gate can have more than 2 input but the function ta the ame ND = output = if LL input are Output for onl input combination OR = output = if N input i Output for onl input combination / Decoder n ND gate onl output for combination That combination can be changed b adding inverter to the input We can think of the ND gate a checking or decoding a pecific combination and outputting a when it matche. X Z X Z X Z X Z 3-input ND 3-input OR ND gate decoding combination ND gate decoding combination

2 / Decoder / Decoder Place inverter at the input of the ND gate uch that produce onl for input combination {,,} = {} G produce onl for input combination {,,} = {} n OR gate onl output for combination That combination can be changed b adding inverter to the input ND gate decoding combination X Z ND gate decoding combination G X Z G dd inverter to create an OR gate decoding combination X Z dd inverter to create an OR gate decoding combination X Z Decoder Eercie Compiler tranlate oftware to intruction that tell the proceor to DD, LOD from Memor, tore to Memor, etc. Thee intruction are binar code The proceor mut decode the intruction Create an ND gate decoder for each intruction tpe in the table that will produce '' when that intruction i about to be eecuted Intruction Tpe 6-bit OPCODE OP[5:] DD LOD TORE BRNCH 7.7 ull Decoder full decoder i a building block that: Take in an n-bit binar number a input Decode that binar number and activate the correponding output Individual output for input combination 3-to-8 Decoder There are gate inide to implement each output 7.8 DD LOD TORE 3-bit binar number output for each combination of the input number

3 Decoder Decoder decoder i a building block that: Take a binar number a input Decode that binar number and activate the correponding output Put in 6=, Output 6 activate ( ) Put in 5=, Output 5 activate ( ) decoder i a building block that: Take a binar number a input Decode that binar number and activate the correponding output Put in 6=, Output 6 activate ( ) Put in 5=, Output 5 activate ( ) Binar #6 Onl that numbered output i activated Binar #5 Onl that numbered output i activated Decoder ie Eercie decoder w/ an n-bit input ha 2 n output output for ever combination of the n-bit input D D D2 X (MB) D3 n input (2) 2-to-4 Decoder 2 n output (4) n input (3) 2 (MB) to-8 Decoder 2 n output (8) Complete the deign of a 2-to-4 decoder X D D D2 D3 D D D2 D3 X (MB) D D D2 D3

4 Building Decoder Vending Machine Eample uming the kepad produce a 4-bit numeric output, add logic to produce the releae ignal for each of the 6 vending item. 3-bit number [2:] for for for for for for O O O2 O3 O4 O5 2 O O O2 O3 O4 O for O6 O6 for O7 O7 Conider an problem with thi deign Enable Enable In a normal decoder eactl one output i active at all time It ma be undeirable to alwa have an active output We can add an etra input (called an enable) that can independentl force all the output to their inactive value When E=, input i ignored (MB) ince E=, all output = (MB) 2-to-4 Decoder One output will alwa be active (MB) Will force all output to when E = (i.e. not enabled) When E=, input will caue the appropriate output to go active (MB) ince E=, output will function normall

5 Implementing Enable Multipleer Original 2-to-4 decoder B B (MB) B E When E=, force all output = When E=, output operate a the did originall D D D2 D3 Multipleer are one of the mot common digital circuit natom: n data input, log 2 n elect bit, output multipleer ( mu for hort) elect one data input and pae it to the output n data input 4-to- Mu i i i2 i3 log 2 n elect bit output i i i2 I Multipleer Multipleer 4-to- Mu 4-to- Mu, 32-bit wide mu 2 Thu, input 2 = C i elected and paed to the output B C D i i i2 i3 elect bit = 2 = 2. C i i i2 2 Thu, input = i elected and paed to the output B C D i i i2 i3 elect bit = 2 =. i i i2 I3 I3

6 Multipleer Recall Uing T/T2 2-to- Mu, 32-bit wide mu t Level of ND gate act a barrier onl paing channel OR gate combine 3 tream of with the channel that got paed (i.e. ICH) 2 nd Level of ND gate pae the channel to onl the elected output 2 Thu, input = B i elected and paed to the output B i i elect bit = 2 =. B i I Eentiall thi logic form a 4-to- mu where one level of gate block all but and then the OR gate combine all ignal ICH ICH ICH 2 ICH 3 ICH Connection Point ICH ICH ICH ICH ICH OCH OCH OCH 2 ICH OCH 3 ND: ND ICH = ICH ND ICH = IEL IEL IEL2 IEL3 OR: + ICH + + = ICH OEL OEL OEL2 OEL3 ND: ND ICH = ICH ND ICH = Eercie: Build a 4-to- mu Building a Mu Complete the 4-to- mu to the right b drawing wire between the 2-to-4 decode and the ND gate I I I2 I3 = = = = ND Gate acting a barrier gate inal OR gate take 3 ero and one elected input To build a mu Decode the elect bit and include the correponding data input. inall OR all the firt level output together. = 2 I I I 2 I I I i i i2 i3 2-to-4 Decoder I 3

7 Building a Mu Building a Mu To build a mu Decode the elect bit and include the correponding data input. inall OR all the firt level output together. = 2 I I I 2 I 3 i i i2 i3 To build a mu Decode the elect bit and include the correponding data input. inall OR all the firt level output together. I I I 3 I 3 I Building Wide Mue Building Wide Mue o far mue onl have ingle bit input I i onl -bit I i onl -bit What if we till want to elect between 2 input but now each input i a 4- B bit number I Ue a 4-bit wide 2-to- Pa all 4 bit mu B I I I -bit wide 2-to- mu When we elect I of I or I or I we want all 4-bit of that input to be paed B 4-bit wide 2-to- mu Ue one mu per To build a 4-bit wide 2-to- mu, ue eparate 2-to- mue Operation: When =, all mue pa their I input which mean all the bit get through When =, all mue pa their I input which mean all the B bit get through In general, to build an m-bit wide (i.e. m-lane) n-to- mu, ue individual mue 2 3 B B B2 B3 I I I I I I I I 2 3

8 Multipleer Multipleer 4-to- Mu, 32-bit wide mu 2-to- Mu, 32-bit wide mu 2 Thu, input = [3:] i elected and paed to the output [3:] B[3:] C[3:] D[3:] i i i2 i3 [3:] 2 Thu, input = B[3:] i elected and paed to the output [3:] B[3:] i i B[3:] elect bit = 2 =. elect bit = 2 = Eercie Building Large Mue How man -bit wide mue and of what ie would ou need to build a 4-to-, 8-bit wide mu (i.e. there are 4 number: W[7:], X[7:], [7:] and Z[7:] and ou mut elect one) How man -bit wide mue and of what ie would ou need to build a 8-to-, 2-bit wide mu? imilar to a tournament of port team Man team enter and then are narrowed down to winner In each round winner pla

9 Deign an 8-to- mu with 2-to- Mue 7.33 Cacading Mue 7.34 I I I2 I3 I4 I5 I6 I7 I I I I I I I I I I I I I I 2 Ue everal mall mue to build large one Rule. rrange the mue in tage (baed on necear number of input in t tage) 2. Output of one tage feed to input of the net until onl final output 3. ll mue in a tage connect to the ame group of elect bit Uuall, LB connect to firt tage MB connect to lat tage Building a 4-to- Mu Building a 4-to- Mu tage tage 2 tage tage 2 D D I I Rule : Output from tage connect to input of tage 2 I D D D 2 D D I I I D 2 I I D 2 I I I Walk through an eample: I 4-to- mu built w/ 2-to- mue Rule 2: LB connect to all mue in firt tage. MB connect to all mue in econd tage =

10 Building a 4-to- Mu Building a 4-to- Mu tage tage 2 tage tage 2 D D D 2 D D I I D I D D D 2 D D I I D D I Walk through an eample: = D 2 I I I = narrow our choice down to D and Walk through an eample: = D 2 I I I = elect our final choice, D Device v. tem Label Eercie When uing hierarch (i.e. building block) to deign a circuit be ure to how both device and tem label Device Label: ignal name ued the block to indicate which input/output i which to the outide uer tem label: ignal name ued the block ignal from the circuit being built Can have the ame name a the device label if uch a ignal name eit at the outide level ketch how ou could build a 6-to- mu with 4-to- mue? 8-to- and 2-to mue? nalog: ormal and ctual parameter in oftware function call. a and b are like device label and indicate the name ued inide a block. 2. and are like tem label and repreent the actual value to be ued. int div(int i, int i) { int t = i/i; return t; } int main() { int d=, d=2; int = div(d,d); } Device Label: Indicate which input/output i which inide the bock. tem Label: ctual ignal from the circuit being built D D D 2 I I I I I I

11 Eercie elect-bit Ordering Create a 3-to- mu uing 2-to- mue Input: I, I, I2 and elect bit, Output: I D I D I I If we connect the elect bit a hown to build an 8-to- mu, how how to label the input (i-i7) o that the correct input i paed baed on the binar value of 2: elect OUT 2 D 2 I2 I I