ULTRAPAK 10 DWDM Optoelectronics Subsystem. General Description. Features. Applications. Figure 1. UltraPak 10 Subsystem

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1 General Description The ULTRAPAK 10 DWDM is a highly integrated optoelectronics subsystem that includes a 10 Gbit/s External Modulated optical transmitter, a 10 Gbit/s PIN or APD optical receiver and a 16-channel Serializer/Deserializer (SER/DES). It provides a complete solution to the physical layer interface in a SONET/SDH transport system including optical-toelectrical conversion, clock recovery, deserialization, serialization, clock synthesization and electrical-tooptical conversion. The transmitter wavelength is available in ITU-T wavelength grid (50 GHz spacing) for Dense Wavelength Division Multiplexing (DWDM) applications. The microprocessor control design enables user full access to control and monitor the subsystem. The output data rate is selectable between 9.953, , , and Gbit/s, allowing for SONET, 10 Gigabit Ethernet, and Forward Error Correction (FEC) implementation. The ULTRAPAK 10 DWDM provides a single plugin footprint for Long Reach to Ultra Long Reach applications. The ULTRAPAK 10 DWDM compact design offers a 3.50 W x 4.14 L x 0.53 H package. Figure 1. UltraPak 10 Subsystem Features 10 Gbit/s Optical Transmitter and 10 Gbit/s Optical Receiver with 16-channel SER/DES µm External Modulated Optical Transmitter with wavelengths available according to ITU-T G.692 wavelength grid (50 GHz spacing). Built in Wavelength Locker. PIN or APD high sensitivity optical receiver. Receiver Decision Slicing Level control. Supports SONET (9.953 Gbit/s), Gigabit Ethernet (10.3 Gbit/s), FEC ( Gbit/s 7% Overhead, and Gbit/s Digital Wrapper ) data rates. Transmitter features Optical output power control by VOA. Tone Modulation signal input for Wavelength Identification. Built in Jitter Clean-up Circuit for Reference Clock Input. 16-bit parallel (or equivalent line rate) Mbit/s Low Voltage Differential Signaling (LVDS) interface. 300-pin Multi-Source Agreement (MSA) pin compatible. I 2 C interface provide the user with expanded control like decision slice level and monitor functions of the ULTRAPAK 10 with additional MSA compliant pins for analog monitors. Compact package: Gen I: 3.50 W x 4.14 L x 0.53 H Compliant with ITU-T G.691 (L 64.2), G.975, G.709, Telcordia GR-253-CORE (LR-2) and Optical Internetworking Forum OIF (SFI- 4 interface) standards. Applications DWDM SONET/SDH-based transport systems. High Performance SONET/SDH test equipment. Terabit Routers/Switches. Optical Cross Connect systems. SONET/SDH Network Interface Processor Electrical Interface ULTRAPAK 10 DWDM Optoelectronics Subsystem Optical Interface

2 Parallel-to-Serial Converter The parallel-to-serial converter shown in Figure 1 is comprised of two byte-wide registers. The TXPICLKP/N ( MHz or equivalent line rate) clocks in the data from the TXDINP/N[0:15] bus to the first register of the parallel-to-serial register. The second register is a parallel loadable shift register, which takes its parallel input from the first register. An internally generated byte clock activates the parallel data transfer between registers. The serial data is shifted out of the second register. FIFO A FIFO is added to decouple the internal and external parallel clocks. The internally generated clock is a divided by 16-clock and is used to clock out data from the FIFO. The FIFO can be initialized in one of the following two ways: 1. During power up, once the PLL has locked to the reference clock provided on the TXREFCLK pins, the TXLOCKERR will become active and initialize the FIFO. 2. When TXRSTB becomes active, the entire chip is reset. When the PLL acquires the lock, the TXLOCKERR becomes active and initializes the FIFO. Note: TXPCLK does not toggle when TXRSTB is active. During normal running operation, the incoming data is passed from the TXPICLKP/N timing domain to the internally generated timing domain. Optical Transmitter The optical transmitter converts the electrical serialized data and clock from the serializer to a serial optical bit stream. The transmitter employs a Continuous Wave (CW) laser with Wavelength Locker built-in and a Mach-Zehnder Modulator. The optical transmitter operates in the 1550 nm window with wavelengths available in ITU-T grid (50 GHz spacing) in the C-band. The wavelength can be locked onto the desired ITU-T grid channel via the use of the wavelength locker in the transmitter. The microprocessor controls and monitors many aspects of the optical transmitter including Initial Setting, Output Power Control with built-in VOA (Voltage-controlled Optical Attenuator, refer to page 22, channel control section), Bias Control, and Temperature Control/Monitor. Receiver Section Description The ULTRAPAK 10 DWDM Gen I subsystem receiver section provides the first stage of the opticalto-electrical conversion and data processing in a SONET/SDH OC-192 transport system. It receives the serial optical data and converts it to an electrical signal. It then recovers the clock from the serial data stream and feeds it to the deserializer. The deserializer converts the bit-serial Gbit/s (or equivalent line rate) data stream into a Mbit/s (or equivalent FEC rates) 16-bit parallel data format. Optical Receiver The optical receiver converts the serial optical signal to a serial electrical bit stream and sends it to the deserializer. The receiver operates in wavelengths from 1.2 µm to 1.6 µm. It consists of a highly responsive Positive-Intrinsic-Negative (PIN) diode or Avalanche-Photo-Diode (APD) coupled to a single-mode fiber pigtail, a wideband linear preamp, and a limiting amplifier buffer. Incoming optical pulses are converted to electrical current pulses by the PIN diode or APD. The preamp is used to translate the electrical current pulses to voltage.

3 Section 3: Optical and Electrical Characteristics Table 4. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the subsystem. These are absolute stress ratings only. Functional operation of the subsystem is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect the reliability of the subsystem. Parameter Symbol Min Max Unit Operating Case Temperature* T op o C Storage Case Temperature T stg Maximum Average Optical Input Power PIN +3 APD -3 Static Discharge Voltage (Human body model) 100 V Supply Voltage (DC) +3.3 V dd V +5.0 V cc V -5.2 V ee V Note: * Operating Temperature will soon be available from -10 to + 70 o C. Table 5. Optical/Electrical Characteristics o C Parameter Symbol Min Typ Max Unit Optical Interface Average Optical Output Power C1330 Po C Peak Center Wavelength λ C nm Variation of Wavelength λ C nm Spectral Width ( λ C20dB ) nm Extinction Ratio EX 11 db Receiver Bandwidth=30GHz (40-60% of Eye window) Side-mode Suppression Ratio SMSR 30 db Eye Mask of Optical Output Compliant with GR-253 and ITU-T G.691 Jitter Generation (Filter bandwidth of 50 khz - 80 MHz) 0.1 UI P-P Jitter Transfer/Tolerance Compliant with GR-253 and ITU-T G.783 Receiver Sensitivity (At 25C case) PIN P RMIN Gbit/s, BER=10-12, PRBS APD Receiver Overload PIN P RMAX Gbit/s, BER=10-12, PRBS APD -7 Dispersion Penalty 1 DP 2 db Optical Return Loss 27 db Optical Signal to Noise Ratio -10 OSNR 20 db LVDS Input (Internal Bias) Input Voltage Differential V INDIFF mv Differential Input Resistance R INDIFF 100

4 LVDS Output Output Voltage Differential V OUTDIFF mv Differential Output Resistance R OUTDIFF Ω LVTTL Input Input High Voltage V IH V Input Low Voltage V IL V Input High Current I IH 50 µa Input Low Current I IL -500 µa LVTTL Output Output High Voltage V OH 2.4 V Output Low Voltage V OL 0.5 V Monitor signals Laser Bias Monitor 10 mv/ma Laser Power Monitor 500 mv Laser Temperature Monitor mv Receiver Loss of Power 3 APD PIN mv mv Power Supply Vdd V Vee V Vcc V Power Consumption P 8 12 W Note: 1 Tested at Gbit/s, PRBS , BER = Dispersion D = 1600 ps/nm 2 Needs further clarification on equivalent noise bandwidth, dependent on customer s application 3 Voltage at RXPOWMON for RXPOWALM active. All parameters are specified End-Of-Life within the overall relevant operating temperature range, unless otherwise specified. The typical values are referenced to +25 o C, nominal power supplies and Beginning-Of-Life. Table 6. AC Transmitter Characteristics TXPICLKP/N = MHz Parameter Symbol Min Typ Max Unit TXPICLKP/N Duty Cycle % TXDINP/N[0:15] Set Up Time Tsu 200 ps With respect to rising edge of TXPICLKP TXDINP/N[0:15] Hold Time Th 200 ps With respect to rising edge of TXPICLKP LVDS Input Rise & Fall Time Tr/Tf 150 ps

5 Section 7: Ordering Information Figure 10. Product Code Definition C XX XX XXXX X CENiX Product Specific Optical Connector S = SC/PC "XX" Data Rate (Gbit/s) X X X X 20 X 21 X 22 X 23 X Note: XX = 20, 21, 22 and 23 have an internal jitter filter at indicated data rate. Product Specific 30 = = +4 Wavelength Field: Last 4 digits of 15xx.xx (1-9999) ITU-T DWDM wavelengths (see Table 10) Table 9. Ordering Matrix CENiX Code Transmit Receive Application Optical Connector C1330xxxxS MZ- Modulator APD DWDM, Power +1 SC/PC C1331xxxxS MZ- Modulator APD DWDM, Power +4 SC/PC C E - - ULTRAPAK 10 Eval Kit -