BL9180 Dual,300mA Ultra-low Noise CMOS LDO Regulator

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1 FEATURES Up to 00mA Output Current(Each LDO) Dual Shutdown Pins Control Each Output 90uA Operating supply current per LDO Excellent Line regulation:0.05%/v Low High Power Supply Rejection Ratio Wide Operating Voltage Range:.0V to 6.0V.V to.v Factory-Preset Output High Accuracy: ±% or ±% Internal Pulled down(8 MΩ)resistor Current Limiting and Thermal Protection Two LDOs in SOT--6 and ESOP-8 Package RoHS Compliant and 00% Lead(Pb)-Free APPLICATIONS Cellular and Smart Phones Battery-Powered Equipment Laptop, Palmtops, Notebook Computers Hand-Held Instruments PCMCIA Cards and Wireless LAN MP/MP4/MP5 Players Portable Information Appliances DESCRIPTION The dual, low noise, low-dropout regulator supplying up to 00mA output current at each channel. The output voltage for each regulator is set independently by trimming. Voltages are selectable in 50mV steps within a range of.v to.v by operating from a V to 6V input. The includes two independent logic-controlled shutdown inputs and allows the output of each regulator to be turned off independently. When both outputs shutdown simultaneously, the chip will be turn off and consumes nearly zero operation current which is suitable for battery-power devices. The includes high accuracy voltage reference, error amplifier, current limit circuit and output driver module. The has excellent load and line transient response and good temperature characteristics, which can assure the stability of chip and power system. And it uses trimming technique to guarantee output voltage accuracy within ±% or ±%. The is available in SOT--6 and ESOP-8 package which is Lead(Pb)-free. ORDERING INFORMATION X X X XX Package: RA:SOT--6A RB:SOT--6B EP:ESOP-8 Features: P:Standard(default, lead free) C:Customized Output Voltage Accuracy A:±% B:±% Output Voltage A:.V(Output),.8V(Output) B:.5V(Output),.0V(Output) C:.8V(Output),.5V(Output) D:.8V(Output),.8V(Output) E:.5V(Output),.8V(Output) F:.8V(Output),.8V(Output) G:.8V(Output),.0V(Output) H:.8V(Output),.V(Output) I:.0V(Output),.5V(Output) J:.V(Output),.8V(Output) K:.V(Output),.V(Output) L:.8V(Output),.V(Output) M:.8V(Output),.V(Output) N:.5V(Output),.V(Output) O:.V(Output),.V(Output) P:.V(Output),.8V(Output) TYPICAL APPLICATION XXX RB VIN uf EN VDD EN VOUT VOUT 6 GND 5 4 uf uf VOUT VOUT Application hints: Output capacitor (C OUT.uF) is recommended in applications to assure the circuit s stability for output voltage.8v. Rev. 8/0 00 Belling All Rights Reserved

2 MARKING MARKING MARKING Absolute Maximum Rating (Note ) Input Supply Voltage (V IN ) -0.V to +7V EN Input Voltage -0.V to +V IN Output Voltage -0.V to V IN +0.V Output Current 400mA Maximum Junction Temperature 5 C Operating Temperature Range (Note) -40 C to 85 C Storage Temperature Range -65 C to 5 C Lead Temperature (Soldering, 0s) 00 C Package Information SOT--6A TOP VIEW SOT--6B TOP VIEW ESOP-8 TOP VIEW VOUT 6 EN EN 6 VOUT VOUT 8 EN VDD 5 GND VDD 5 GND VIN VOUT 7 6 GND GND VOUT 4 EN EN 4 VOUT VIN 4 5 EN Part Number Top Mark Temp Range -XXXRA EVYW (Note) -40 C to +85 C -XXXRB EVYW -40 C to +85 C -XXXEP VYWEP (Note) -40 C to +85 C Pin Description Thermal Resistance (Note 4) : Name VOUT VDD VOUT EN GND EN VIN VIN Function LDO Output Pin Input Pin LDO Output Pin LDO Enable Pin Ground Pin LDO Enable Pin Input Pin Input Pin Package Ө JA Ө JC SOT-6 50C/W 0 C/W ESOP-8 50C/W 0C/W Y 9 A B C D Year W Week A Y Z a y z Product Classification Output Voltage Voltage Code Accuracy Package Type Product Name Package Type Product Name Package Type Product Name.V/.8V A ±% SOT--6A -ABPRA SOT--6B -ABPRB ESOP-8 -ABPEP.5V/.0V B ±% SOT--6A -BBPRA SOT--6B -BBPRB ESOP-8 -BBPEP.8V/.5V C ±% SOT--6A -CBPRA SOT--6B -CBPRB ESOP-8 -CBPEP.8V/.8V D ±% SOT--6A -DBPRA SOT--6B -DBPRB ESOP-8 -DBPEP.5V/.8V E ±% SOT--6A -EBPRA SOT--6B -EBPRB ESOP-8 -EBPEP Rev. 8/0 00 Belling All Rights Reserved

3 .8V/.8V F ±% SOT--6A -FBPRA SOT--6B -FBPRB ESOP-8 -FBPEP.8V/.0V G ±% SOT--6A -GBPRA SOT--6B -GBPRB ESOP-8 -GBPEP.8V/.V H ±% SOT--6A -HBPRA SOT--6B -HBPRB ESOP-8 -HBPEP.0V/.5V I ±% SOT--6A -IBPRA SOT--6B -IBPRB ESOP-8 -IBPEP.V/.8V J ±% SOT--6A -JBPRA SOT--6B -JBPRB ESOP-8 -JBPEP.V/.V K ±% SOT--6A -KBPRA SOT--6B -KBPRB ESOP-8 -KBPEP.8V/.V L ±% SOT--6A -LBPRA SOT--6B -LBPRB ESOP-8 -LBPEP.8V/.V M ±% SOT--6A -MBPRA SOT--6B -MBPRB ESOP-8 -MBPEP.5V/.V N ±% SOT--6A -NBPRA SOT--6B -NBPRB ESOP-8 -NBPEP.V/.V O ±% SOT--6A -OBPRA SOT--6B -OBPRB ESOP-8 -OBPEP.V/.8V P ±% SOT--6A -PBPRA SOT--6B -PBPRB ESOP-8 -PBPEP Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The is guaranteed to meet performance specifications from 0 C to 70 C. Specifications over the 40 C to 85 C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note : E: with RA package E: with RB package V: Voltage code Y: Year of wafer manufacturing W: Week of wafer manufacturing EP: ESOP-8 Note 4: Thermal Resistance is specified with approximately square of oz copper. Block Diagram SOT-6 ESOP-8 Rev. 8/0 00 Belling All Rights Reserved

4 Electrical Characteristics (Note 5) (V IN =.6V, EN=EN=V IN, C IN =C OUT =F, T A =5 C, unless otherwise noted.) Parameter Symbol Conditions MIN TYP MAX unit Input Voltage V IN 6 V Output Voltage Accuracy V (Note 6) V IN=.6V, - + OUT I OUT =ma - + % Current Limit I LIM R LOAD = ma Quiescent Current I Q V EN >.V, I OUT =0mA A Dropout Voltage V DROP I OUT =00mA, V OUT =.8V 0 80 I OUT =00mA, V OUT =.8V 0 00 mv (Note 7) Line Regulation ΔV LINE V IN =.6V to 5.5V I OUT =ma %/V Load Regulation (Note 8) ΔV LOAD ma<i OUT <00mA %/A (Note 9) Output Voltage Temperature Coefficient TC VOUT I OUT =ma ±60 ppm/ C Standby Current I STBY V EN =GND,Shutdown 0.0 A EN Input Bias Current I IBSD V EN =GND or V IN 0 00 na V EN Logic Low V IN =V to 5.5V, IL 0.4 V Shutdown Input V Threshold Logic High V IN =V to 5.5V, IH. V Start up 0Hz to00khz, Output Noise e Voltage NO I OUT =00mA C OUT =uf 00 V RMS Power f=7hz -7 Supply Rejection f=khz PSRR I OUT =00mA -70 db Ratio f=0khz -50 Thermal Shutdown Shutdown, Temp T Temperature SD increasing 65 C Thermal Shutdown Hysteresis T SDHY 0 C Note 5: 00% production test at +5 C. Specifications over the temperature range are guaranteed by design and characterization. Note 6: This IC includes two kinds of output voltage accuracy versions. A: ±%, B: ±%. Note 7: Line regulation is calculated by VOUT V OUT VLINE 00 VIN V OUT ( normal) Where V OUT is the output voltage when V IN=5.5V, and V OUT is the output voltage when V IN=.6V, V IN=.9V. V OUT(normal)=.8V. Note 8: Load regulation is calculated by VOUT V OUT VLOAD 00 IOUT V OUT ( normal ) Where V OUT is the output voltage when I OUT=mA, and V OUT is the output voltage when I OUT=00mA. I OUT=0.99A, V OUT(normal)=.8V. Note 9: The temperature coefficient is calculated by VOUT TC VOUT T V OUT Rev. 8/0 00 Belling All Rights Reserved 4

5 EN Pin Shutdown Threshold(V) Output Voltage(V) Dropout Voltage(mV) PSRR(dB) Output Voltage(V) Quiescent Current(uA) Typical Performance Characteristics Output Voltage Vs. Temperature IQ Vs.VIN(-HBPRB) V IN =.6V C IN =C OUT =uf 5 CIN=uF COUT=uF,COUT=uF No Load Temperaute(C) Input Voltage(V) Dropout Voltage Vs. Load Current C IN =C OUT =uf VOUT=.8V 0-0 PSRR(VOUT) CIN=COUT=COUT=uF VOUT=.8V VOUT=.0V Load Current(mA) TJ=85C TJ=5C TJ=-40C Frequency(Hz) ma Load 00mA Load 00mA Load EN Pin Shutdown Threshold Vs. Temperature VOUT Vs. VIN(-HBPRB) V IN =.6V C IN =C OUT =uf CIN=uF COUT=COUT=uF IOUT=IOUT=00mA VOUT(.8V) VOUT(.V) Temperature(C) Input Voltage(V) Rev. 8/0 00 Belling All Rights Reserved 5

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7 Output Voltage(V) CIN=COUT=uF VOUT Vs.VIN Input Voltage(V) ILoad=mA ILoad=00mA ILoad=00mA Rev. 8/0 00 Belling All Rights Reserved 7

8 Applications Information The is integrated with two low noise, low dropout and low quiescent current linear regulators designed primarily for battery applications. Output voltages are optional ranging from.v to.v, and each channel can supply current up to 00 ma. Enable Function The is shutdown by pulling the EN input low, and turn on by driving the input high. If this feature is not be used, the EN input should be tied to VIN to keep the regulator on at all times. Current Limit and Thermal Protection The includes two independent current limit structure which monitor and control each pass transistor s gate voltage limiting the guaranteed maximum output current to 00mA. Thermal overload protection limits total power dissipation in the. When the junction temperature exceeds T J =65 C, the OTP circuit starts the thermal shutdown function turn the pass element off and allowing the IC to cool. The OTP circuit turn on the pass element again after IC s junction temperature cool by 0 C, result in a pulsed output during continuous thermal overload conditions. Thermal-overloaded protection is designed to protect the in the event of fault conditions. Do not exceed the absolute maximum junction temperature rating of T J =5 C for continuous operation. The output can be shorted to ground for an indefinite amount of time without damaging the part by cooperation of current limit and thermal protection. Operating Region and Power Dissipation The maximum power dissipation of depends on the thermal resistance of the case and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The power dissipation across the device is P D = (V IN V OUT ) I OUT + V IN I Q The maximum power dissipation is: P D (MAX) = ( T J (MAX) T A ) /θ JA Where T J (MAX) is the maximum operation junction temperature 5 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. The GND pin of the performs the dual function of providing an electrical connection to ground and channeling heat away. Connect the GND pin to ground using a large pad or ground plane. Capacitor Selection and Regulator Stability Like any low-dropout regulator, the external capacitors used with the must be carefully selected for regulator stability and performance. The requires an output capacitor between the VOUT and GND pins for phase compensation. Using a capacitor whose value is > μf on the input and the amount of Rev. 8/0 00 Belling All Rights Reserved 8

9 capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs applications. The is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least μf with ESR is > 5mΩ on the output ensures stability. The still works well with output capacitor of other types due to the wide stable ESR range. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the and returned to a clean analog ground. Load-Transient Considerations The load-transient response graphs show two components of the output response: a DC shift from the output impedance due to the load current change, and the transient response. The DC shift is quite small due to the excellent load regulation of the IC. Typical output voltage transient spike for a step change in the load current from 0mA to 50mA is tens of mv, depending on the ESR of the output capacitor. Increasing the output capacitor's value and decreasing the ESR attenuates the overshoot. Input-Output (Dropout) Voltage A regulator's minimum input-output voltage differential (or dropout voltage) determines the lowest usable supply voltage. In battery-powered systems, this will determine the useful end-of-life battery voltage. Because the uses a P-Channel MOSFET pass transistor, the dropout voltage is a function of drain-to-source on resistance [R DS(ON) ] multiplied by the load current. Layout Considerations To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for V IN and V OUT, with each ground plane connected only at the GND pin of the device. Rev. 8/0 00 Belling All Rights Reserved 9

10 Layout Circuit J VIN EN VOUT 6 VOUT VIN VIN VDD GND 5 C C J VIN EN VOUT 4 C VOUT Top Layer Layout Bottom Layer Layout Rev. 8/0 00 Belling All Rights Reserved 0

11 Package Description Rev. 8/0 00 Belling All Rights Reserved

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13 ESOP-8 Symbol Dimensions In Millimeters Min NOM Max A.77 A A..4.6 A b b c c D E E e.7bsc L L.05BSC Θ 0 8 D.0REF E.40REF ESOP-8 Surface Mount Package Rev. 8/0 00 Belling All Rights Reserved