Resistorless Electronically Tunable Grounded Inductance Simulator Design

Transcription

1 dspace.vutbr.cz Resistorless Electronically Tunable Grounded Inductance Simulator Design HERENCSÁR, N.; KARTCI, A. Proceedgs of the 27 4th International Conference on Telecommunications and Signal Processg (TSP) pp eisbn: DOI: Accepted manuscript 27 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtaed for all other uses, any current or future media, cludg reprtg/republishg this material for advertisg or promotional purposes, creatg new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work other works. Norbert Herencsar, Aslihan Kartci, "Resistorless electronically tunable grounded ductance simulator design", Proceedgs of the 27 4th International Conference on Telecommunications and Signal Processg (TSP), pp , 27. DOI:.9/TSP Fal version is available at

2 Resistorless Electronically Tunable Grounded Inductance Simulator Design Norbert Herencsar * and Aslihan Kartci *, * Department of Telecommunications / Department of Radio Electronics Brno University of Technology Technicka 382/2, 66 Brno, Czech Republic s: {herencsn; kartci}@feec.vutbr.cz Abstract A new realization of grounded lossless positive ductance simulator (PIS) usg simple vertg voltage buffer and unity-ga current follower/verter (CF±) is reported. Considerg the put trsic resistance of CF± as useful active parameter, the proposed PIS can be considered as resistorless circuit and it only employs total 6 Metal-Oxide- Semiconductor (MOS) transistors and a grounded capacitor. The resultg equivalent ductance value of the proposed simulator can be adjusted via change of put trsic resistance of CF± by means of its supply voltages. The behavior of the proposed simulator circuit is tested via implementation voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. Theoretical results are verified by SPICE simulations usg TSMC.8 μm level-7 LO EPI SCN8 CMOS process parameters with ±.9 V supply voltages. Keywords Positive ductance simulator; PIS; grounded lossless circuit; current follower; vertg voltage buffer; 5thorder high-pass filter; RLC prototype; Bessel; Butterworth; Chebyshev I; voltage-mode. I. INTRODUCTION The importance of grounded lossless positive ductance simulator (PIS) circuit theory is well known []. Monolithic prted spiral ductors have several drawbacks, for an stance substrate resistive losses, capacitive couplgs, not easy tunability the passive case due to lead of component variations by process tolerances and too costly [2], [3]. Therefore, order to overcome these disadvantages, researchers have started to focus on ASIC design of synthetic ductors. Therefore, many cases the size of ductors has been reduce, especially the higher valued ones, their cost, and add the tunability feature for quality factor tung. A part of those used several passive components grounded or floatg form. Thus, attention was widely focused on the characterization of a passive ductor as an active ductance simulator usg different analog buildg blocks (ABBs), particularly ga-variable third-generation current conveyor (GVCCIII) [3], modified dual-output differential difference current conveyor (MDO-DDCC) [4], differential secondgeneration current conveyor (DCCII) [5], [6], modified vertg and conventional first- and second-generation current conveyor (MICCI/MICCII/CCI/CCII) [7] [], dual-x secondgeneration current conveyor (DXCCII) [2], differential Research described this paper was fanced by the National Sustaability Program under grant LO4 and by the Czech Science Foundation under grant no. 6-46Y. For the research, frastructure of the SIX Center was used. voltage current conveyor (DVCC) [3], current-feedback operational amplifier (CFOA) [4], z-copy current-controlled current vertg transconductance amplifier (ZC-CCCITA) [5], positive four-termal-floatg-nullor (PFTFN) [6], differential difference operational mirrored amplifier (DDOMA) [7], voltage differencg vertg buffered amplifier (VDIBA) [8], etc. and their equivalent usg commercially available devices [9]. The aim of this paper is to crease the variety of ductance simulator circuits the literature with troduction of a new PIS topology based on two vertg voltage buffers (IVBs), unity-ga current follower/verter (CF±), and one grounded capacitor. The proposed circuit is electronically tunable via change of trsic put resistance of CF± by means of its supply voltages. The behavior of the proposed simulator circuit is tested voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. SPICE simulation results have been performed to confirm the theory. II. CIRCUIT DESCRIPTION Basic NMOS-based CMOS IVB is shown Fig. (a) [2], [2]. Considerg non-ideal IVB, which assumg that both transistors work saturation region, V THN = V THN2, +V DD = V SS, and k N = k N2, it can be described by the followg hybrid matrix: I V V s R I out IVB_o out (a) (b) Fig.. CMOS implementations: (a) vertg voltage buffer (IVB), (b) unity-ga current follower/verter (CF±).

3 (a) Fig. 2. (a) Symbol of a PIS, (b) CMOS implementation of proposed resistorless PIS cludg the ma parasitics. (b) where () the ma source of non-ideality is a non-zero output resistance R IVB_o (/g m2 ) r o of the output termal. Note that the (s) is frequency-dependent non-ideal voltage ga, which usg a sgle-pole model can be expressed as (s) = o /( + s j ), where o = ε v is DC voltage ga of IVB and ε v denotes voltage trackg error with ε v «. Similarly, the unity-ga CF± is a three-termal ABB with CMOS implementations shown Fig. (b) [8], [22] [24]. Usg standard notation and takg to account its ma parasitics, it can be described by the followg hybrid matrix: Vx Rx Ix I s sc / R V z z z z I z s scz / R z V z where (2) the ma source of non-idealities is firstly the trsic put impedance R x, which value can be found and approximated as given [22] and its value can be set via supply voltages. Equivalent resistance seen at output ports z± can be expressed as R z+ r o2 r o4 and R z r o7 r o, respectively. Secondly, the ma source of non-idealities is parasitic admittance Y z± at termals z±, which is modeled by a parallel non-ideal output resistance R z± and capacitance C z±. Note that the j (s) for j = {+, } are frequency-dependent nonideal current gas, which usg a sgle-pole model can be defed as j (s) = jo /( + s j ), where α jo = ε ij are DC current gas of CF±, ε ij denote current trackg errors described as ε ij «. In ideal case the above mentioned voltage o and current α jo gas are unity. III. INDUCTANCE SIMULATOR DESIGN Symbol of a lossless PIS and the CMOS implementation of proposed resistorless PIS cludg the ma parasitics are shown Figs. 2(a) and (b), respectively. Considerg the use of a sgle grounded capacitor and assumg non-idealities of ABBs, i.e. the put trsic resistances R xk at x termal of CF±s as useful active parameters, fite output admittances at ports z±, non-zero output resistance R IVB_ok of the output termal of IVBs, and DC voltage gas ok and current gas α jok of both ABBs for k = {, 2}, its route circuit analysis yields the followg put impedance: Z s V I RR 2 RRsC 2 Rlossy sleq Z o o2 o o2 o o2 o o2, where R k = R IVB_ok + R xk, C = C + C z, while Z = R z. Note that (3) results lossy grounded ductance simulator (serial R-L) with quality factor: Q L. eq L CRz Rlossy Hence, its quality factor of PIS is frequency dependent and has fite value. IV. SIMULATION RESULTS To verify the theoretical analysis, the proposed grounded lossless PIS Fig. 2(b) has been simulated usg SPICE program. DC power supply voltages were set +V DD = V SS =.9 V. In the design, transistors are modeled by the TSMC.8 μm level-7 LO EPI SCN8 CMOS process parameters (V THN =.3725 V, N = cm 2 /(Vs), V THP =.3948 V, P = cm 2 /(Vs), T OX = 4. nm) [25]. Ma design parameters of used ABBs are available [8] and the aspect ratios of CMOS transistors PIS are listed Table I. All simulations were done with settg temperature as 25 C. Additionally, the proposed PIS was simulated with the followg active parameters and passive element values: R k [8] and C = {2.; 38.63} pf, which result L eq = {98.36; 33.79} μh, respectively. The ideal and simulated magnitude and phase responses are shown Fig. 3. Due to parasitics, the performance of the proposed lossless PIS is reduced. TABLE I. TRANSISTOR DIMENSIONS OF PIS. NMOS Transistors W/L (m)/(m) PMOS Transistors W/L (m)/(m) M, M 2, M, M 2 54/.8 M 3, M 4, M 7, M 8, M 3, M 4 2.6/.8 M 5, M 6, M 9, M, M 5, M /.8

4 Magnitude () M k 8 Ideal Simulation for Leq = μh Simulation for Leq = μh TABLE II. PASSIVE COMPONENT VALUES AND DESIGN PARAMETERS USED IN 5TH-ORDER HIGH-PASS FILTER RLC PROTOTYPE Components Bessel Butterworth Chebyshev I approximation approximation approximation R S, R P (k) C S (pf) C S2 (pf) C S3 (pf) L P (μh) [C P_Leq (pf)] [38.63] L P2 (μh) [C P2_Leq (pf)] [7.64] [2.] 45.9 [7.96] Phase (deg.) 9 Magnitude () k k k M M M Fig. 3. Ideal and simulated magnitude and phase responses of the proposed PIS with different impedances relative to frequency. M k CF supply voltages:.7 V.9 V. V Ga (db) Fig. 5. 5th-order high-pass RLC ladder prototype. Ideal Bessel approx. Butterworth approx. Chebyshev I approx Phase (deg.) k M 5M -2 k k M M M Fig. 6. Ideal and simulated ga characteristics of the 5th-order VM high-pass filter with three different approximations. k k k M M M Fig. 4. Simulated magnitude and phase responses of the impedance of the grounded lossless PIS with value L eq = μh vs. frequency for different supply voltage of CF±. Considerg deg. phase deviation, the useful frequency ranges for L eq with values mentioned above are about 3 khz up to 3 MHz and khz up to 6 MHz, respectively. Figure 4 shows the simulated magnitude and phase responses of the impedance of the grounded lossless PIS with value L eq = μh vs. frequency for different supply voltage of CF±. To demonstrate the usefulness of the proposed resistorless grounded lossless PIS, it was used a 5th-order high-pass filter (HPF) realization. The passive RLC prototype is shown Fig. 5. Passive component values and design parameters obtaed for f MHz cut-off frequency with Bessel, Butterworth, and Chebyshev I type (with passband ripple db) approximations are given Table II. Ideal and simulated ga Ga (db) k k M M M Fig. 7. Monte Carlo analysis: Ga response changes of 5th-order VM high-pass filter with Chebyshev I approximation due to 5% tolerance of passive component values. characteristics of designed RLC ladder prototype equivalents are shown Fig. 6. In order to observe possible manufacturg process variations and their effect on 5th-order HPF designed from RLC ladder prototype equivalent based on Chebyshev I type approximations, Monte Carlo analysis was performed with

5 Percent of samples MHz n samples = 3 n divisions = 5 mean = sigma =.2888 mimum = th %ile = median = th %ile = maximum = *sigma = Fig. 8. Monte Carlo analysis: Ga variation of the 5th-order VM high-pass filter with Chebyshev I approximation at MHz. 5% tolerance for passive component values and 3 runs. Figure 7 shows the simulated ga response of the proposed filter. The histogram Fig. 8 demonstrates the variation of the ga of the selected filter at MHz. From obtaed results it can be seen that they are very good agreement with the theory. V. CONCLUSION In this paper, an electronically tunable grounded ductance simulator topology has been presented. It employs simple vertg voltage buffers and unity-ga current follower/verter as active buildg blocks and one grounded capacitor as passive element. In total it is composed of 6 Metal-Oxide-Semiconductor (MOS) transistors. Additional ma advantages of troduced ductance simulator are the followg: (i) employs grounded capacitor, (ii) resistorless circuit, (iii) composed of low number of transistors, (iv) tunability, and (v) provides high learity and wide bandwidth high frequencies. To demonstrate the validity of the proposed grounded PIS, its behavior is tested voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. The simulation results verify the theoretical analysis. REFERENCES [] F. Yuan, CMOS Active Inductors and Transformers: Prciple, Implementation, and Applications. Sprger Sci. & Bus. Media, 28. [2] G. Thanachayanont and A. Payne, CMOS floatg active ductor and its applications to bandpass filter and oscillator designs, IEEE Proc. Circuits Devices Systems, vol. 47, pp , 2. [3] E. Yuce, S. Maei, and O. Cicekoglu, Limitations of the simulated ductors based on a sgle current conveyor, IEEE Trans. Circuits Syst.I, vol. 53, pp , 26. [4] M. A. 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