CHAPTER 2 LITERATURE SURVEY

Transcription

1 20 CHAPTER 2 LITERATURE SURVEY Section 1.2 briefly describes a common method of implementing digital multiplier called Modified Booth Multiplier (MBM). The method of implementing MBM can be reduced to two basic steps create a group of partial products and then add them up to yield the final product. For the past one decade number of efforts have been made to reduce dynamic power consumption in partial products generation and adder circuits design. About 40% of the research is on techniques for reducing partial products by changing the modified booth multiplier s encoder design and the remaining 60% is on implementing low power adder circuits, error correction methods and circuit level power optimization techniques. A review from the earlier literature in this area is discussed in this chapter. Ohban et al. (2002) exploit a transition activity optimization technique, namely hardware bypassing. Since adding zero partial product generates a large number of signal transitions in the carry-adder array without affecting the results, the authors propose to dynamically bypass such addition by disabling the adders. This row-bypassing technique saves upto 27% of transitions in comparison to the traditional multiplier design. Wen et al.(2005) proposes a low power parallel multiplier design with column bypassing technique, in which some columns in the multiplier array can be turned-off whenever their outputs are known. ie, the operations in a column can be disabled if the corresponding bit in the multiplicand is 0. The circuit overhead of the column bypassing scheme is smaller than that of the row bypassing

2 21 scheme. Here only one multiplexer per adder cell is needed (compared with 2 in the row bypassing scheme). In general, bypassing technique is a generic architecture design and does not require elaborate transistor size tweaking as needed in other delay sensitive schemes. There is no need for extra clock signals and delay cells either. Chong et al. (2005) describe a low-voltage micro power bit 2 s complement array multiplier that features low switching operation. Authors attain the micro power attribute by changing most of the adders in the Adder Block by Latch Adders (LAs). In the LAs, the novelty is the realization of latches as an integral part of the adder, resulting in small power and hardware overheads. These integrated latches are effectively placed in the input of the adders, and serve to synchronize the inputs to the adder. With the latch function and simple delay circuits, the inputs are synchronized to the adders in the adder block in a predetermined chronological sequence, thereby substantially reducing the spurious switching. However, this approach serves to pipeline the multiplication operation and achieve the micro power operation by substantially reducing (by 62% and 79% compared to conventional bit and bit designs respectively) the spurious switching in the Adder Block in the multiplier. Chen et al. (2005a, 2005b) proposes an efficient Spurious Power Suppression Technique (SPST) on the Booth s multiplier and its applications in an MPEG-4 AVC/H.264 transform coding design. There are three techniques addressed in this work, which are (1) the SPST to eliminate the spurious power consumption in the H.264 standard, (2) an efficient multitransform design for H.264 exploiting the direct 2-D algorithm, and (3) the interlaced I/O schedule for integrating the proposed multi-transform design with H.264 system to solve the design challenges induced by both the realtime processing and low-power requirements. The major novelty of the work

3 22 is implementing the SPST concept on the transform architecture for H.264 IP core design. The proposed technique adopts the design concept of separating the arithmetic units into Most Significant Part (MSP) and Least Significant Part (LSP), and then freezing the MSP whenever this part of the circuit does not affect the computation result. The proposed SPST technique not only dynamically adjusts the bit-widths of the arithmetic circuits but also eliminates the glitch switches exited in them to effectively decrease the power dissipation. The post-layout simulation results show that turning on the SPST function can save average 27.38% of power dissipation of the multi-transform design. Wu et al. (2005) have designated a bit high performance multiplier based on multiplexer cells which is implemented with pass transistor logic. A multiplexer-select Booth encoder is implemented to increase the speed and reduce the hardware cost. Moreover, a partitioned method is introduced in the design to save the propagate time of final adder. Realistic simulation using extracted timing parameters from the layout expressions show that the propagation time of the critical path of the booth encoder is reduced to 50% compared to conventional design. Danysh & Tan (2005) presented the design and implementation of a vector multiplier-accumulate (MAC) unit that can perform one 64 64, two bit, four 16 16, or eight 8 8 signed/unsigned multiply-accumulates using essentially the hardware as a 64-bit MAC and without significantly more delay. The concept of shared segmentation is introduced in which the existing scalar hardware structure is segmented and then shared between vector modes. In the case of the MAC, the scalar architecture is vectorized by inserting mode-dependent masking into the partial product generation and by injecting mode-dependent kills in the carry chain of the reduction tree and final carry-propagate adder. The shared segmentation idea could be applied to other arithmetic operations, such as rotators, shifters, floating-point

4 23 addition, and multiplication. The shared segmentation vector MAC architecture is compared to an alternative vector MAC architecture used in the AltiVec implementation, which uses the shared subtree method. For 16-bit operand widths, both methods provide similar results in terms of area and delay. However, as the operand width is increased and the number of supported vector modes are increased, the shared segmentation technique becomes superior in terms of area and delay compared to the shared subtree method. Lee et al. (2005) presented new bit-parallel dual basis multipliers using the modified Booth s algorithm (MBA). The proposed multiplier inherits the advantage of the MBA and then reduces both space and time complexities. A multiplexer-based structure is proposed for realization of the proposed algorithm. The authors have shown that their multiplier saves about 9% space complexity as compared to former multipliers, if the generating polynomial is trinomial or all one polynomial. Furthermore, authors claim that the proposed multiplier is faster. Song et al. (2005) developed a systematic methodology for designing one low-error and power-efficient fixed-width MBM. By properly choosing binary thresholding and the generalized index, it derives one better error-compensation bias to improve the truncation error. Furthermore, the error-compensation bias can be easily constructed as a lower-error fixedwidth Booth multiplier at the expense of slightly increased power consumption. For the benchmark of 8 8 multipliers, the simulation results show that a reduction of 82.04% average error compared to that using the direct-truncated fixed-width Booth multiplier. Moreover, the power consumption is 40.68% compared to that of full-precision Booth multiplier design. It is suitable for VLSI signal processing applications where the accuracy, power, speed, and area issues are crucial. By properly choosing the generalized index the authors derive a better error-compensation bias. This

5 24 work is proposed in Song et al. (2007) and reduces the maximum error, average error and the variance of error, and improved truncation error. Finally the proposed fixed-width booth multiplier is successfully applied to a digital FIR filter for speech processing application and the authors claim that the performance for the consonant part is far better than that of existing fixed width booth multipliers. Two s complement n n multipliers using radix-4 MBM produce n 2 partial products. But due to the sign handling, the partial product array has a maximum height of n Kang & Gaudiot (2006) dealt with a multiplication algorithm in which the partial product are reduced. The number of steps in the generation of partial products is reduced from n + 1 to n. The 2 2 authors managed to achieve the goal of eliminating the extra row before the partial product reduction phase. This helps using less hardware in the design of the multiplier and the partial product array become more regular and easier to implement. This multiplication algorithm shows 13% speed improvement and 14% power savings for 8 8-bit multiplications and 10% speed improvement and 3% power savings for bit multiplications when compared to the conventional multiplication algorithms. A similar method that produces a partial product array with a maximum height of n 2 is proposed by Lamberti et al. (2011), without introducing any extra delay in the partial product generation stage. The effect is that the reduction of the maximum height of the partial product array by one unit shortens the partial product reduction tree, both in terms of delay and regularity of the layout. An efficient MBM design method for predetermined co-efficient group for Digital Signal Processing (DSP) application is proposed in the literature Kim et al. (2006). In this method, not only the multiplier size but also the ROM (for saving the co-efficient data) size is reduced. The

6 25 performance of the proposed method is demonstrated using two practical design examples such as 128-point radix-2 4 Fast Fourier Transform (FFT) and a pulse-shaping filter for Code Division Multiple Access (CDMA). Compared with conventional MBM, this method reduces the area, power consumption and computation time in the pulse-shaping filter design and FFT design up to 44%, 48% and 21%, and 18%, 36% and 10%, respectively. The design of an energy-efficient 2 s complement multiplier with bit and reconfigurable PLA control engine loop operating at 1 GHz in a 1.3 V, 90-nm CMOS technology is proposed by Hsu et al. (2006). The use of an optimally tiled Booth-encoded compression tree, low clock power writeport flip-flop and the arrival-profile aware completion adder resulted in the most power-efficient multiplier reported to date. The leakage component of total power was limited to 6% by maximizing the usage of high-v t and minimum sized transistors, with selective upsizing on critical paths. Multiplier performance is scalable to 1.5 GHz, 32 mw, at 1.95 V. In the lowvoltage mode of operation at 570 mv, the multiplier operates at 50 MHz and consumes 79 µw. Ultra-low standby power of 75 µw and less than 1 cycle wake-up time was achieved using PMOS sleep transistors, resulting in 7 times reduction in measured leakage compared to active mode. This prototype addresses the challenges involved in designing energy-efficient hardware for power-constrained applications in high-performance process technologies, while consuming ultra-low energy. A self-compensation method for error correction in a fixed-width Booth multipliers is proposed by Huang et al. (2006). The amount for compensating the error introduced by truncation is determined by the input data adaptively. According to the simulation results, proposed approach has improved 85% of the average error while compared with direct-truncated multiplier. But the circuit complexity can reduce to only 60% of the standard

7 26 Booth multiplier by using the proposed one. In addition, the multiplier is applied to a 128-point FFT. The approach has 10% area improvement and only 1dB SQNR loss while compared to traditional Booth multiplier. Compared with the direct-truncated multiplier approach, this approach has 10dB SQNR improvement with only 2% increase in circuit overhead. Two new signed parallel multipliers are presented by El-Razouk & Abid (2006). They achieved low-power as well as low-transistor count, mainly due to the use of two new types of partial product generators than conventional CMOS AND-NAND partial product generators. The proposed signed Array multiplier, based on the two new types of partial products, achieves 17% and 13.3% reduction in power consumption and transistor count compared to Baugh Wooley multiplier with only an increase of 4.5% in time delay. The proposed signed Tree multiplier incorporates two new lowpower low-area partial products and achieves 15.4% and 9.4% reduction in power consumption and transistor count compared to Wallace Tree multiplier with a small increase in time delay of 3.66%. The proposed multipliers are used for low power, low area and high speed digital circuits and systems for various applications including DSP. Economakos & Anagnostopoulos (2006) presented a technique for the design of low power array multiplier. The application of this method in the implementation of a Carry-Save array multiplier produces significant gains in power consumption, making it ideal for implementation of power efficient DSP VLSI systems. By conjoining this architecture with the architecture of the traditional Carry Save multiplier, bypassing only columns (or rows) with high probability to be 0, a mixed architecture can be created that offers significant power and timing savings, with a 15%-20% extra area penalty.

8 27 A new design technique for low power multiplier is introduced by Kuo & Chou (2006). This method utilizes the bypassing technique to minimize the switching activities and tree structure to decrease the critical path. The design of circuit uses the standard TSMC 0.18µm CMOS technology. Author claim that this design is greater power-efficient with less extra hardware and efficient power-delay product while compared to existing bypassing multiplier. Lee et al. (2006) proposed a novel multiplication algorithm using the modified Booth's algorithm that permits efficient VLSI realizations. The proposed algorithm uses a multiplexer-based array to implement a new bitparallel systolic multiplier. The multiplier has the latency of 3m/2 clock cycles, as opposed to 3m in previous works using AND and XOR gates. Therefore, the speed of the proposed multiplier is double. To estimate the complexity of the proposed multiplier, the design is taken into the transistor level using a standard CMOS VLSI realization. Authors claim that the proposed multiplier is less complex than other bit parallel systolic multipliers. Authors say, in terms of the time and the space complexities, the multiplexer based array architecture is the better choice for the proposed bit-parallel systolic multipliers. More than that the proposed multipliers have good features for high-speed VLSI system design, such as simplicity, regularity and modularity. Chen et al. (2006) proposed a Versatile Multimedia Functional Unit (VMFU) which computes six varieties of frequently used arithmetic operations in multimedia applications. Equipping the SPST saves 24% power dissipation at the cost of only 15% area increment, which is an acceptable trade-off particularly for modern CMOS technologies. This paper provides the design explorations for versatile designs and exploits the SPST to decrease the misused dynamic power dissipation. Hence, the planned VMFU is madeup to facilitate the rapid creation of high efficiency and low-power SoC structures.

9 28 An improved column bypassing scheme which will reduce both the circuit and power overhead of the bypassing circuitry is proposed in Hwang et al. (2006). Proposed designs successfully integrate the bypassing logic and the adder cell into one which reduces the circuit overheads and at the same time fix the DC power dissipation encountered in previous designs. The proposed schemes exhibit consistent and considerable power saving over different power supply. Another effort regarding enhanced row bypassing is suggested in Hwang et al. (2007), which reduces both the circuit and power overhead of the bypassing circuitry. C 2 MOS circuitry is adopted to serve two mechanisms called signal multiplexing (between a bypassing signal and an evaluated signal) and evaluation suspension (of the bypassed full adder). The study propose two versions of row bypassing based multiplier designs, one for maximum power saving and one for lower circuit overhead. The power saving is as high as 17% in design-1. The power saving of design-2 is at best reach 16.5% with about one half silicon area overhead. Wang & Sung (2006) propose a 2-dimensional bypassing approach which detects the nullity of the partial products as well as the multiplicand at the same time to determine whether the adding cells on the corresponding row and those on the corresponding column are skipped or not, respectively. An 8 8 bit digital multiplier using the proposed 2- dimensional bypassing design is carried out by TSMC 0.35μm 2P4M CMOS process. The post-layout simulations show that the power reduction compared to the prior multipliers is at least 75%. An architecture optimization technique to reduce the switching activity in a MBM is presented in (Mangal et al. 2007). It proposes a low power multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. A look up table is used for implementing the logic for

10 29 counting the number of ones and generation of booth recoded multiplicand. Comparing with column bypassing and other techniques this methodology guarantees to have equal or more number of zeros in the multiplicand. Effective implementation of 16x16 multiplier in FPGA is also presented. Crookes & Jiang (2007) introduce an efficient high-radix MBM algorithm, which can reduce the number of partial products to as much as one-fourth, and which avoids some of the causes of high-power consumption in the radix-16 Booth multiplier. The author claims that based on Binary Signed Digit (BSD) representation the partial products can be reused to reduce the power consumption. Power reduction is only around 50% of that of the conventional Booth multiplier. The research also suggests that BSD arithmetic, is generally regarded as less efficient because of its 2-bits per digit requirement and can have significant power saving advantages only in the specialized application of binary multiplication. Wang et al. (2007) have presented an efficient high radix iterative multiplier structure based on a novel real-time Canonical Signed Digit (CSD) recoding circuit. Because of the iterative multiplier nature, the proposed design requires lower area compared with array multipliers. Furthermore, the real-time CSD conversion ensures that the proposed design has the simplest structure among all radix-8 multipliers. Also, this multiplier has the minimum number of nonzero partial products based on the CSD number property. The number of add/subtract operations is further reduced through the use of bypass techniques. Thus, the complexity of the hardware implementation is dramatically reduced as compared to conventional methods, including modified Booth recoding and competing CSD recoding techniques. Results show that this new iterative structure delivers significant performance improvements with respect to speed, area, and power consumption relative to previous iterative multiplier designs.

11 30 Gao et al. (2007) presents an optimized design approach of two s complement large-size multipliers using embedded multipliers in FPGAs. The realization is based on Baugh-Wooley s algorithm. To achieve efficient implementation, a set of optimized schemes for the realization of the addition of partial products is proposed. The implementations of the multipliers is carried out for operands with sizes from 20 to 128 bits. The results indicate that the proposed approach outperforms the traditional methods by 50% in terms of LUT-delay product. Design of a high performance low power multiplier used in kernelbased operations for real-time video applications is proposed by Ngo & Asari (2007). The hardware design employed special characteristics in the video stream, which is the high correlation of the pixel values within a fixed size window of a neighborhood to decrease the number of operations and the switching activities in the functional modules. Higher bits of the pixel data within the same window are estimated at the same time to determine if a possible decrease of multiplications and additions can be accomplished. In addition, bit-representations of the pixel values are considered in the distributed architecture scheme to disable parts of the data paths when irrelevant values are detected. The reduced switching activity rate results in reduced dynamic power consumption of the modules. The architecture design helps to reduce up to 46% in transition rate in various applications. Author s claims that this approach can be further improved by considering hybrid multipliers to reduce the sign extension portion in the Booth multiplier. On the basis of analyzing the philosophy of multiplication process in block ciphers and modular multiplication algorithms of different operation width, Li et al. (2007) presented a high-speed reconfigurable multiplier, which can be reconfigured to achieve 16-bit, 32-bit multiplication and modulo multiplication operation, and then optimize each critical block. The

12 31 design is realized using Altera's FPGA. Synthesis, placement and routing of reconfigurable multiplier have accomplished on 0.18 µm SMIC technology. The result demonstrates that the propagation time of the critical path is 2.84ns. The reconfigurable multiplier is able to accomplish comparatively high performance in processing the block cipher algorithms. An advanced version of SPST to filter out the useless switching power in a modified booth multiplier is proposed in the literature by Chen & Chu (2007) and Chen et al. (2007). The SPST uses a detection logic circuit to detect the effective data range of arithmetic units, e.g., adders or multipliers. When a portion of data does not affect the final computing results, the data controlling circuits of the SPST, latch this portion to avoid useless data transitions occurring inside the arithmetic units. Besides, there is a data asserting control realized by using registers to further filter out the useless spurious signals of the arithmetic units every time when the latched portion is being turned on. When implemented in a 0.18µm CMOS technology, the proposed SPST-equipped multiplier dissipates only mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction than the conventional multiplier. Compared with the older version SPST, the new approach improves 40% speed of the SPST-equipped multipliers. Hu et al. (2007) proposed an adiabatic array multiplier based on modified Booth algorithm. It is composed of Booth encoders, a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-look ahead adder. All circuits are realized with DTGAL (dual transmission gate adiabatic logic) circuits using 0.18µm TSMC process. The energy loss of the proposed adiabatic Booth encoders, partial product generators and full adders is compared with their corresponding CMOS implementations. The simulation results show that the proposed adiabatic Booth encoder attains energy savings of 92.5% at 50MHz and 78.3% at

13 32 300MHz, compared with its CMOS counterpart. The adiabatic partial product generator and 1-bit full adder attain energy savings of 88.5% and 75.6% as compared to the conventional CMOS implementations at 200MHz, respectively. Wang et al. (2007) presents an adiabatic tree multiplier based on modified Booth algorithm. All circuits including Booth encoders, partial product generators, and compressors are realized with DTGAL (dual transmission gate adiabatic logic) circuits. The energy loss of the proposed adiabatic circuits is compared with their corresponding pass-transistor adiabatic logic with NMOS pull-down configuration (PAL-2N) and CMOS implementations. The proposed circuits are verified using TSMC 0.18μm CMOS technology. The power consumption is greatly reduced since the energy transferred to large load capacitances is well recovered. Lee (2008) proposed two multiplication algorithms using the modified Booth s algorithm that allows efficient VLSI realizations. The proposed algorithms can use a multiplexer-based array to implement finite field multipliers. The first architecture uses a multiply-by-α 2 method to achieve a bit-parallel systolic multiplier for a generic field of GF(2 m ); the second architecture is adopted by a multiply-by-α method to implement a bitparallel systolic multiplier with a design based on an irreducible trinomial or an irreducible pentanomial. Both multipliers have the latency of [3m/2] clock cycles, as opposed to 3m in previous works used AND and XOR gates. As compared with previous bit-parallel systolic multipliers, the proposed multipliers show that it has significantly less time area product complexity than the traditional multipliers. If finite field multiplication is applied to error correcting applications, which require large field size, proposed architectures have better time and space complexity. Moreover, the proposed multipliers

14 33 have attractive features for high-speed VLSI system design, such as simplicity, regularity and modularity. Wang et al. (2008) discuss about an improved modified Booth encoder and selector logic. Authors claim that the design is well-structured because rearranging and reducing partial products to achieve an extra-rowremoval for the multiplier is possible by their enhanced MBM and selector logic. This facilitates reduction of the gate count and improves performance of the multiplier. This research also explores various architectures of two's complement logics. It adopts a spare-tree structure in the extra-row removal mechanism to further reduce the area of the two s complementary circuit. Moreover, the hybrid two s complement logic takes advantage of the uneven arrival time of inputs to further save the area and power consumption. According to the experimental results, the design can obtain 15.8% and 11.7% reduction on the area and power savings respectively over the classical MBM design. The modified-booth algorithm is broadly used for high-speed multiplier circuits. Once, when array multiplier is used, the reduced number of generated partial products significantly enhance multiplier performance. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a constrained impact on overall performance. The Baugh-Wooley algorithm is a different scheme for signed multiplication, but is not so widely adopted because it may be difficult to deploy on irregular reduction trees. Själander & Larsson-Edefors (2008) uses the Baugh-Wooley algorithm in a High Performance Multiplier (HPM) tree, which combines a regular layout with a logarithmic logic depth. Author s shown that for a range of operator bitwidths, when implemented in 130nm and 65nm process technologies, the Baugh-Wooley multipliers exhibit

15 34 comparable delay, less power dissipation and smaller area foot-print than modified-booth multipliers. Abid et al. (2008) proposed five new hybrid full bit adder cells and three new hybrid (4:2) compressors. They are used to design an 8 8 bit array and tree topology multipliers in which partial product bits are generated by means of NAND instead of AND gates. The proposed ALL-NAND array multiplier showed a decrease of 15.7% in power dissipation and 7.8% in transistor count compared to Baugh Wooley, while the proposed ALL-NAND tree achieved a 12.5% reduction in power consumption and a 7.3% reduction in transistor count with respect to the previous (4:2) compressor based tree multipliers. These reductions are achieved at the cost of longer time delays of 6.9% for the array multiplier and 4.4% for the tree multiplier. Therefore, the All-NAND signed array and tree multipliers are promising for low area and low power applications. Saravanan & Madheswaran (2008) explore the implementation approaches of a low power Modified Booth Multiplier (MBM) with Reduced Spurious Transition Activity Technique (RSTAT) for DSP functions that encounter a wide diversity of operating scenarios in battery powered wireless sensor network system. This RSTAT approach is applied on both the compression tree of multipliers and the Booth Encoder to increase the power clampdown, for high speed and low power purposes. To filter out the spurious switching power of the multiplier, there are two approaches, one is using registers and other using AND gates, to assert the data signals of the multipliers after the data transition has been proposed. The RSTAT approach leads to a 40% reduction in power consumption and speed improvement when compared with the existing power minimization technique.

16 35 Carbognani et al. (2008) have related various 16 bit multiplier architectures in terms of dissipated energy, propagation delay, energy delay product and area occupation. These parameters are considered in the view of low power low voltage signal processing for low frequency applications. The established approach is set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It has been found that the spurious activity is a major cause of energy dissipation in multipliers. From the simulation results, it can be concluded that, as the full adder chains are shortened, the Wallace multiplier dissipated less energy than other traditional array multipliers. The transmission gate multiplier construction introduced in this work is found to be successful in reducing spurious switching activity significantly without compromising the benefits. Mudassir et al. (2008) proposed a low power algorithm using operand decomposition for radix-8 Booth multipliers. The proposed scheme decomposes both the multiplicand and multiplier to reduce the number of ones in total partial products as well as reducing the number of partial product rows to bypass the generation of hard multiples and sign extension. As a result, signal transitions are reduced, leading to lower switching activity. A Redundant Binary Signed Digit (RBSD) Modified Booth-3 (Radix-8) encoding scheme is implemented by the authors to generate RBSD partial product rows and low power redundant binary adder unit designed for accumulation thereby bypassing the need to generate hard multiples and sign extension. Experimental results show a reduction of 21% in dynamic power consumption and at least 44% reduction in Energy Delay Product (EDP) with a penalty of 4% in area, when compared with Multiplication Algorithm for Switching Activity Reduction (MASAR) technique.

17 36 An efficient Multiplier is developed using a redesigned booth multiplier based on Wen Chang booth encoderand redesigned 4:2 compressor proposed by Hussin et al. (2008). The objective of developing the fast multiplier is achieved with ns, ns and ns for 8 bit, 16 bit and 32 bit multipliers respectively. This is 2% to 7% speed improvement compared to other parallel multiplier designs. Although the improvement seems marginal, the authors claim that when implemented in a larger system, the accumulated delay is much significant. The total transistor count for this new multiplier is slightly more. This is due to the new MBE which uses more transistors. However this proposed multiplier is quite good in terms of speed. The use of Redundant Binary (RB) arithmetic in the design of highspeed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary to redundant binary number conversion. He & Chang (2009) proposed a high-speed and energy-efficient RB multiplier design based on covalent RB Booth encoding algorithm. The idea of He & Chang (2009) is to polarize the two adjacent Booth-encoded digits into a differential pair to restore the effective redundant binary partial product reduction rate without the normal binary to redundant binary number conversion overhead. The proposed method fully exploits the characteristics of the positive negative complement coding of redundant binary numbers to directly generate a redundant binary partial product from two adjacent Booth-encoded digits. Consequently, it shares the same advantages of RB Booth encoder like ease of generating hard multiples and avoidance of error compensation vector. Six redundant binary multipliers with different Booth encoding schemes are prototyped for evaluation. The

18 37 synthesis results show that the redundant binary radix-4 Booth multiplier is faster and more energy-efficient among other method refered in terms of power and word lengths of computation. A run-time multi-precision multiplier with dynamic input data range detection and unused hardware circuitry deactivation is proposed by Zhang et al. (2009). Block-wise shutdown and voltage scaling techniques are combined to disable unused hardware resources, adjust the supply voltage and clock frequency to reduce power consumption. This results in nearly a cubic reduction in dynamic power dissipation. Furthermore, by using modified Booth encoding scheme, partial products generating algorithm, and compression topology, this multiplier achieves both delay and power reduction. The design is synthesized using TSMC 0.18µm standard cell library and evaluated in Synopsys design environment. Reported results show that the multiplier achieves up to 75% power reduction with less than 10% overhead in terms of silicon area while compared with traditional multipliers. In radix-8 Booth encoding, the number of partial products is reduced to one-third. However the inevitable carry propagation adder circuit is required to generate the hard multiple, 3X, where X is the multiplicand, falls on the critical path of the multiplier. The generation of the hard multiple degrades the performance of the multiplier due to the long word-length carry propagation adder. An efficient parallel-prefix modulo 2 n 1 hard multiple generator is proposed by Muralidharan & Chang (2009). Instead of using a conventional two-operand adder, an efficient modulo 2 n 1 hard multiple generator for radix-8 Booth encoding algorithm is proposed. The performance of the proposed hard multiple generator is evaluated against existing modulo 2 n 1 adders both analytically and by synthesis results. It is found that this proposed hard multiple generator significantly reduces the area and delay complexity for any n.

19 38 Two design examples for the application of SPST are discussed in the literature by Chen & Chu (2009). The first one is an Efficient Multi- Transform Design (ETD) for MPEG-4 AVC/H.264 and the second one is a Versatile Multimedia Functional Unit (VMFU) design. The ETD can compute three transforms, i.e., the forward, inverse, and Hadamard transform, adopted in H.264 video encoding. On the other hand, the VMFU can compute six commonly used arithmetic operations in multimedia/dsp processing, i.e., addition, subtraction, multiplication, MAC, interpolation, and Sum-of- Absolute-Difference (SAD). Encapsulating the VMFUs, designers can increase the flexibility and scalability of multimedia/dsp processors. When applying the SPST to these two designs, the realization issues in every design highlydiffers from each other due to the large difference in hardwareconfiguration. However, with an elaborate design optimization, the proposed SPST can reduce power dissipation by an average of 27% and 24% for the ETD and the VMFU with 1.8-V supply voltage, respectively. A low-power architecture for shift-and-add multipliers is proposed by Mottaghi-Dastjerdi et al. (2009). The changes to the conventional architecture included the elimination of the shift of the B register (in A B), direct feeding of A to the adder, bypassing the adder whenever possible, use of a ring counter as an alternative of the binary counter, and removal of the partial product shift. The results show an average power reduction of 30% by the proposed architecture. Authors also compared the multiplier with Spurious Power Suppression Techniques (SPST), a low-power tree-based array multiplier. The comparison showed that the power saving of BZ-FAD is only 6% lower than that of SPST whereas the SPST area is five times higher than BZ-FAD. Thus, for applications where small area and high speed are important concerns, BZ-FAD is an excellent choice. Additionally, a lowpower architecture for ring counters is proposed based on partitioning the counter into blocks of flip-flops, clock gated with a special clock gating

20 39 assembly the complexity of which is independent of the block sizes. The simulation results show that the proposed architecture has reduced the power consumption more than 75% for the 64-bit counter. The design and analysis of Spurious Switching Suppression Technique (SSST) equipped low power multiplier with hybrid encoding is proposed by Saravanan & Madheswaran (2009). The proposed encoding technique reduces the number of switching activities and dynamic power consumption by analyzing the bit patterns in the input data. In this proposed encoding scheme, the operation depends upon the number of 1 s and its position in the multiplier input data. The switching activity of the proposed multiplier is reduced by 86% and 46% compared with conventional and Booth multiplier respectively. Authors say, it is observed from the device level simulation using tanner 12.6 EDA that the power consumption of the proposed multiplier has been reduced by 87% and 26% compared with conventional and Booth multiplier. Liu & Hu (2009) presented an adiabatic tree multiplier based on MBM, which operates on four phase power clocks. It is composed of Booth encoder, partial product generators followed by booth encoding, a complementary decoder that is required by the partial product generator, Wallace trees with 4-2 compressors, and a final carry-look ahead adder. All circuits are realized by Complementary Pass transistor Adiabatic Logic (CPAL) circuits with TSMC 0.18μm CMOS process technology. Compared with its CMOS counterpart based on conventional logic circuits, the fourphase adiabatic multiplier attains energy savings of 86.6% at 50MHz and 72.8% at 300MHz, respectively. Zhang et al. (2009) proposed an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (Clocked Adiabatic Logic) circuits

21 40 with TSMC 0.18μm CMOS process. The proposed single-phase adiabatic Booth encoder attains energy savings of 82% at 50MHz and 70% at 300MHz, compared with its CMOS counterpart. The single phase adiabatic partial product generator and 4-2 compressors based on the gate level attain energy savings of 80% and 76% as compared to the conventional CMOS implementations at 200MHz, respectively. Jiang (2010) presents layout optimization methods for complementary pass-transistor adiabatic logic (CPAL) circuits in order to make the circuits more energy-efficient. The layout optimizations for a lowpower tree multiplier based on modified Booth algorithm is carried out. The multiplier is realized with TSMC 0.18µm CMOS process technology with full-custom layouts, and full parasitic extraction is done. Compared with its layout of counterpart in conventional logic (static complementary CMOS logic), the adiabatic multiplier attains large energy savings. A new architecture for a high-speed multiplier-and-accumulator (MAC) is proposed by Seo and Kim (2010). In this MAC, the computations of multiplication and accumulation are combined and a hybrid-type carry save adder (CSA) structure is proposed to reduce the critical path and improve the output rate. It uses MBM algorithm based on 1 s complement number system. A modified array structure for the sign bits is used to increase the density of the operands. A carry look-ahead adder (CLA) is inserted in the CSA tree to reduce the number of bits in the final adder. In addition, in order to increase the output rate by optimizing the pipeline efficiency, intermediate calculation results are accumulated in the form of sum and carry instead of the final adder outputs. Authors claim that the proposed MAC shows superior properties compared to the standard design in many ways and performance is twice as much as the previous research on a similar clock frequency.

22 41 Chen & Yao (2010) describes a well-organized architecture for diminished-1 modulo (2 n +1) multipliers. The new architecture is constructed using a clean radix-4 Booth recoding block, an inverted end-around-carry carry save adder tree and a final diminished-1 adder. Although one correction term is used, there is no complication in the circuit. There are n/2 partial products, one simple correction term and one constant, each one n bits wide. The new multiplier can handle zero inputs and results. The analytical and experimental results point out that the new multiplier offers better speed and additional compact than previously published solutions. Saravanan & Madheswaran (2010) present the design approach of a low power high performance Multiply and Accumulate (MAC) unit with Hybrid Encoded Reduced Transition Activity Technique (HERTAT) equipped multiplier and low power 0.13µm adder. The developed low power MAC unit is tested for image processing systems exploiting irrelevant bits in pixels values and the resemblance of neighboring pixels in video streams. The suggested technique decreases dynamic power consumption by examining the bit patterns in the input data to reduce switching activities. If the number of 1 s less than or equal to three the proposed encoding method used otherwise go for conventional Booth method. The proposed adder cell used in the MAC block consumes less power than the other previous adder methods. This high recital low power MAC can be used in image processing. Authors claim that the proposed scheme reduces the switching activities in the MAC unit up to 19% and saves power up to 46% while performed device level simulation using TANNER v12.6 EDA tool. Kuang & Wang (2010) proposed a power-efficient 16times 16 configurable Booth multiplier (CBM) that supports single 16-b, single 8-b, or twin parallel 8-b multiplication processes. To efficiently decrease power consumption, a novel dynamic-range detector is developed to dynamically

23 42 sense the effective dynamic ranges of two input operands. The detection result is used to pick the operand with reduced dynamic range for Booth encoding to increase the probability of partial products becoming zero and to deactivate the redundant switching activities in ineffective ranges as much as possible. Moreover, the output product of the proposed multiplier can be truncated to further decrease power consumption by sacrificing a bit of output precision. To efficiently and correctly combine these methods, some supplementary components, including a correcting-vector generator, an adjustor, a sign-bit generator, a modified error compensation circuit, etc., are developed. Finally, three real-life applications are adopted to evaluate the power efficiency and error performance of the proposed multiplier. The results show that the proposed multiplier is more complex than non-cbms, but significant power and energy savings are achieved. Furthermore, the proposed multiplier preserves an acceptable output quality for these applications when truncation is done. Wang et al. (2011) proposed a high-accuracy error compensation circuit for the fixed-width modified Booth multiplier. The circuit makes the error distribution to be symmetric and also centralizes in zero error as much as possible. Therefore, the mean and mean-square errors are significantly reduced. The resultant fixed-width multiplier is suitable for different applications whose output data may be produced from a single multiplication or multiply-accumulation operations. Compared to the previous circuits, the proposed error compensation circuit achieves a tiny mean error and a significant reduction in mean-square error (e.g., at least 12.3% reduction for the 16-bit fixed-width multiplier) while maintaining the approximate hardware overhead.

24 43 Dimitrov et al. (2011) proposed a new method for multiplying integers. It has a provably subquadratic area and time complexity. It is based on carefully designed look-up tables that allow multiplication with a very small number of additions/ subtractions, which reduces area complexity and power consumption of the computation. As a consequence, this approach is ideally suited for many applications that require fast and low power multipliers. Authors provide extensive theoretical analysis and experimental results for multipliers based on the new representations on 0.18µm CMOS technology. Results provide a clear image about the benefits of the new scheme in 64-bit hardware implementations compared to array-based classical multiplier and radix-8-based multiplier. Muralidharan & Chang (2011) proposed a low-area and low-power radix-8 Booth encoded modulo 2 n 1 multipliers whose delay can be tuned to match the RNS delay closely. In this, the hard multiple is generated using small word-length ripple carry adders (RCAs) operating in parallel. The carry-out bits from the adders are not propagated but treated as partial product bits to be accumulated in the CSA tree. The effect of the RCA word-length, k on the time complexities of each constituent component of the multiplier is analyzed qualitatively and the multiplier delay is shown to be almost linearly dependent on the RCA word-length. Consequently, the delay of the modulo 2 n 1 multiplier is directly controlled by the word-length of the RCAs to equal the delay of the critical modulo multiplier of the RNS. By means of modulo 2 n 1 arithmetic properties, it is known that the compensation constant that negates the effect of the bias introduced in this process can be pre-computed and implemented by direct hardwiring with no delay overhead for all feasible combinations. Results show that the proposed multiplier reduces the area and power dissipation of the radix-4 Booth encoded modulo multiplier.

25 44 The design of low power high performance Multiply-Accumulate (MAC) unit using Modified Booth s Multiplier (MBM) is presented by Madheswaran & Saravanan (2012). The power analysis for MAC unit is carried out for image filtering application exploiting irrelevant bits in pixel values. The developed method is found to reduce dynamic power consumption by analyzing the bit patterns in the input data which decreases the switching activities. The power consumption of the developed multiplier is compared with existing multiplier methods and found that is performs better. It is observed from the simulation using SYNOPSIS EDA tool that the proposed pixel properties reusability technique saves power up to 88% with small area over head when used in MAC unit. Jiang et al. (2015) proposed different signed bit approximate radix- 8 Booth multiplier designs. Initially, an approximate 2-bit adder consisting of a 3-input XOR gate is proposed to calculate the triple of binary numbers. The error detection, compensation and recovery circuits of the approximate 2-bit adder are also presented. The 2-bit adder is then employed to implement the lower part of an approximate encoding adder for generating a triple multiplicand without carry propagation; it overcomes the issue commonly found in a radix-8 scheme. In the proposed signed approximate radix-8 Booth multipliers, referred to as ABM1 and ABM2, a truncation technique is employed to further save power and time. The parallel processing by a Wallace tree is then employed to speed up the addition of partial products. The simulation results show that the proposed approximate recoding adders (ARA8, ARA8-2C and ARA8-2R) are more suitable (in terms of hardware efficiency and accuracy) for a radix-8 Booth multiplier than other approximate adders.

26 45 Kumar & sahoo (2015) discuss about Vedic multipliers based on Vedic Mathematics. Vedic multipliers are presently under focus due to their high speed and low power consumption. They propose a design of 8 and 16- bit multipliers using fast adders (carry save adder, Brent- Kung adder and carry-select adder) to minimize the power delay product of multipliers intended for high-performance and low-power applications. Implementation results demonstrate that the proposed Vedic multipliers with fast adders really achieve significant improvement in delay, and power-delay product when compared with the conventional multipliers. In this chapter, a research overview of different technique used for the power reduction in Modified Booth s Multiplier for the past one decade is presented. Design techniques have clearly focused on power reduction in recent years, although the larger goal is to achieve power efficiency and performance without compromising the system functionality, which is much more difficult. In subsequent chapters, describes analysis and design of MBM for low power, using multiplier designs are down to reinforce the conclusions.