GENERAL DESCRIPTION FEATURES

Transcription

1 4-Bit Microcontroller with Built-in1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min.) GENERAL DESCRIPTION This version: Sep Previous version: Mar The ML63187B and ML63189B are CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers and operates at 0.9 V (min.). The ML63187B and 63189B are suitable for applications such as games, toys, watches, etc. which are provided with an LCD display. The ML63187B and ML63189B are M6318x series mask ROM-version product of OLMS-63K family, which employs Oki s original CPU core nx-4/250. FEATURES Rich instruction set 408 instructions Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, stack operations, flag operations, branch, conditional branch, call/return, control Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register Data memory bank internal direct addressing mode Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle Minimum instruction execution time : 61 µs (@ khz system clock) 1 µs (@2 MHz system clock) Clock generation circuit Low-speed clock : Crystal oscillation or RC oscillation selected with mask option (30 to 80 khz) High-speed clock : Ceramic oscillation or RC oscillation selected with software (2 MHz max.) Program memory space ML63187B : 16 K words ML63189B : 32 K words Basic instruction length is 16 bits/1 word Data memory space ML63187B : 1024 nibbles ML63189B : 1536 nibbles Stack level Call stack level Register stack level : 16 levels : 16 levels 1/36

2 I/O ports Input ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input Input-output ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input Selectable as P-channel open drain output/n-channel open drain output/cmos output/high-impedance output Can be interfaced with external peripherals that use a different power supply than this device uses. V DD is the power supply pin for ports. Number of ports: ML63187B Input-output port ML63189B Input port Input-output port : 2 ports 4 bits : 1 port 4 bits : 4 ports 4 bits Melody output Melody frequency Tone length Tempo Melody data Buzzer driver signal output : 529 to 2979 Hz : 63 types : 15 types : Resides in the program memory : 4 khz LCD driver Number of segments : 1024 Max. (64 SEG 16 COM) Duty : 1/1 to 1/16 duty Bias : Selectable as 1/4 or 1/5 bias regulator circuit built-in Frame frequency : 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty ), 256 Hz (at 1/4 duty), 512Hz (at 1/2 duty), 1024 Hz (at 1/1 duty ) Contrast : A maximum of 16 levels adjustable Display modes : Selectable s all-on mode/all-off mode/power down mode/normal display mode adjustable contrast. System reset function System reset by RESET pin (Built-in 2 khz RESET sampling circuit can be selected by mask option) System reset by power-on detection (When not using 2 khz RESET sampling circuit) System reset by detection that low-speed clock has stopped oscillation Battery check Low-voltage supply check The value of the judgment voltage is selected by the software by setting the LD1 and LD0 bits of BLDCON. LD1 LD0 Judgment Voltage (V) Remarks ± 0.10 Ta = 25 C ± 0.10 Ta = 25 C ± 0.10 Ta = 25 C ± 0.10 Ta = 25 C Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum 2/36

3 Timers and counter 8-bit timer 4 Selectable as auto-reload mode/capture mode/clock frequency measurement mode Watchdog timer Hz timer 1 Measurable in steps of 1/100 sec. 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read Shift register Shift clock Data length : 1 or 1/2 system clock, timer 1 overflow, external clock : 8 bits Interrupt sources ML63187B External interrupt : 2 Internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt) ML63189B External interrupt : 3 Internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt) Operating temperature 20 to +70 C Operating voltage When backup used When backup not used : 0.9 to 2.7 V (Operating frequency: 30 to 80 khz) 1.2 to 2.7 V (Operating frequency: 300 to 500 khz) 1.5 to 2.7 V (Operating frequency: 200 khz to 1 MHz) : 1.8 to 5.5 V (Operating frequency: 200 khz to 2 MHz) Package: Chip (ML63187B: 111 pads, ML63189B: 123 pads): (Product name: ML63187B-xxxWA, ML63189B-xxxWA) 128-pin plastic QFP (QFP128-P K) : (Product name: ML63187B-xxxGA, ML63189B-xxxGA) xxx indicates a code number. 3/36

4 MASK OPTION In the ML63187B and ML63189B use the mask option to specify the following functions: Low-Speeed clock oscillation circuit Specify the crystal oscillation circuit or the RC oscillation circuit for the low-speed clock oscillation circuit. Reset signal sampling Specify whether or not the reset signal will be sampled at 2 khz. When specifying will carry out 2 khz sampling, hold the RESET pin at a H level for 1 ms or more. To use the mask option, assign mask option data in the application program in accordance with the formats below. The mask option area for each device is an application program execution disabled area. Mask Option Data Assignment Format Function Mask option area bit data Option to be selected Low-speed clock oscillation circuit (crystal oscillation circuit/rc oscillation circuit) Reset signal sampling (will/will not carry out 2 khz sampling) 0 Crystal oscillation circuit ML63187B:3FE0H bit 0 1 RC oscillation circuit 0 Will carry out 2 khz sampling ML63189B:7FE0H bit 1 1 Will not carry out 2 khz sampling 4/36

5 BLOCK DIAGRAM (ML63187B) An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from V DDI (power supply for interface). CPU CORE nx-4/250 TIMING CON- TROL CBR EBR H X L Y RA A PC ROM 16 KW SP RSP ALU C G Z MIE BUS CON- TROL STACK CAL : 16-level REG : 16-level INSTRUCTION DECODER IR RAM 1024N INT 4 TIMER 8 bit 4 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* RESET TST1 TST2 RST TST INT 4 INT187 TBC INT 1 SFT SCLK* SIN* SOUT* XT0 XT1 OSC0 OSC1 OSC INT 1 INT 1 BLD 100 HzTC WDT DATA BUS INT 1 MELODY MD MDB V DDH V DD CB1 CB2 BACK UP INT 2 I/O PORT PB.0-PB.3 PE.0-PE.3 V DD1 V DD2 V DD3 V DD4 V DD5 C1 BIAS LCD & DSPR COM1-16 SEG0-63 C2 V DD1 V SS V DDL 5/36

6 BLOCK DIAGRAM (ML63189B) An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from V DDI (power supply for interface). CPU CORE nx-4/250 TIMING CON- TROL CBR EBR H X L Y RA A PC ROM 32 KW SP RSP ALU C G Z MIE BUS CON- TROL STACK CAL : 16-level REG : 16-level INSTRUCTION DECODER IR RAM 1536N INT 4 TIMER 8 bit 4 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* INT RESET RST INT189 1 SCLK* TST1 TST2 XT0 XT1 OSC0 TST OSC INT 4 INT 1 TBC BLD 100 HzTC DATA BUS INT 1 INT 1 SFT MELODY SIN* SOUT* MD MDB OSC1 INT 1 WDT INPUT PORT P0.0-P0.3 V DDH P9.0-P9.3 V DD CB1 CB2 V DD1 V DD2 BACK UP INT 2 I/O PORT PA.0-PA.3 PB.0-PB.3 PE.0-PE.3 V DD3 V DD4 BIAS V DD5 C1 C2 LCD & DSPR COM1-16 SEG0-63 V DDI V DDL V SS 6/36

7 7/36 PIN CONFIGURATION (TOP VIEW) (ML63187B) 128-Pin Plastic QFP Note: Pins marked as are no-connection pins which are left open SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG RESET OSC0 OSC1 V DDL V DD CB2 CB1 V DDH C2 C1 V DD5 V DD4 V DD3 V DD2 VDD1 VSS COM16 COM15 COM14 COM SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB.3 PB.2 PB.1 PB.0 PE.3 PE.2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG COM9 COM10 COM11 COM PE.1 PE.0 V DDI MDB MD TST2 TST1 XT0 XT1 SEG12 SEG13 SEG14 SEG15 SEG16 SEG

8 PAD CONFIGURATION (ML63187B) Pad Layout V DDI 83 PE.0 84 PE.1 85 PE.2 86 PE.3 87 PB.0 88 PB.1 89 PB.2 90 PB.3 91 COM1 92 COM2 93 COM3 94 COM4 95 COM5 96 COM6 97 COM7 98 COM8 99 SEG0 100 SEG1 101 SEG2 102 SEG3 103 SEG4 104 SEG5 105 SEG6 106 SEG7 107 SEG8 108 SEG9 109 SEG SEG COM COM11 COM COM9 SEG63 51 SEG62 50 SEG61 49 SEG60 48 SEG59 47 SEG58 46 SEG57 45 SEG56 44 SEG55 43 SEG54 42 SEG53 41 SEG52 40 SEG51 39 SEG50 38 SEG49 37 SEG48 36 SEG47 35 SEG46 34 SEG45 33 SEG44 32 SEG SEG42 SEG SEG40 SEG39 27 SEG38 SEG12 1 SEG13 2 SEG14 3 SEG15 4 SEG16 5 SEG17 6 SEG18 7 SEG19 8 SEG20 9 SEG21 10 SEG22 11 SEG23 12 SEG24 13 SEG25 14 SEG26 15 SEG27 16 SEG28 17 SEG29 18 SEG30 19 SEG31 20 SEG32 21 SEG33 22 SEG34 23 SEG35 24 SEG36 25 SEG MDB 81 MD 80 TST2 79 TST1 78 XT0 77 XT1 76 RESET 75 OSC0 74 OSC1 ML VDDL 72 VDD 71 CB2 70 CB1 69 VDDH 68 C2 67 C1 66 VDD5 65 VDD4 64 VDD3 63 VDD2 62 VDD1 61 VSS 60 COM16 59 COM15 58 COM14 57 COM13 (0,0) Y X Chip size : mm mm Chip thickness : 350 µm (280 µm: available as required) Coordinate origin : center of chip Pad hole size : 100 µm 100 µm Pad size : 110 µm 110 µm Minimum pad pitch : 140 µm Note: The chip substrate voltage is V SS. 8/36

9 Pad Coordinates (ML63187B) Center of chip: X = 0, Y = 0 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) 1 SEG SEG V DDI SEG SEG PE SEG SEG PE SEG SEG PE SEG SEG PE SEG SEG PB SEG SEG PB SEG SEG PB SEG SEG PB SEG SEG COM SEG SEG l COM SEG COM COM SEG COM COM SEG COM COM SEG COM COM SEG COM COM SEG COM COM SEG COM SEG SEG COM SEG SEG V SS SEG SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG C SEG SEG C SEG SEG V DDH SEG SEG CB SEG SEG CB SEG V DD SEG V DDL SEG OSC SEG OSC SEG RESET SEG XT SEG XT SEG TST SEG TST SEG MD SEG MDB /36

10 10/36 PIN CONFIGURATION (TOP VIEW) (ML63189B) 128-Pin Plastic QFP Note: Pins marked as are no-connection pins which are left open SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM16 COM15 COM14 COM13 COM12 COM SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 P0.3 P0.2 P0.1 P0.0 P9.3 P9.2 P9.1 P9.0 PA.3 PA.2 PA.1 PA.0 PB.3 PB.2 PB.1 PB.0 PE.3 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM PE.2 PE.1 PE.0 V DDI MDB MD TST2 TST1 XT0 XT1 RESET OSC0 SEG4 SEG5 SEG6 SEG7 SEG8 SEG

11 PAD CONFIGURATION (ML63189B) Pad Layout 92 MDB 70 COM16 69 COM15 68 COM14 67 COM13 66 COM12 65 COM11 64 COM10 V DDI 93 PE.0 94 PE.1 95 PE.2 96 PE.3 97 PB.0 98 PB.1 99 PB PB PA PA PA PA P P P P P P P P COM1 114 COM2 115 COM3 116 COM4 117 COM5 118 COM6 119 COM7 120 COM8 121 SEG0 122 SEG SEG63 61 SEG62 60 SEG61 59 SEG60 58 SEG59 57 SEG58 56 SEG SEG56 SEG SEG54 SEG53 51 SEG52 50 SEG51 49 SEG50 48 SEG49 47 SEG48 46 SEG47 45 SEG46 44 SEG45 43 SEG44 42 SEG43 41 SEG42 40 SEG41 39 SEG40 38 SEG39 37 SEG38 36 SEG37 35 SEG36 34 SEG SEG34 SEG33 31 SEG32 SEG2 1 SEG3 2 SEG4 3 SEG5 4 SEG6 5 SEG7 6 SEG8 7 SEG9 8 SEG10 9 SEG11 10 SEG12 11 SEG13 12 SEG14 13 SEG15 14 SEG16 15 SEG17 16 SEG18 17 SEG19 18 SEG20 19 SEG21 20 SEG22 21 SEG23 22 SEG24 23 SEG25 24 SEG26 25 SEG27 26 SEG28 27 SEG29 28 SEG30 29 SEG MD 90 TST2 89 TST1 88 XT0 87 XT1 86 RESET 85 OSC0 84 OSC1 83 VDDL 82 VDD 81 CB2 80 CB1 79 VDDH 78 C2 77 C1 76 VDD5 75 VDD4 74 VDD3 73 VDD2 72 VDD1 71 VSS 63 COM9 (0,0) Y X ML63189B Chip size : 4.81 mm 5.20 mm Chip thickness : 350 µm (280 µm: available as required) Coordinate origin : center of chip Pad hole size : 100 µm 100 µm Pad size : 110 µm 110 µm Minimum pad pitch : 140 µm Note: The chip substrate voltage is V SS. 11/36

12 Pad Coordinates (ML63189B) Center of chip: X = 0, Y = 0 Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) 1 SEG SEG V DDL SEG SEG OSC SEG SEG OSC SEG SEG RESET SEG SEG XT SEG SEG XT SEG SEG TST SEG SEG TST SEG SEG MD SEG SEG MDB SEG SEG V DDI SEG SEG PE SEG SEG PE SEG SEG PE SEG SEG PE SEG SEG PB SEG SEG PB SEG SEG PB SEG SEG PB SEG SEG PA SEG SEG PA SEG COM PA SEG COM PA SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG V SS P SEG V DD P SEG V DD COM SEG V DD COM SEG V DD COM SEG V DD COM SEG C COM SEG C COM SEG V DDH COM SEG CB COM SEG CB SEG SEG V DD SEG /36

13 PIN DESCRIPTIONS The basic functions of each pin of the ML63187B, ML63189B are described in Table 1. A symbol with a slash (/) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, denotes a power supply pin, I an input pin, O an output pin, and I/O an input-output pin. Table 1 Pin Descriptions (Basic Functions) Function Power Supply Oscillation Pin No. Pad No. Symbol Type ML63187B ML63189B ML63187B ML63189B V DD Positive power supply V SS Negative power supply V DD V DD V DD V DD V DD C C V DDI V DDL V DDH CB CB XT I XT O OSC I OSC O Description Power supply pins for LCD bias (internally generated) Capacitors () should be connected between these pins and V SS. Capacitor connection pins for LCD bias generation A capacitor () should be connected between C1 and C2. Positive power supply pin for external interface (power supply for input, and input-output ports) Positive power supply pin for internal logic (internally generated) A capacitor () should be connected between this pin and V SS. Voltage multiplier pin for power supply backup (internally generated) A capacitor (1.0 µf) should be connected between this pin and V SS. Pins to connect a capacitor for voltage multiplier A capacitor (1.0 µf) should be connected between CB1 and CB2. Low-speed clock oscillation pins An option for using crystal oscillation or RC oscillation is chosen by the mask option. If the crystal oscillation is chosen, a crystal should be connected between XT0 and XT1, and capacitor (C G ) should be connected between XT0 and V SS. If the RC oscillation is chosen, external oscillation resistor (R OSL ) should be connected between XT0 and XT1. High-speed clock oscillation pins A ceramic resonator and capacitors (C L0, C L1 ) or external oscillation resistor (R OSH ) should be connected to these pins. 13/36

14 Function Symbol Table 1 Pin Descriptions (Basic Functions) (continued) Pin No. Pad No. Type ML63187B ML63189B ML63187B ML63189B Description Test TST I Input pins for testing A pull-down resistor is internally connected to TST I these pins. The user cannot use these pins. Reset RESET I Reset input pin Setting this pin to H Ievel puts this device into a reset state. Then, setting this pin to L Ievel starts executing an instruction from address 0000H. A pull-down resistor is internally connected to this pin. An option of using RESET sampling circuit or not is chosen by the mask option. When using RESET sampling circuit, the system reset mode is entered by holding the RESET pin at a H Ievel for 1 ms or more. Melody MD O Melody output pin (non-inverted output) MDB O Melody output pin (inverted output) Port P0.0/INT P0.1/INT P0.2/INT P0.3/INT P P P P PA PA PA PA PB.0/INT0/ TM0CAP/ TM0OVF PB.1/INT0/ TM1CAP/ TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK PE.0/SIN PE.1/SOUT PE.2/SCLK PE.3/INT I I/O I/O I/O I/O 4-bit input ports Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. Applied to the ML63189B only. 4-bit input-output ports In input mode, pull-up resistor input, pulldown resistor input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit. P9.0 to P9.3 and PA.0 to PA.3 are applied to the ML63189B only. 14/36

15 Table 1 Pin Descriptions (Basic Functions) (continued) Function LCD Symbol Pin No. Pad No. ML63187B ML63189B ML63187B ML63189B COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG Type Description LCD common signal output pins O LCD segment signal output pins O 15/36

16 Table 1 Pin Descriptions (Basic Functions) (continued) Function LCD Symbol Pin No. Pad No. ML63187B ML63189B ML63187B ML63189B SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG Type Description O LCD segment signal output pins 16/36

17 Table 2 shows the secondary functions of each pin of the ML63187B, ML63189B. Table 2 Pin Descriptions (Secondary Functions) Function External Interrupt Symbol Pin No. Pad No. ML63187B ML63189B ML63187B ML63189B PB.0/INT PB.1/INT I PB.2/INT PB.3/INT PE.3/INT I P0.0/INT P0.1/INT I P0.2/INT P0.3/INT Description External 0 interrupt input pins The change of input signal level causes an interrupt to occur. The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit. External 2 interrupt input pin The change of input signal level causes an interrupt to occur. External 5 interrupt input pins The change of input signal level causes an interrupt to occur. The Port 0 Interrupt Enable register (P0IE) enable or disable an interrupt for each bit. Applied to the ML63189B only. Capture PB.0/TM0CAP I Timer 0 capture input pin PB.1/TM1CAP I Timer 1 capture input pin PB.0/TM0OVF O Timer 0 overflow flag output pin Timer PB.1/TM1OVF O Timer 1 overflow flag output pin PB.2/T02CK I PB.3/T13CK I External clock input pin for timer 0 and timer 2 External clock input pin for timer 1 and timer 3 PE.0/SIN I Shift register receive data input pin Shift Register PE.1/SOUT O Shift register transmit data output pin PE.2/SCLK I/O Shift register clock input-output pin Clock output when this device is used as a master processor. 17/36

18 ABSOLUTE MAXIMUM RATINGS (V SS = 0 V) Parameter Symbol Condition Rating Unit Power Supply Voltage 1 V DD1 Ta = 25 C 0.3 to +1.6 V Power Supply Voltage 2 V DD2 Ta = 25 C 0.3 to +2.9 V Power Supply Voltage 3 V DD3 Ta = 25 C 0.3 to +4.2 V Power Supply Voltage 4 V DD4 Ta = 25 C 0.3 to +5.5 V Power Supply Voltage 5 V DD5 Ta = 25 C 0.3 to +6.8 V Power Supply Voltage 6 V DD Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 7 V DDI Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 8 V DDH Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 9 V DDL Ta = 25 C 0.3 to +6.0 V Input Voltage 1 V IN1 V DD Input, Ta = 25 C 0.3 to V DD +0.3 V Input Voltage 2 V IN2 V DDI Input, Ta = 25 C 0.3 to V DDI +0.3 V Output Voltage 1 V OUT1 V DD1 Output, Ta = 25 C 0.3 to V DD V Output Voltage 2 V OUT2 V DD2 Output, Ta = 25 C 0.3 to V DD V Output Voltage 3 V OUT3 V DD3 Output, Ta = 25 C 0.3 to V DD V Output Voltage 4 V OUT4 V DD4 Output, Ta = 25 C 0.3 to V DD V Output Voltage 5 V OUT5 V DD5 Output, Ta = 25 C 0.3 to V DD V Output Voltage 6 V OUT6 V DD Output, Ta = 25 C 0.3 to V DD +0.3 V Output Voltage 7 V OUT7 V DDI Output, Ta = 25 C 0.3 to V DDI +0.3 V Output Voltage 8 V OUT8 V DDH Output, Ta = 25 C 0.3 to V DDH +0.3 V Storage Temperature T STG 55 to +150 C 18/36

19 RECOMMENDED OPERATING CONDITIONS When backup is used (V SS = 0 V) Parameter Symbol Condition Range Unit Operating Temperature T op 20 to +70 C Operating Voltage V DD 0.9 to 2.7 V V DDI 0.9 to 5.5 V Crystal Oscillation Frequency f XT C G = 5 to 25 pf to 76.8 khz Low-Speed RC Oscillation Frequency R OSL = 1.0 MΩ 36 ±30% f ROSL R OSL = 1.1 MΩ 33 ±30% R OSL = 1.2 MΩ 30 ±30% khz V DD = 0.9 to 1.2 V Not applied Ceramic Oscillation Frequency f CM V DD = 1.2 to 2.7 V 300k to 500k V DD = 1.5 to 2.7 V 200k to 1M Hz High-speed RC Oscillation Frequency f ROSH V DD = 0.9 to 1.2 V Not applied R OSH = 400 kω 200k ±30% V DD = 1.2 to 2.7 V R OSH = 100 kω 700k ±30% R OSH = 75 kω 1M ±30% Hz When backup is not used (V SS = 0 V) Parameter Symbol Condition Range Unit Operating Temperature T op 20 to +70 C Operating Voltage V DD 1.8 to 5.5 V DDI 1.8 to 5.5 Crystal Oscillation Frequency f XT C G = 5 to 25 pf to 76.8 khz Low-Speed RC Oscillation Frequency R OSL = 1.0 MΩ 36 ±30% f ROSL R OSL = 1.1 MΩ 33 ±30% R OSL = 1.2 MΩ 30 ±30% Ceramic Oscillation Frequency f CM V DD = 1.8 to 5.5 V 200k to 2M Hz High-speed RC Oscillation Frequency f ROSH V DD = 1.8 to 5.5 V R OSH = 100 kω 700k ±30% R OSH = 75 kω 1M ±30% R OSH = 51 kω 1.35M ±30% V DD = 1.8 to 3.5 V, R OSH = 30 kω 2M ±30% V khz Hz 19/36

20 Typical characteristics of low-speed RC oscillation When backup is used/backup is not used (V DD = V DDI = 1.5 V/V DD = V DDI = 3.0 V) 1000 Reference data frosl [khz] R OSL [kω] Typical characteristics of high-speed RC oscillation When backup is used (V DD = V DDI = 1.5 V) Reference data frosh [khz] R OSH [kω] 20/36

21 Typical characteristics of high-speed RC oscillation When backup is not used (V DD = V DDI = 3.0 V) Reference data frosh [khz] R OSH [kω] 21/36

22 ELECTRICAL CHARACTERISTICS DC Characteristics (1) (V DD = V DDI = 0.9 to 5.5 V, V SS = 0 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit V DD2 Voltage V DD2 1/5 bias, 1/4 bias (Ta = 25 C) V V DD2 Voltage Temperature Deviation V DD2 4 mv/ C V DD1 Voltage V DD1 1/5 bias, 1/4 bias Typ /2 V DD2 Typ V 1/5 bias Typ /2 V DD2 Typ V DD3 Voltage V DD3 1/4 bias (connect V DD3 and V DD2 ) Typ. 0.2 V DD2 Typ V Measuring Circuit 1/5 bias Typ V DD2 Typ V DD4 Voltage V DD4 1/4 bias Typ /2 V DD2 Typ /5 bias Typ /2 V DD2 Typ V DD5 Voltage V DD5 1/4 bias Typ V DD2 Typ V V V DDH Voltage (Backup used) V DDH High-speed clock oscillation stopped V DD = 1.5 V High-speed clock oscillation (Ceramic oscillation, 1 MHz) V DD = 1.5 V High-speed clock oscillation V DDL Voltage V DDL stopped High-speed clock oscillation (V DD = 1.2 to 5.5 V) Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detect Time External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance External Ceramic Oscillator Capacitance Internal RC Oscillator Capacitance V STA Oscillation start time: within 5 seconds V V V V 1.2 V Backup 0.9 V V HOLD Backup not used 1.7 V T STOP ms C G 5 25 pf C D pf C L0,1 CSA2.00MG (Murata MFG.-make) used V DD = 3.0 V 30 pf C OS pf V DD = 1.5 V V POR Voltage V POR1 V DD = 3.0 V V 1 V DD = 1.5 V V Non-POR Voltage V POR2 V DD = 3.0 V V LD1 = 1, LD0 = 1, Ta = 25 C BLD Judgment Voltage BLD Judgment Voltage Temperature Deviation V BLDC V BLDC LD1 = 1, LD0 = 0, Ta = 25 C LD1 = 0, LD0 = 1, Ta = 25 C LD1 = 0, LD0 = 0, Ta = 25 C V BLDC = 2.40 V (LD1 = 1, LD0 = 1) 3.5 V BLDC = 1.80 V (LD1 = 1, LD0 = 0) 2.3 V BLDC = 1.20 V (LD1 = 0, LD0 = 1) 1.6 V BLDC = 1.05 V (LD1 = 0, LD0 = 0) 1.2 V mv/ C 22/36

23 Notes:1. T STOP indicates that if the crystal oscillator stops over the value of T STOP, the system reset occurs. 2. POR denotes Power On Reset. 3. V POR1 indicates that POR occurs when V DD falls from V DD to V POR1 and again rises up to V DD. 4. V POR2 indicates that POR does not occur when V DD falls from V DD to V POR2 and again rises up to V DD. 23/36

24 DC Characteristics (2) When backup is used ( khz crystal is used for the low-speed clock, V DD = V DDI = 1.5 V, V SS = 0 V, 1/5 bias, LCD contrast (DSPCNT) = 0H, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Supply Current 1 I DD1 (High-speed clock CPU is in HALT state. Ta = 20 to +50 C oscillation stopped) Ta = 20 to +70 C 5 10 Supply Current 2 I DD2 CPU is in HALT state. LCD is in Power Down mood. (High-speed clock oscillation stopped) Supply Current 3 I DD3 low-speed oscillation. (High-speed clock CPU is in operation at oscillation stopped) Supply Current 4 I DD4 (approx. 700 khz RC oscillation, CPU is in operation at high-speed oscillation R OSH = 100 kω ) Supply Current 5 I DD5 CPU is in operation at high-speed oscillation (Ceramic oscillation, 1 MHz) When backup is not used Ta = 20 to +50 C 4 5 Ta = 20 to +70 C 4 8 Ta = 20 to +50 C Ta = 20 to +70 C µa µa µa µa µa Measuring Circuit ( khz crystal is used for the low-speed clock, V DD = V DDI = 3.0 V, V SS = 0 V, 1/5 bias, LCD contrast (DSPCNT) = 0H, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Supply Current 1 I DD1 (High-speed clock CPU is in HALT state. Ta = 20 to +50 C oscillation stopped) Ta = 20 to +70 C Supply Current 2 I DD2 CPU is in HALT state. LCD is in Power Down mood. (High-speed clock oscillation stopped) Supply Current 3 I DD3 low-speed oscillation. (High-speed clock CPU is in operation at oscillation stopped) Supply Current 4 I DD4 (approx. 700 khz RC oscillation, CPU is in operation at high-speed oscillation R OSH = 100 kω ) Supply Current 5 I DD5 CPU is in operation at high-speed oscillation (Ceramic oscillation, 2 MHz) Ta = 20 to +50 C Ta = 20 to +70 C Ta = 20 to +50 C Ta = 20 to +70 C µa µa µa µa µa 1 Measuring Circuit 1 24/36

25 DC Characteristics (3) (V DD = V DDI = V DDH = 3.0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Output Current 1 (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) I OH1 V OH1 = V DDI 0.5 V V DDI = 1.5 V ma V DDI = 3.0 V ma V DDI = 5.0 V ma V DDI = 1.5 V ma Measuring Circuit Output Current 2 (MD, MDB) Output Current 3 (SEG0 to SEG63) (COM1 to COM16) Output Current 4 (OSC1) Output Leakage Current (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) I OL1 V OL1 = 0.5 V V DDI = 3.0 V ma V DDI = 5.0 V ma V DD = 1.5 V ma I OH2 V OH2 = V DD 0.7 V V DD = 3.0 V ma V DD = V DDH = 5.0 V ma V DD = 1.5 V ma I OL2 V OL2 = 0.7 V V DD = 3.0 V ma V DD = V DDH = 5.0 V ma I OH3 V OH3 = V DD5 0.2 V (V DD5 Ievel) 4 µa I OHM3 V OHM3 = V DD V (V DD4 Ievel) 4 µa I OHM3S V OHM3S = V DD4 0.2 V (V DD4 Ievel) 4 µa I OMH3 V OMH3 = V DD V (V DD3 Ievel) 4 µa I OMH3S V OMH3S = V DD3 0.2 V (V DD3 Ievel) 4 µa I OML3 V OML3 = V DD V (V DD2 Ievel) 4 µa I OML3S V OML3S = V DD2 0.2 V (V DD2 Ievel) 4 µa I OLM3 V OLM3 = V DD V (V DD1 Ievel) 4 µa I OLM3S V OLM3S = V DD1 0.2 V (V DD1 Ievel) 4 µa I OL3 V OL3 = V SS V (V SS Ievel) 4 µa I OH4R I OL4R I OH4C I OL4C V OH4R = V DDH 0.5 V V DD = V DDH = 3.0 V ma (RC oscillation) V DD = V DDH = 5.0 V ma V OL4R = 0.5 V V DD = V DDH = 3.0 V ma (RC oscillation) V DD = V DDH = 5.0 V ma V OH4C = V DDH 0.5 V V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa V OL4C = 0.5 V V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa I OOH V OH = V DDI 0.3 µa I OOL V OL = V SS 0.3 µa *: Applied to the ML63189B only. 2 25/36

26 DC Characteristics (4) (V DD = V DDI = V DDH = 3.0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Input Current 1 (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Input Current 2 (OSC0) Input Current 3 (RESET) I IH1 I IL1 V OH1 = V DDI (when pulled up) V IL1 = V SS (when pulled up) V DDI = 1.5 V µa V DDI = 3.0 V µa V DDI = 5.0 V µa V DDI = 1.5 V µa V DDI = 3.0 V µa V DDI = 5.0 V µa I IH1Z V IH1 = V DDI (in a high impedance state) 0 1 µa I IL1Z V IL1 = V SS (in a high impedance state) 1 0 µa I IL2 V IL2 = V SS V DD = V DDH = 3.0 V µa (when pulled up) V DD = V DDH = 5.0 V µa I IH2R V IH2R = V DDH (RC oscillation) 0 1 µa I IL2R V IL2R = V SS (RC oscillation) 1 0 µa I IH2C I IL2C V IH2C = V DDH V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa V IL2C = V SS V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa V DD = 1.5 V µa I IH3 V IH3 = V DD V DD = 3.0 V µa V DD = V DDH = 5.0 V ma Measuring Circuit 3 Input Current 4 (TST1, TST2) I IL3 V IL3 = V SS 1 0 µa V DD = 1.5 V µa I IH4 V IH4 = V DD V DD = 3.0 V ma V DD = V DDH = 5.0 V ma I IL4 V IL4 = V SS 1 0 µa *: Applied to the ML63189B only. 26/36

27 DC Characteristics (5) (V DD = V DDI = V DDH = 3.0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit V Input Voltage 1 V DDI = 1.5 V V (P0.0 to P0.3)* V DDI = 3.0 V V IH1 (P9.0 to P9.3)* V DDI = 5.0 V V (PA.0 to PA.3)* (PB.0 to PB.3) V DDI = 1.5 V V (PE.0 to PE.3) V IL1 V DDI = 3.0 V V V DDI = 5.0 V V Measuring Circuit Input Voltage 2 (OSC0) V DD = V DDH = 3.0 V V V IH2 V DD = V DDH = 5.0 V V Input Voltage 3 (RESET, TST1, TST2) V IL2 V DD = V DDH = 3.0 V V V DD = V DDH = 5.0 V V V DD = 1.5 V V V IH3 V DD = 3.0 V V V DD = 5.0 V V V DD = 1.5 V V V IL3 V DD = 3.0 V V V DD = 5.0 V V 4 Hysteresis Width 1 (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) V T1 V DDI = 1.5 V V V DDI = 3.0 V V V DDI = 5.0 V V Hysteresis Width 2 V DDI = 1.5 V V (RESET, TST1, TST2) V T2 V DDI = 3.0 V V VDDI = 5.0 V V Input Pin Capacitance (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) C IN 5 pf 1 *: Applied to the ML63189B only. 27/36

28 Measuring circuit 1 Cb12 C12 1 *1 2 CB1 CB2 C1 C2 OSC0 OSC1 VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL XT0 XT1 3 *2 4 A Ca Cb V Cc V Cd V Ce V Ch V Cl V V Ca,Cb,Cc,Cd,Ce,Cl,C12 Ch,Cb12 CG CL0 CL1 Ceramic Resonator : : : : : : 1 µf 15 pf 30 pf 30 pf CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG-.make) *1 RC Oscillator *2 RC Oscillator ROSH ROSL Ceramic Oscillator CL0 CL1 1 Ceramic Resonator 2 Crystal Oscillator 3 Crystal 4 CG 28/36

29 Measuring circuit 2 V IH *3 *2 INPUT OUTPUT A V ll V SS V DD V DDl V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL *2 Input logic circuit to determine the specified measuring conditions. *3 Measured at the specified output pins. Measuring circuit 3 V IH *4 INPUT OUTPUT Waveform Monitoring V IL V SS V DD V DDl V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL *4 Measured at the specified input pins. Measuring circuit 4 *4 A INPUT OUTPUT V SS V DD V DDl V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL 29/36

30 AC Characteristics (Serial Interface, Shift Register) (V DD = 0.9 to 5.5 V, V DDH = 1.8 to 5.5 V, V SS = 0 V, V DDI = 5.0 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCLK Input Fall Time t f 1.0 µs SCLK Input Rise Time t r 1.0 µs SCLK Input L Level Pulse Width SCLK Input H Level Pulse Width t CWL 0.8 µs t CWH 0.8 µs SCLK Input Cycle Time t CYC V DDI = 5 V to V DD 1.8 µs SCLK Output Cycle Time t CYC1(O) CPU in operation state at khz 30.5 µs t CYC2(O) CPU in operation at 2 MHz V DD = V DDH = 1.8 to 3.5 V 0.5 µs SOUT Output Delay Time t DDR Output load capacitance 10 pf 0.4 µs SIN Input Setup Time t DS 0.5 µs SIN Input Hold Time t DH 0.8 µs AC characteristics timing ( H level = 4.0 V, L level = 1.0 V) t CYC SCLK (PE.2) 5 V (V DDl ) t r t f 0 V (V SS ) t CWH t CWL t DDR t DDR SOUT (PE.1) 5 V (V DDI ) t DS t DH t DS 0 V (V SS ) SIN (PE.0) 5 V (V DDI ) 0 V (V SS ) 30/36

31 APPLICATION CIRCUITS (ML63187B) Crystal khz XT0 COM1-16 LCD SEG0-63 OSC0 Crystal oscillation is selected as low-speed oscillation by mask option. RC oscillation is selected as high-speed oscillation by software. Ports are powered from external memory power source. C V is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C l, C b12, C 12, C h, and C G, are for reference only. C G 5 to 25 pf 1.5 V C v C l C e C d C c C b C a Buzzer C h 1.0 µf C b12 C µf 1.0 µf XT1 V DDH V DD CB1 CB2 V DDL V DD5 V DD4 V DD3 V DD2 V DD1 C1 Push SW C2 RESET TST1 TST2 MD ML63187B OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 V DDl R OSH V DD MDB V SS Note: V DDI is the power supply pin for the input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup 31/36

32 C G V DD 5 to 25 pf 5.0 V C v C l C e C d C c C v C a C 12 Buzzer Crystal khz Open Push SW XT0 XT1 V DDH V DD CB1 CB2 V DDL V DD5 V DD4 V DD3 V DD2 V DD1 C1 C2 RESET TST1 TST2 MD COM1-16 LCD SEG0-63 OSC0 ML63187B OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 V DDl Crystal oscillation is selected as low-speed oscillation by mask option. Ceramic oscillation is selected as high-speed oscillation by software. Ports, external memory, and IC share their power supply. C v is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C l, C 12, C G, C L0, and C L1 are for reference only. C L0 30 pf C L1 30 pf Ceramic Resonator (Example: 1 MHz) V DD MDB V SS Note: V DDI is the power supply pin for the input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup 32/36

33 APPLICATION CIRCUITS (ML63189B) Crystal khz XT0 COM1-16 LCD SEG0-63 OSC0 Crystal oscillation is selected as low-speed oscillation by mask option. RC oscillation is selected as high-speed oscillation by software. Ports are powered from external memory power source. C v is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C l, C b12, C 12, C h, and C G, are for reference only. C G 5 to 25 pf XT1 V DDH V DD 1.0 µf CB1 C b µf C CB2 l V DDL C e C d C c C b C a C 12 V DD5 V DD4 V DD3 V DD2 V DD1 C1 Buzzer Push SW C2 RESET TST1 TST2 MD C v 1.5 V C h 1.0 µf ML63189B OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 V DDI R OSH V DD MDB V SS Note: V DDI is the power supply pin for the input and input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup 33/36

34 C G V DD 5 to 25 pf 5.0 V C v C l C e C d C c C b C a C 12 Buzzer Crystal khz Open Push SW XT0 XT1 V DDH V DD CB1 CB2 V DDL V DD5 V DD4 V DD3 V DD2 V DD1 C1 C2 RESET TST1 TST2 MD COM1-16 LCD ML63189B SEG0-63 OSC0 OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 V DDl Crystal oscillation is selected as low-speed oscillation by mask option. Ceramic oscillation is selected as high-speed oscillation by software. Ports, external memory, and IC share their power supply. C v is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C l, C 12, C G, C L0, and C L1 are for reference only. C L0 30 pf C L1 30 pf Ceramic Resonator (Example: 1 MHz) V DD MDB V SS Note: V DDI is the power supply pin for the input and input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup 34/36

35 PACKAGE DIMENSIONS (Unit: mm) QFP128-P K Mirror finish 5 Rev. Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5µm) Package weight (g) 1.19 TYP. No./Last Revised 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/36

36 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 36/36