A Blended SPS-ESPS Control DAB-IBDC Converter for a Standalone Solar Power System

Transcription

1 energies Article A Blended SPS-ESPS Control Converter for Stlone Solr Power System P. Sthishkumr 1, Himnshu 1, Shengxu Pio 1, Muhmmd Adil Khn 1, Do-Hyun Kim 1, Min-Soo Kim 1, Dong-Keun Jeong 2, Cheewoo Lee 3 Hee-Je Kim 1, * 1 School Electricl Engineering, Pusn Ntionl University, Busehk-ro 63 beon-gil 2, Busn 46241, Kore; sthishnno2013@gmil.com (P.S.); himnshuhimnshu820@gmil.com (H.); pioshengxu88@hotmil.com (S.P.); engrdilee@gmil.com (M.A.K.); kdh8486@nver.com (D.-H.K.); rllstn5122@nver.com (M.-S.K.) 2 Power Conversion Control Reserch Centre, HVDC Reserch Division, KERI, Chngwon 51435, Kore; keunygjjng@nte.com 3 School Electricl Engineering, Pusn Ntionl University, Busn 46241, Kore; cwlee1014@pusn.c.kr * Correspondence: heeje@pusn.c.kr; Tel.: Received: 9 August 2017; Accepted: 12 September 2017; Published: 18 September 2017 Abstrct: In sustinble energy pplictions, stlone solr systems re mostly preferred for self-ed energy zones. In ll stlone renewble systems, btteries re still preferred s common energy srge device. On or h, btteries re not pplicble for high pek dem pplictions becuse ir low density. A supercpcir is preferble high- density energy srge device for high pek pplictions. A 2 kw, 50 khz digitl dul ctive bridge isolted bi-directionl dc-dc converter () ws developed for interfcing supercpcir bnk in stlone solr system. This pper proposes blended SPS-ESPS digitl lgorithm for converter insted using trditionl single-phse shift (SPS) lgorithm, which is commonly used for lrge input output voltge vrying pplictions. This proposed blended SPS-ESPS lgorithm chieved high conversion efficiency during lrge input output voltge vrition, over trditionl phse shift lgorithm by reducing bck- flow stress in circuit. This system lso chieved mximum point for solr modules enhnced rpid chrging-dischrging for supercpcir bnk. Both SPS blended SPS-ESPS lgorithms were verified experimentlly using 2 kw pology implemented with stlone system tht combintion 2000 W input solr module 158 Wh supercpcir bnk. Keywords: dul ctive bridge; isolted bi-directionl dc-dc converter; ; blended SPS-ESPS; high density energy srge system; stlone solr system 1. Introduction Over lst decde, fossil fuel technology hs become less ttrctive due depletion reserves on Erth. Renewble energy sources re believed be n lterntive energy source replce fossil fuels. Among renewble energy systems, st-lone phovoltic systems re commonly preferred in remote res. A typicl st-lone system incorportes phovoltic pnel, mximum point trcker (MPPT), energy srge system, chrging ler [1]. A phovoltic system is not n idel dc source for chrging energy srge systems grdully becuse it does not stisfy desirble requirements srge devices. output such system is dependent on frequent chngeble wer conditions, which re lrgely unpredictble. refore, phovoltic system output is unrelible optiml chrge dischrge cycle cnnot be gurnteed [2]. With led cid btteries, which re most prefer common energy srge device in stlone Energies 2017, 10, 1431; doi: /en

2 Energies 2017, 10, renewble energy systems, this unrelible chrging results in low bttery stte chrge, which leds sulphting strtifiction tht both shorten bttery life cycle [3]. To void this, MPPT chrge ler re used s n intermedite circuit in renewble solr energy system between solr source energy srge device. Recently, reserchers hve focused on supercpcirs s n energy srge device insted using btteries. Supercpcirs hve severl dvntges over btteries, such s bility hle high pek, high density, instntneous turn on bility, rpid chrge-dischrge cpbility. se unique properties supercpcir mke it idel energy srge device in certin lod pplictions where high pek dem is necessry. For exmple, in mor strting pplictions, strting requirement cn be 6 10 times higher thn norml operting mor. Electric vehicles re likely employ electriclly ed cturs for high- trnsient lods. A supercpcir-bsed energy srge system hs been proposed meet pek dems electric vehicle lods bsorb regenerted [4,5]. On or h, mjor limittion supercpcirs is ir lower energy density, so y cnnot sre lrge mounts energy like bttery. For exmple, if supercpcir is be used sre sme energy s led cid bttery, with present technology, supercpcir must be ten times lrger thn corresponding bttery. Although lrge size is considered mjor disdvntge supercpcir, it cn still be pplied in n energy srge system becuse its higher density. Mny studies mteril side hve ttempted improve supercpcir energy density wrds mke it n efficient energy srge device [6]. In future, energy density supercpcirs will hopefully be much improved compred conventionl btteries. Nowdys, led cid btteries with solr source re commonly used for developing self-ed energy zones commonly known s no- grid zones. Although led cid btteries re pproprite for self-ed energy zones, however while hling high pek pplinces such s ir-conditioners, mixers, grinders, etc. stress on btteries is incresed enormously which leds btteries be bdly dmged. Mny reserchers hve proposed supercpcirs or combintions supercpcirs btteries s energy srge devices in st-lone systems for developing better self-ed energy zone [5]. Mny dc-dc converter pology pproches re being proposed in stlone renewble energy srge systems for chieving mximum, high conversion efficiency secure fst chrging-dischrging [7 10]. In design high dc-dc converters, min trde-fs re between efficiency converter. Since 1970s, semiconducr technology hs been developed, resulting in significnt increse in density electronic converters. With more progressive semiconducr devices, switch mode electronic converters with higher switching frequency hve been developed. refore, volumes converter circuits cn be decresed. Power semiconducrs integrted circuits hve been developed economiclly produce dc-dc converters. Bsed on reviews, mong ll dc-dc converters for interfcing renewble sources high- density-energy srge devices, becuse its unique chrcteristics Dul Active Bridge-Isolted Bidirectionl DC-DC Converter () ws proposed by uthors in erly 1990s [11]. On or h, becuse performnce limittions devices, losses were high efficiency ws uncceptble. In recent yers, dvnces in new devices mgnetic mterils hve mde simple low loss converter circuit mong ll or converters [12]. For conversion, pology is populr mong reserchers becuse its high performnce, high efficiency, glvnic isoltion, bility for hling high density, both side flow bility, inherent st switching property. se fetures mke typicl circuit for high density pplictions [13]. Severl ppers hve been published performnce comprehensive nlyses DAB converters hve been reported. Design considertions DAB converter high frequency DAB trnsformer were discussed briefly under ssumption future trends [14]. Nygi et l. proposed new model for stedy

3 Energies 2017, 10, Energies 2017, 10, stte nlysis DAB converter circuit tht produces equtions for rms verge device s, device s, rms pek inducr s. se equtions re useful for predicting rms pek inducr s. se equtions re useful for predicting losses tht occur in losses tht occur in device pssive components [15]. A previous study [16] optimized device pssive components [15]. A previous study [16] optimized design dul ctive design dul ctive bridge converter permitting flexible interfcing energy srge devices bridge converter permitting flexible interfcing energy srge devices chieve uninterrupted chieve uninterrupted supply in militry pplictions. DAB performnce for next supply in militry pplictions. DAB performnce for next genertion conversion genertion conversion systems using ultr-cpcir-bsed technologies hs been vlidted systems using ultr-cpcir-bsed technologies hs been vlidted [17]. performnce n [17]. performnce n ultr-cpcir-bsed DAB converter dynmic ws modelled ultr-cpcir-bsed DAB converter dynmic ws modelled nlyzed [18]. According previous nlyzed [18]. According previous reserch bsed on digitl lgorithm, ESPS reserch bsed on digitl lgorithm, ESPS n isolted bi-directionl dc-dc converter n isolted bi-directionl dc-dc converter is improving system efficiency circuit for is improving system efficiency circuit for distribution between energy source distribution between energy source energy srge system in micro grids over wide input energy srge system in micro grids over wide input voltge output rnge [19]. voltge output rnge [19]. stress bckflow n isolted converter stress bckflow n isolted converter circuit ws nlyzed using ESPS circuit ws nlyzed using ESPS it ws verified tht ESPS chieves greter efficiency with it ws verified tht ESPS chieves greter efficiency with n inner phse limittion over SPS n inner phse limittion over SPS under microgrid pplictions [20]. under microgrid pplictions [20]. This pper proposes modified digitl converter be deployed in This pper proposes modified digitl converter be deployed in stlone solr system coupled with high- density energy srge device, s shown stlone solr system coupled with high- density energy srge device, s shown in 1. proposed lgorithm cn operte solr source t its mximum point in 1. proposed lgorithm cn operte solr source t its mximum point (MPPT), converting with mximum conversion efficiency enhncing rpid (MPPT), converting with mximum conversion efficiency enhncing rpid chrging-dischrging for high density energy srge devices. In digitl lgorithm, chrging-dischrging for high density energy srge devices. In digitl lgorithm, blended SPS-ESPS lgorithm opertes converter with mximum conversion blended SPS-ESPS lgorithm opertes converter with mximum conversion efficiency by reducing bck-flow in converter circuit. In such lrge voltge vrying efficiency by reducing bck-flow in converter circuit. In such lrge voltge vrying pplictions (k > 1) like renewble energy source, bck-flow converter is pplictions (k 1) like renewble energy source, bck-flow converter lrge, which leds n increse in stress in circuit. refore, overll circuit is lrge, which leds n increse in stress in circuit. refore, overll circuit performnce will be ffected conversion efficiency will be reduced. proposed performnce will be ffected conversion efficiency will be reduced. proposed blended SPS-ESPS digitl lgorithm continuously monirs bck- flow in circuit blended SPS-ESPS digitl lgorithm continuously monirs bck- flow in circuit reduces it s much s possible by djusting inner phse shift primry bridge. In this reduces it s much s possible by djusting inner phse shift primry bridge. In this lborry, 2 kw pology with MOSFET switching bridges ws developed. overll lborry, 2 kw pology with MOSFET switching bridges ws developed. overll lgorithm ws verified experimentlly using this pology in 2000 W stlone solr lgorithm ws verified experimentlly using this pology in 2000 W stlone solr system. To nlyses modified lgorithm, experiment ws lso conducted using system. To nlyses modified lgorithm, experiment ws lso conducted using trditionl single-phse shift (SPS) lgorithm. results re discussed bsed on experimentl trditionl single-phse shift (SPS) lgorithm. results re discussed bsed on experimentl results it ws concluded tht proposed blended SPS-ESPS digitl results it ws concluded tht proposed blended SPS-ESPS digitl converter converter gins more efficiency over trditionl phse shift DAB converters. results showed tht gins more efficiency over trditionl phse shift DAB converters. results showed tht blended blended SPS-ESPS digitl is more suitble for stlone renewble SPS-ESPS digitl is more suitble for stlone renewble system in high system in high pek dem pplictions, such s electric vehicles, mors, etc. pek dem pplictions, such s electric vehicles, mors, etc. DIGITAL CONTROLLED DAB- IBDC SUPER CAPACITOR BANK SOLAR LOAD 1. Block digrm stlone phovoltic system. 1. Block digrm stlone phovoltic system.

4 Energies 2017, 10, Energies 2017, 10, Converter Circuit 2 presents schemtic digrm digitl dul ctive bridge isolted bidirectionl dc-dc converter circuits. se circuits re simply structured with two full bridges isolted by high frequency high trnsformer. Both side flow exists in circuit is led by DSP ler (TMS320F28335, Texs Instruments, Dlls, TX, USA). schemtic digrm explntion, principle opertion, stedy stte model circuit re explined below. 2. Schemtic digrm Digitl Controlled Dul Active Bridge-Isolted Bidirectionl DC-DC Converter (). A Dul Active Bridge converter contins n n isolted isolted trnsformer with with lekge lekge Inductnce, Inductnce, Lleq. L leq. required required inductnce inductnce for for circuit circuit is provided is provided prtly prtly or or entirelyby by trnsformer lekge inductnce. If If needed, n n dditionl dditionl coupling coupling inducr inducr my bemy connected be connected in series with in series trnsformer with trnsformer lekge inducr lekge inducr boost overll boost inductnce overll inductnce converter circuit converter bsedcircuit on bsed conversion conversion requirements. requirements. isolted trnsformer isolted trnsformer isoltes two isoltes full-bridge two circuits, full-bridge in tht circuits, primry in tht side primry full bridge side isfull connected bridge is connected high voltge high DC source voltge clled DC source high clled voltge bridge high voltge (V b ) bridge nor (Vb) full bridge nor on full bridge secondry side secondry is connected side is connected low voltge energy low voltge srge energy system srge clledsystem low clled voltge bridge low voltge (V cd ). Inbridge forwrd (Vcd). mode, In forwrd mode, flows from source flows from supercpcir source until supercpcir until is chrged supercpcir fully. is lod chrged is connected fully. lod primry is connected side circuit primry becuse side it cncircuit be ed becuse upit bycn be energy ed srge up system by in energy bckwrd srge system mode in opertion. bckwrd Bothmode side full opertion. bridges consist Both side four full 47N60C3 bridges MOSFETs consist (Infineon four 47N60C3 Technologies, MOSFETs Hong (Infineon Kong, Technologies, Chin), s shown Hong in Kong, Chin), 2, re s led shown in by high 2, frequency re led squre wve by voltge high frequency given by squre DSPwve followed voltge by given MOSFET by driver. DSP followed Both sideby bridges, MOSFET two squre driver. wves Both side cnbridges, be suitbly two squre phse shifted wves cn withbe respect suitbly phse ech or shifted with respect ech flowor direction. In forwrd mode, flow direction. phse In forwrd V cd squre mode, wve is phse shifted by Vcd Vsqure wve is shifted by Vb b wve. In contrst, in bckwrd squre mode, wve. In contrst, phse in bckwrd V b squre mode, wve is phse shifted by Vb phse squre wve V is shifted by phse Vcd cd squre wve. refore, bidirectionl squre wve. flow refore, is enbled bidirectionl in DAB flow is enbled in DAB converter. flow occurs becuse voltge difference cross inducr due phse shift between se two bridges squre wve voltges.

5 Energies 2017, 10, converter. Energies 2017, 10, 1431 flow occurs becuse voltge difference cross inducr due 5 19 phse shift between se two bridges squre wve voltges. In In 3, 3, L is is sum sum trnsformer trnsformer lekge lekge inductnce, inductnce, L Lleq, leq, coupling coupling uxiliry uxiliry inductnce inductnce L L1. Vb 1. V Vcd b V re cd re equivlent equivlent AC AC output output voltges voltges primry primry secondry secondry side, side, respectively. respectively. VL V L IL I re L re voltge voltge inducr, inducr, L. L. -flow -flow direction direction mgnitude mgnitude cn cn be be led led simply simply by by djusting djusting phse phse shift shift between between Vb V b V Vcd. cd. Although Although vrious vrious digitl digitl lgorithms lgorithms were were proposed, proposed, trditionl trditionl single-phse single-phse shift shift (SPS) (SPS) lgorithm lgorithm is is still still preferred preferred by by mny mny reserchers reserchers for for its its unique unique chrcteristics chrcteristics such such s s high high hling hling bility bility hling hling lrge lrge input input output output voltge voltge vrition vrition [2]. [2]. Extended Extended single-phse single-phse shift (ESPS) is preferred by reserchers increse conversion efficiency by reducing bck flow stress in circuit. Regrding incresing conversion efficiency, compred shift (ESPS) is preferred by reserchers increse conversion efficiency by reducing bck- flow stress in circuit. Regrding incresing conversion efficiency, compred or digitl lgorithms it cn be implemented very esily by dding n inner phse shift t or digitl lgorithms it cn be implemented very esily by dding n inner phse shift primry side bridge. Both lgorithm forwrd mode wveform shown in t primry side bridge. Both lgorithm forwrd mode wveform shown in 4 were ssessed by wveform stedy stte nlysis. 4 were ssessed by wveform stedy stte nlysis Equivlent circuit phse-shift.. Stedy Stte Anlysis 4 shows min wveforms in SPS ESPS, where TThs is hlf switching period, d is phse-shift rtio between primry secondry voltges isoltion high frequency trnsformer, where 0 0 dd 1. In 4 4 VVb VVcd re both squre wve voltges interction between se two voltges occurred through inducr circuit. refore, primry voltge is is lwys in miss-phse with primry becuse it psses through inducr. verge verge s s lekge lekge inducr inducr re derived re bsed derived on bsed wveform on Iwveform L. difference IL. indifference voltge between in voltge V b between V cd ppers Vb cross Vcd ppers inducr, cross L, inducr,, L, Iinducr L, t switching, IL, instnts, t switching t 1 t 2, instnts, respectively: t1 t2, respectively: I p = T s 4 [ + (2 (1) 4L [nv in + V 0 (2d 1)] (1) L 1 = T = s 4L [nv 4 [ in(2d 1) + V 0 ] (2) (2 1) + ] (2) wveform is periodic over hlf cycle. Thus, dividing re by durtion T s /2, verge wveform output is periodic DAB over converter: hlf cycle. Thus, dividing re by durtion Ts/2, verge output DAB converter: I 0 = nv ( int s = d d 2) (3) 2L 2 ( ) (3) Normlly verge output depends on nv int s Normlly verge output depends on ( : I 0 = d d 2) (4) = ( ) (4) From Eqution (4), by substituting full rnge 0 1 phse shift d, it cn be observed tht mximum trnsfer occurs for duty rtio L :

6 Energies 2017, 10, From Eqution (4), by substituting full rnge 0 1 phse shift d, it cn be observed tht mximum trnsfer occurs for duty rtio 0.5. Energies 2017, 10, Key operting wveforms during during forwrd forwrd (buck) (buck) mode. () mode. Trditionl () Trditionl single- single-phse shift shift (SPS), (SPS); (b) extended (b) extended phse phse shift shift (ESPS). (ESPS). As shown in 4, IL is opposite phse from Vb for n intervl t = t0 t0 t = t2 t2 is As portion shown in 4, delivered I L is opposite Vout side phse in from single V b switching for n intervl period. t = t or 0 t 0 portion t = t 2 = t 2 is portion t0 t1 t = t2 t3, is sent delivered bck primry V out voltge side insource, single Vin. switching This is defined period. s bckflow or portion t = for t 0 t given 1 trnsmission t = t 2 t 3, sent. bck tl trnsmission primry voltge source, bckflow V in. This is defined cn be derived s bckflow s follows: for given trnsmission. tl trnsmission bckflow cn be derived s follows: P= P = nv inv out T ( s ( d d 2) ) (5) (5) 2L 2 P = [ (2 1)] b f = nv inv out T s [k + (2d 1)] 2 (6) 16L(k + 1) (6) 16 ( 1) where, n = Trnsformer turns rtio, k = Voltge trnsfer rtio, d phse shift, V in = input voltge, where, n = Trnsformer turns rtio, k = Voltge trnsfer rtio, d phse shift, Vin = input voltge, Vout V out = chrging voltge, L = inductnce converter, T s = Switching time. = chrging voltge, L = inductnce converter, Ts With incresing bckflow, forwrd = Switching lso increses time. compenste for loss With incresing bckflow, forwrd lso increses compenste for loss cused by bckflow. circulting stress re n incresed, which result cused by bckflow. circulting stress re n incresed, which result in gret loss in devices mgnetic components low efficiency converter: in gret loss in devices mgnetic components low efficiency converter: I mx = nv 2T s (2d 1 + k) (7) 4L (2 ) (7) 4 From Equtions (1) (7), mximum trnsfer occurs t duty rtio 0.5. Even sme trnsfer is chieved for duty 0.5 1, which is sme s 0 0.5, in tht bckflow stress will be low in region where duty is compred duty region.

7 Energies 2017, 10, From Equtions (1) (7), mximum trnsfer occurs t duty rtio 0.5. Even sme trnsfer is chieved for duty 0.5 1, which is sme s 0 0.5, in tht bckflow stress will be low in region where duty is compred duty region. To decrese bckflow, V b should not be confined squre wve with 50% duty cycle. In figure, S 1 S 4 hve phse shift β, which reduces V b squre wve duty cycle. trnsformer primry voltge will emerge s three levels insted two levels in SPS. This lters behvior I L, s shown in figure. inducr (I L ) chnges in three instnts time t 2, t 3, t 4, which re denoted s I L1, I P, I L2, respectively: I L2 = T s 4L [nv in(1 β) + V 0 (2d 1)] (8) I L1 = T s 4L [nv in(2d 1 + β) + V 0 ] (9) I p = T s 4L [nv in(1 β) + V 0 (2d 1 + 2β)] (10) where, β = inner phse shift, d outer phse shift, T s = Switching time. If see wveform, it s periodic over hlf cycle, dividing re by durtion T s /2, gives verge output DAB converter is: I 0 = nv int s 2L [d d2 dss + β 2 β2 2 ] (11) Normlised verge output bsed on vlues nv int s 2L gives: I 0 = d d 2 dβ + β 2 β 2 (12) bckflow ppernce time re divided in two intervls t = t 0 t 1, t = t 1 t 1 t = t 3 t 4, t = t 4 t 4. bckflow is zero s trnsformer primry voltge reches zero for first intervls. Thus, overll bckflow decresed for given trnsmission : Bckflow : P = 1 Ths T hs 0 V h1 i L (t)dt = nt sv 1 V 2 (d(1 d) + 1 β(1 β 2d) (13) 2L 2 P bf = 1 t 1 V T h1 i L (t) dt = nt sv 1 V 2 [k(1 β) + (2d 1)] 2 hs t 1 16L(k + 1) (14) where, k = voltge trnsfer rtio. Current stress under ESPS : where i L (t 1 ) < 0, from eqution, we hve I mx = nt sv 2 (k(1 β) + (2β + 2d 1) (15) 4L k > 1 2d 1 β (16) When k (1 2d)/(1 β), bck- flow is zero. In figure, β is phse shift rtio between driving signls S1 & S4, S2 & S3 in primry bridge. β is defined s inner phse shift rtio, where 0 β 1. d is phse shift rtio between primry secondry voltges isoltion trnsformer. d is ten known s outer

8 Energies 2017, 10, 1431 Energies 2017, 10, stress, exp regulting rnge trnsmission, enhnce regulting Energies 2017, 10, flexibility. phse shift rtio, where 0 d 1 0 β + d 1. Compred SPS, ESPS hve not only nstress, outer exp phse shift but lso n inner phse shift, rtio, which will decrese rtio, regulting rnge trnsmission enhnce regulting 3. Experiments stress, exp regulting rnge trnsmission, enhnce regulting flexibility. flexibility. 5 presents developed 2 kw converter circuit experimentl setup. In 3. Experiments 3. Experiments pology, both side ctive bridges hve been designed with 47N60C3 MOSFET. equivlent gte cpcitnce is expressed by gte source gte drin cpcirs. setup. drin 5 5presents kw converter circuit experimentl presents developed developed 22 kw converter circuit experimentl setup. In source resistnce is 0.07both Ω, which is considered been bestdesigned vlue mong or MOSFET switches. pology, side bridges with ll 47N60C3 MOSFET. In pology, both sidective ctive bridgeshve hve been designed with 47N60C3 MOSFET. equivlent gte cpcitnce expressed by gte source gte source cpcirs. According dtsheet, drin source by voltge is nerly 650 V gte drin drin is 47 A,drin pulsed equivlent gte cpcitnce isisexpressed gte drin cpcirs. drin source resistnce is 0.07 Ω, which is considered best vlue mong ll or MOSFET switches. drin is 141 A. To trigger MOSFET switches t high frequency (f > 10 khz), pulse width source resistnce is 0.07 Ω, which is considered best vlue mong ll or MOSFET switches. According dtsheet, drin source voltge isnerly nerly A, pulsed modultion signls (±7 drin ±30source V, 3 ma) needis be pplied gte-source terminl. According (PWM) dtsheet, voltge 650VVcross drin drin isis A, pulsed drin 141 trigger MOSFET MOSFETswitches switches t t high pulse width drin is is 141 A.A.ToTotrigger high frequency frequency(f(f>>1010khz), khz), pulse width modultion (PWM) signls (±7 ±30 V, 3 ma) need be pplied cross gte-source terminl. modultion (PWM) signls (±7 ±30 V, 3 ma) need be pplied cross gte-source terminl. 5. Developed converter experimentl setup. experimentl experimentlsetup. setup. 5.5.Developed Developed converter converter pplied PWM signls re generted by digitl signl processor (TMS320F28335) bsed on pplied PWMsignls regenerted generted by digitl signl signl processor (TMS320F28335) onon pplied PWM digitl processor (TMS320F28335) lgorithm. Assignls sere PWM signlsby from DSP do not hve sufficient bsed bsed operte lgorithm.as Asse se PWM PWM signls signls from DSP do not hve sufficient operte lgorithm. from DSP do not hve sufficient operte switches, MOSFET driving circuit ws designed used interfce DSP MOSFET switches,mosfet MOSFET driving circuit ws designed used interfce DSP MOSFET switches, circuit wsoutput designed used interfce DSP MOSFET switches. switches. driverdriving circuit input wveform signl re shown in 6. designed switches. driver circuit input output wveform signl re shown in 6. designed driverdriver circuitconverts input wveform shown in designed MOSFET MOSFET output low 0 5 Vsignl PWMre signl 3 12 V 6. high PWM signls, MOSFET driver converts low 0 5signl V PWM signl 12 3Vhigh 12 V high PWM signls, driver converts low 0 5 V PWM 3 PWM signls, which which cn turn switches on f. which cn turn switches on f. cn turn switches on f. 6.6.Input Input output output signl signl wveform wveform circuit. MOSFET MOSFETdriver drivercircuit. circuit.

9 Energies 2017, 10, Energies 2017, 10, previous conversion system (PCS) is employed minly with line frequency (LF) trnsformer previous chieve isoltion conversion voltge system mtching. (PCS) is employed Bsiclly, minly LFwith trnsformer line frequency size is extremely (LF) lrge, trnsformer which hinders chieve design isoltion simple voltge PCS. mtching. In Bsiclly, LF trnsformer, LF trnsformer -voltge size is extremely disrtions losses lrge, which re high hinders due core design sturtion. simple Overll, PCS. In in previous LF trnsformer, PCSs, -voltge LF trnsformer disrtions reduces conversion losses re high efficiency due core sturtion. density. Overll, With in previous im PCSs, incresing LF trnsformer efficiency reduces density conversion converter, efficiency high frequency density. conversion With im system incresing hs recently efficiency been proposed. When switching density frequency converter, is high bove frequency 20 khz, PCSs conversion noise cn system be hs reduced recently gretly been proposed. sizes When switching frequency is bove 20 khz, PCSs noise cn be reduced gretly sizes mgnetic mterils, such s trnsformer inducr, re lso reduced. This mkes pth design mgnetic mterils, such s trnsformer inducr, re lso reduced. This mkes pth design simple lossless conversion system. As 50 khz is preferred, simple high simple lossless conversion system. As 50 khz is preferred, simple high high high frequency frequency trnsformer trnsformer ws ws designed designed using using ferrite ferrite core, core, s s shown shown in in 7, with 7, with trnsform trnsform turn turn rtio rtio (n) (n) 3:4 3:4 lekge lekge inductnce 5.26 μh. µh. () (b) (c) (d) 7. converter sub circuits mgnetic components. () MOSFET driving circuit; 7. converter sub circuits mgnetic components. () MOSFET driving circuit; (b) Trnsformer; (c) Inducr; (d) Digitl ler. (b) Trnsformer; (c) Inducr; (d) Digitl ler. According design, required inductnce is 9.98 μh, which cn be given by According trnsformer lekge inductnce, design, eir lone required or combined inductnce with n isexternl 9.98 µh, coupling whichinducr. cn be given As by trnsformer per design, lekge rech inductnce, required eir inductnce lone or combined circuit, t with trnsformer externl secondry coupling side, inducr. n As per dditionl design, inducr rech with vlue required 4.72 inductnce μh is connected in circuit, series. t dditionl trnsformer inducr secondry is clled side, coupled inducr, overll inductnce is clled uxiliry inductnce circuit. Tble n dditionl inducr with vlue 4.72 µh is connected in series. dditionl inducr is clled 1 lists developed 2 kw converter specifictions. input source DAB converter coupled inducr, overll inductnce is clled uxiliry inductnce circuit. Tble 1 ws 220 V renewble solr energy DC source, which ws obtined from six 38 V, 340 W solr pnels lists developed 2 kw converter specifictions. input source DAB converter connected in series. output ws connected supercpcir bnk, which were built with ws three 220 V48 renewble V, 165 F, solr energy 53 Wh DC Mxwell source, supercpcirs which ws obtined connected fromin sixprllel. 38 V, 340 W solr overll pnels connected in series. output ws connected supercpcir bnk, which were built with three 48 V, 165 F, 53 Wh Mxwell supercpcirs connected in prllel. overll supercpcir bnk specifiction ws 48 V, 495 F, 159 Wh. proposed converter ws led

10 Energies 2017, 10, by digitl bord which designed using DSP (TMS320F28335) IC long with mny sub circuits, such s short circuit protection, PWM protection, st strt, voltge sensor sensor which shown in 7d. Tble 1. converter design specifiction. Prmeter Rting Input Voltge V Power 2000 W Output Voltge 48 V Trnsformer turns rtio 3:4 Switching frequency 50 khz Secondry lekge inductnce 5.26 µh Auxiliry inductnce 4.72 µh Input cpcir 1200 µf Output cpcir 1800 µf Digitl Control System A closed loop ler is required in converters for regulting output voltge/ lso it is needed compenste source/lod disturbnce. closed loop ler is essentilly used minimize or eliminte error in n output. proposed digitl lgorithm s flow chrt loop for converter presents in s 8 9. four vribles clled output voltge (V out ), input voltge (V in ), input (I in ), output (I out ) converter re given DSP s processing vribles through voltge sensors. LV25-P (LEM Components, Genev, Switzerl) LA25-P (LEM Components, Genev, Switzerl) were used s voltge sensors. se sensors sense I/O voltges I/O s converter sends corresponds low voltge signl DSP. DSP ler opertes MOSFET switches in higher switching frequency. It genertes high frequency-50% dutycycle PWM signls for triggering MOSFET switches which locted t both side bridges. Along with this, DSP genertes inner outer phse ngle bsed on proposed lgorithm, which s wrds chieving sfe chrging, mximum point, high efficiency conversion. In DSP, proportionl integrl (PI) ler hs been used for chieving zero stedy stte error in n output by finding proper phse ngle: Digitl PI ler is given by: PI ler = K p e(t) + 1 t e(τ)dτ (17) K i PI_out = Pre_PI_out + Err (K p + 0.5*K i *T s ) + Pre_Err (0.5* K i T s K p ) (18) where Err = Ref Vrible, Pre_Err = previous Err vlue, Pre_PI_out = Previous PI_out vlue, K p Proportionl ler gin K i integrl ler gin. proposed blended SPS-ESPS digitl lgorithm initilly performs process strted with SPS lgorithm. ler genertes n error signl bsed on reference output voltge. voltge Proportionl Integrl (PI) ler process tht error signl finds vlue for outer phse shift (d). Thus, while string, converter inevitbly sets phse shift between two bridges squre wves V b V cd using SPS lgorithm. This helps in chieving sfe chrging (Eqution (3)) for supercpcirs by ling inducr (I L ). Menwhile, MPPT lgorithm runs prllelly continuously monirs input. At every cycle, it frequently vries reference vlue (I ref ), subsequently monirs correspond chnges in n input. In six ten DSP timing cycles, lgorithm finds better reference vlue where mximum input cn be obtined. error signl 0

11 Energies 2017, 10, Energies 2017, 10, finds better reference vlue where mximum input cn be obtined. error signl is generted by compring this reference vlue with supercpcir chrging. Current PI ler processed tht error signl generted vlue which modifies phse shift d gin. MPPT lgorithm routinely repeting sme process prllel with SPS lgorithm finding reference vlue wrds continuously chieving mximum point t every time instnts. Thus, MPPT lgorithm works in prllel with SPS lgorithm chieve mximum point trcking for solr source. 8. Blended SPS-ESPS digitl lgorithm flow chrt.

12 Energies 2017, 10, Energies 2017, 10, Blended SPS-ESPS digitl lgorithm loop. Lter ESPS begins nlyse bck- flow circuit set inner phse Lter ESPS begins nlyse bck- flow circuit set inner phse shift (β) for primry bridge chieve low bck flow in circuit (Equtions (14) (15)). shift (β) for primry bridge chieve low bck flow in circuit (Equtions (14) (15)). ESPS region chieves mximum possible conversion efficiency by reducing bck-flow ESPS region chieves mximum possible conversion efficiency by reducing bck-flow. bck-flow circuit depends voltge conversion rtio k (k = Vin/n Vout). For. bck-flow circuit depends voltge conversion rtio k (k = V lrge input output voltge vritions, k will be greter thn one. According [21], comprison in /n V out ). For lrge input output voltge vritions, k will be greter thn one. According [21], comprison ESPS with SPS lgorithm showed tht SPS DAB converter bck flow is ESPS with SPS lgorithm showed tht SPS DAB converter bck flow is low for prticulr phse shift region, i.e., for 2. At rest tht region, ESPS low for prticulr phse shift region, i.e., for k > 2. At rest tht region, ESPS lgorithm chieves higher efficiency thn SPS by chieving low bck flow. lgorithm chieves higher efficiency thn SPS by chieving low bck flow. According mentioned design, k is: According mentioned design, k is: = = 200~222 k = V in = 48 6 nv out where k = Voltge trnsfer rtio. where k = Voltge trnsfer rtio. From Equtions (6) (15), it is noted tht bck-flow (Pbf) is directly proportionl From Equtions (6) (15), it is noted tht bck-flow (P voltge trnsfer rtio k, so bck-flow for this bf ) is directly proportionl design lso will be mximum voltge s it trnsfer hs rtio mximum k, so k vlue. bck-flow refore, increse for this conversion design lso efficiency will be in mximum such lrge s input it hs output mximum voltge k vlue. vrition, refore, this pper proposed increse combintion conversion SPS efficiency ESPS in such lgorithm. lrge input This works output in voltge such vrition, wy tht for this prticulr pper proposed outer phse combintion shift d region, SPS it will ESPS follow SPS lgorithm. lgorithm This works in such reminder wy tht for or prticulr phse shift outer d region phseit shift will d obey region, itesps will follow lgorithm. SPS Thus, proposed lgorithm lgorithm reminder opertes in or both phse SPS shift ESPS d region mode it will for obey chieving ESPS possible lgorithm. mximum Thus, conversion proposed efficiency lgorithm in lrge opertes voltge conversion in both SPS rtio. When ESPS mode conversion for chieving is strted, possible proposed mximum lgorithm conversion initilly efficiency opertes in converter lrge voltge with conversion st strt rtio. lgorithm When conversion reduce inrushing is strted, proposed overshoot lgorithm voltge in initilly circuit. opertes Next SPS converter with MPPT st strt lgorithm lgorithm re strted. reduce Prllel inrushing working SPS overshoot MPPT voltge lgorithm in circuit. helps Next in SPS enhncing sfety MPPT chrging lgorithm process refor strted. supercpcir Prllel working bnk while SPS chieving MPPT solr lgorithm mximum helps in point. enhncing After tht sfety ESPS chrging lgorithm process is initited for supercpcir strts nlyze bnk while bck-flow chieving solr in mximum circuit. Bsed on point. this nlyztion, After tht inner ESPSphse lgorithm shift is initited primry bridge strtsis djusted nlyze or mintining bck-flow t zero inwrds circuit. chieving Bsed on this mximum nlyztion, possible inner phse conversion shift efficiency. primry bridge proposed is djusted blended or mintining SPS-ESPS digitl t zero wrds chieving 2 kw mximum performnce possible ws conversion nlyzed efficiency. experimentlly proposed with blended comprison SPS-ESPS study digitl trditionl 2 kwsps digitl performnce. ws nlyzed Both

13 Energies 2017, 10, experimentlly Energies 2017, 10, with 1431 comprison study trditionl SPS digitl. Both experiment results re discussed below. proposed lgorithm chieved better conversion efficiency thn experiment trdition results re discussed lgorithm below. in lrge proposed voltge conversion lgorithm rtio chieved cusedbetter renewble conversion energy srge efficiency system. thn trdition lgorithm in lrge voltge conversion rtio cused renewble energy srge system. 4. Results Discussion 4. Results Discussion Both SPS blended SPS-ESPS converter conversion performnce Both SPS blended SPS-ESPS converter conversion discussed below re bsed on experimentl results. experiments were conducted in performnce discussed below re bsed on experimentl results. experiments were stlone renewble energy srge system with combintion 2 kw solr modules 153 Wh conducted in stlone renewble energy srge system with combintion 2 kw solr supercpcir bnk. experiments were conducted during different time stges wrds chieving modules 153 Wh supercpcir bnk. experiments were conducted during different time different input voltges by solr module. converter output wveforms re stges wrds chieving different input voltges by solr module. discussed for vrious input s 2000, 1900, W, circuit performnce is converter output wveforms re discussed for vrious input s 2000, 1900, W, nlyzed using circuit performnce experimentl is nlyzed results. using SPS experimentl results. conversion SPS wveform, chrging time, conversion efficiency wveform, re discussed chrging time, below. efficiency re discussed below. A single A single phse phse shift shift is is trditionl technology for for converter. 10 shows 10 shows tht tht SPS s SPS s conversion conversion wveforms wveforms for for different different input input s. HV (V b HV ) (Vb) LV (VLV cd ) side (Vcd) voltge, side voltge, inducr inducr,, output output chrging chrging voltge voltge re shown re shown for ech for ech input input from from 10,b. s 10,b. 9 shows9 tht shows DSPtht umticlly DSP umticlly vries vries phse shift phse (0.47 shift ( ) between 0.245) V b between VVb cd chieve Vcd chieve constnt constnt output output voltge voltge limiting limiting bsed bsed on on SPS SPS lgorithm. lgorithm. solr source solr source chieved chieved n input n input voltge voltge from from d d V, V, V, V, V, V, V, respectively V, respectively. SPS digitl SPS digitl lgorithm lgorithm chnged chnged only only outer phse outer phse shift shift inducr inducr obtin obtin constnt constnt dc output dc output voltge. voltge Experiment results SPS SPS converter converter t different t different input input () () 2000W, W; (b) (b) W, W; (c) (c) W W (d) (d) W. W. Time Time scle: scle: 5 ms/div. 5 ms/div.

14 Energies 2017, 10, Energies 2017, 10, presents super cpcir chrging wveform for SPS converter; 11 shows time time vs. vs. voltge voltge chrcteristics chrcteristics wveforms wveforms 11b shows 11b shows time vs. time vs. chrcteristics chrcteristics wveforms wveforms converter. converter. This tkes This6 tkes min 26 6 min s, 626 min s, 658 min s, 758min s, 743 min s, 43 s, 9 min 9 23 min s 23chrge s chrge 158 Wh-supercpcir 158 bnk bnk with with respective respective input input 2000, 2000, 1900, 1900, W On W. Onor or h, h, ccording ccording oreticl oreticl clcultion, clcultion, 2000, 2000, 1900, 1900, W 1400 input W input energy energy cn chrge cn chrge 158 Wh 158supercpcir Wh bnk in bnk 4 min 45 min s, 545 min s, 01 5 min s, 5 01 min s, 35 5 min s, 35 6 s, min 647 min s, respectively. 47 s, respectively. Owing Owing losses losses in incircuit SPS SPS lgorithm chieves less efficiency for given protype. efficiency converter cn be clculted from difference between oreticl experimentl vlues, which re plotted in ,b shows chieved output output conversion conversion efficiency efficiency SPS SPS converter. converter. SPS SPS pology pology chieved chieved conversion conversion efficiency efficiency 73%, 72.6%, 73%, 72.6%, 71%, 71%, 69% for69% n input for n solr input solr 2000 W, W, W, W, W, respectively W, respectively. As discussed As discussed bove, bove, efficiency efficiency converter will converter be reduced will be due reduced bckflow due bckflow in circuit. in To reduce circuit. To reduce bck-flow bck-flow in circuit, in blended circuit, SPS-ESPS blended SPS-ESPS lgorithm ws lgorithm proposed. ws Toproposed. compre To compre performnce performnce converter in both converter in lgorithm, both sme lgorithm, experiments sme wereexperiments repeted with were repeted sme operting with conditions sme operting using conditions blended SPS-ESPS using blended lgorithm SPS-ESPS experimentl lgorithm results re experimentl given below. results re given below. 13 shows blended SPS-ESPS circuit wveforms. two squre wve signls S1, S4 S4re re switching signls for for two two inner inner brnches brnches primry primry bridge. bridge. phse phse shift shift between between se se two brnches two brnches clled clled inner phse inner phse shift (β) shift s (β) s bck-flow bck-flow in circuit. in circuit. S5,7 re S5,7 resqure squre wve wve switching signls signls for for secondry bridge. phse shift between S1 S5 re clled outer phse shift rtio (d), which s flow in circuit. HV side voltge (Vb) ) LV side voltge (Vcd) ) re shown in 13, in which Vb chnges considerbly due inner phse shift. In figure compring wveform (), inner phse shift ws quite lrge for or wveforms. As solr input voltge decreses, outer phse shift increses compenste for desired output dc voltge. refore, bck flow in circuit increses subsequently conversion output circuit is decresed. 13 shows proposed lgorithm reduce bck- flow by by incresing inner inner phse phse shift. shift. Becuse Becuse dditionl phse phse shift shift voltge voltge difference cross cross inducr inducr hs hs six levels six levels chnges, it it resembles chnges chnges in inducr inducr.. () (b) Supercpcir Supercpcir chrging chrging wveform wveform by by SPS SPS converter. converter. () Shows () Shows time time vs. voltge vs. voltge chrcteristics chrcteristics wveforms wveforms (b) shows (b) shows time vs. time chrcteristics vs. chrcteristics wveforms wveforms converter. converter.

15 Energies 2017, 10, Energies 2017, 2017, 10, 10, () () (b) (b) SPS converter conversion efficiency for for different input solr. () () Shows chieved output output SPS SPS converter converter (b) shows (b) (b) shows conversion conversion efficiency efficiency SPS SPS converter. converter. 13. Cont.

16 Energies 2017, 10, Energies 2017, 10, Blended SPS-ESPS conversion wveform for different input 13. Blended SPS-ESPS conversion wveform for different input tht tht () 2000 W, (b) 1900 W, (c) 1700 W (d) 1400 W. Time scle 5 ms/div. () 2000 W; (b) 1900 W; (c) 1700 W (d) 1400 W. Time scle 5 ms/div. 14 shows AC link wveforms generted by two ctive bridges. 14,b show 14 shows LV HV AC link side device wveforms wveforms. generted From by two figure, ctive introducing bridges. n inner 14,b show phse shift LV in single HV side phse device shift reduces wveforms. switching From reverse figure, introducing or bck n flow inner. phse From shift in mesured single phse results, shift reduces blended switching SPS-ESPS reverse converter or opertes bck flow with. mximum From conversion mesured results, efficiency blended 84%. SPS-ESPS converter opertes with mximum conversion efficiency 84%. 15 presents conversion efficiency comprison plot for SPS proposed lgorithm; 15 presents () shows tht conversion conversion efficiency comprison efficiency plot (b) for shows SPS tht proposed chieved output lgorithm; respective () shows vrious tht input solr conversion s. efficiency blended (b) SPS-ESPS shows tht pology chieved chieved output respective conversion efficiency vrious input 75%, solr 79%, s. 84%, blended 81% for SPS-ESPS respective pology input chieved solr conversion 2000, 1900, efficiency %, W. Compred 79%, 84%, 81% SPS for lgorithm, respective it input increses solr 2000, conversion 1900, efficiency with W. 2 13% Compred tke 6 min SPS 14 s, 6 min lgorithm, 15 s, 6 it min increses 30 s 7 min conversion 59 s chrge efficiency 158 with Whsupercpcir 2 13% tke bnk 6 min with 14 s, 6 respective min 15 s, input 6 min 30 s 2000, 7 min 1900, 59 s 1700 chrge W. Wh-supercpcir bnk with respective input 2000, 1900, W.

17 Energies 2017, 10, Energies 2017, 10, Experimentl Experimentl results results device device wveform wveform blended blended SPS-ESPS SPS-ESPS led led DAB- converter. IBDC converter. ()Primry ()Primry bridge bridge switching switching ;, (b) Secondry (b) Secondry bridge bridge switching switching Blended SPS-ESPS Power conversion efficiency. () Input Power vs. 15. Blended SPS-ESPS Power conversion efficiency. () Input Power vs Efficiency; (b) Input Power vs. Output Power. Efficiency, (b) Input Power vs Output Power. 16 shows bckwrd mode opertion wveforms SPS () blended SPS-ESPS (b) converter. At At bckwrd mode, high high resistive lod lod (25 (25 Ω) ws Ω) ws used used t t primry primry side side converter converter circuit, circuit, s shown s in shown block in digrm block which digrm which 1, for dischrging 1, for dischrging supercpcir supercpcir bnk. In forwrd bnk. mode, In forwrd when mode, supercpcir when supercpcir ws fully chrged, ws fully ler chrged, umticlly ler switched umticlly from switched forwrd mode from forwrd bckwrd mode mode bckwrd enbled mode reverse side enbled reverse flow in side circuit. flow In in experiment, circuit. In 25 experiment, Ω, 2500 W resistive 25 Ω, 2500 lod W ws resistive connected lod t ws connected primry side t dischrge primry side 158 Wh dischrge super cpcir 158 Wh bnk. super cpcir supercpcir bnk. bnk supercpcir output voltge bnk ws output 48 V, voltge which ws converted 48 V, which ws 220 V converted dc t bckwrd 220 V mode dc t bckwrd pplied mode cross pplied lod 25 cross Ω. An pproximtely lod 25 Ω. 9 An A pproximtely ws pssed 9 A through ws pssed lod. through lod.

18 Energies 2017, 10, Energies 2017, 10, Bckwrd mode opertion wveforms () () SPS, ; (b) Blended SPS-ESPS. Time scle 10 ms/div Conclusions Conclusions blended blendedsps-esps SPS-ESPSdigitl digitl lgorithm lgorithmws wsproposed proposedover over SPS SPS lgorithm for for converter converter chieve high- high-conversion conversionefficiency, efficiency, mximum mximum point, point, enhnced enhnced fst fst chrging-dischrging in in high density energy srge device. In In lborry, using MOSFET switches, switches, 22 kw, kw, khz khz converter converter ws ws developed developed SPS SPS blended blended SPS-ESPS SPS-ESPS lgorithm lgorithm were were verified verified experimentlly. experimentlly. results results showed showed tht tht in in lrge lrge voltge voltge conversion conversion rtio rtio pplictions, pplictions, such s such stlone s stlone solr solr systems, systems, proposed proposed blended SPS-ESPS blended SPS-ESPS lgorithm lgorithm chieves high chieves conversion high conversion efficiency efficiency by reducing by reducing bck-flow bck-flow stress in stress circuit. in circuit. Acknowledgments: This reserch ws supported by Bsic Reserch Lborry through Ntionl Reserch Foundtions Kore funded by Ministry Science, ICT Future Plnning (NRF-2015R1A4A ). Author Contributions: P. Sthishkumr, Hee-Je Kim Cheewoo Lee conceptulize ide this reserch project. P. Sthishkumr designed converter, MOSFET driver units. Dong-Keun project. P. Sthishkumr designed converter, MOSFET driver units. Dong-Keun Jeong Jeong designed DSP ler bord. P. Sthishkumr Shengxu Pio developed lgorithm designed DSP progrm DSP ler with help bord. P. Sthishkumr Dong-Keun Jeong. Shengxu P. Sthishkumr, Pio developed Himnshu Muhmmd lgorithm Adil Khn DSP progrm developedwith mgnetic help component Dong-Keun for circuits Jeong. tht P. Sthishkumr, high frequency trnsformer Himnshu inducr. Muhmmd P. Sthishkumr, Adil Khn developed Do-Hyun Kim mgnetic Min-Soo component Kim mking for n experimentl circuits tht setup high frequency doing experiment. trnsformer dt ws inducr. nlyzed P. Sthishkumr, by tem Do-Hyun pper Kim ws written Min-Soo by P. Kim Sthishkumr mking n experimentl Hee-Je Kim. setup doing experiment. dt ws Conflicts nlyzed Interest: by tem uthors pper declrews no conflict written by interest. P. Sthishkumr Hee-Je Kim. Conflicts Interest: uthors declre no conflict interest. References Reference 1. Romno, R.; Sino, P.; Acone, M.; Loi, V. Combined opertion electricl lods, Air conditioning 1. Romno, Phovoltic R.; Sino, BtteryP.; Systems Acone, inm.; smrt Loi, houses. V. Combined Appl. Sci. opertion 2017, 7, 525. electricl [CrossRef] lods, Air conditioning Phovoltic Bttery Systems in smrt houses. Appl. Sci. 2017, 7, 525, doi: /pp

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