Electronics Review Flashcards

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1 November 21, 2011

2 1 Op Amps 2 Diodes 3 Silicon 4 pn Junctions 5 BJTs 6 MOSFETs

3 Open Loop Characteristics Open-Loop Op-Amp Characteristics (first-order model)

4 Closed Loop Characteristics Closed-Loop Op-Amp Amplifiers (first-order op-amp model) A 0 large, low-frequencies: ( v 0 = 1 + R ) 2 v 1 R 2 v 2 R 1 R 1 }{{}}{{} non-inverting gain inverting gain -3 db bandwidth (either input): f BW = f T 1 + R2 R 1 For finite op-amp low-frequency gain A 0, the closed loop inverting and non-inverting gains are reduced by a factor of 1 + (1 + R 2 /R 1 )/A 0.

5 Op Amp Saturation Op-Amp output saturation limits: Rated Output Voltage: Maximum output voltage range. Rated Output Current: Maximum output current. (Remember that the op-amp must supply the load current plus any current required by the feedback circuit) Slew Rate: Maximum rate of change of the output voltage. SR = dv o dt max

6 DC Nonidealitis Op-Amp DC Imperfections Offset Voltage: V OS is the maximum magnitude of a DC input voltage that is required to bring the output voltage to zero. Model as an ideal op-amp, with an additional DC source at one of the opamp input terminals. In some cases, capacitively coupling an amplifer input will significantly reduce the DC gain, so that the output is less dependent on V OS. Input Currents: The input bias current I B is the average current which must be externally supplied to each op-amp input terminal. The offset current I OS is the maximum magnitude of the difference between the currents for the two inputs. Model using an ideal op-amp, with two additional DC current sources at the input terminals to reflect the required bias currents. Use I B1 I B2 I B with I B1 I B2 I OS. By making the external resistance seen at two op-amp input terminals the same (assuming 0-volts at the op-amp output), the output can be made independent of I B (but not I OS).

7 Inverting Amplifier

8 Inverting Amplifier v o = R 2 R 1 v in

9 Noninverting Amplifier

10 Noninverting Amplifier v o = ( 1 + R ) 2 v in R 1

11 Voltage Buffer

12 Voltage Buffer v o = v in

13 Difference Amplifier

14 Difference Amplifier v o = R 2 R 1 (v 1 v 2 )

15 Integrator

16 Integrator H(s) = 1 R 1 Cs

17 Leaky Integrator

18 Leaky Integrator H(s) = R 2/R R 2 Cs

19 Summing Amplifier

20 Summing Amplifier ( Rf v o = v 1 + R f v 2 + R ) f v R 1 R 2 R 3

21 Exponential Diode Model Exponential Model: ) i D = I s (e vd/nvt 1 I s e vd/nvt I s : Reverse Saturation Current V T : Thermal Voltage ( 25.8 mv at 300K) n : Ideality Coefficient v D = nv T ln (i D /I S ) r D = nv T /I D

22 Ideal Diode Model Ideal Diode Model:

23 Voltage Drop Model Constant Voltage Drop Model:

24 Small-Signal Diode Model Small Signal Behavior: Once a DC operating point (V D, I D ) is determined, deviations from the operating point can be predicted by modeling the diode as the resistance r D = nv T /I D. i D = I D + i d, v D = V D + v d = v d = i d r D

25 Temperature Dependence Temperature Dependence: For a pn-junction diode, i D I s e vd/nvt. I s grows exponentially with temperature (tending to increase i D or decrease v D ), while V T increases linearly with temperature (tending to have the opposite effect). For silicon at room temperature, I s essentially doubles every 5 C, and dominates the change in the diode current & voltage (i D increases with T, while v D decreases with T ). However, the amount of change in i D or v D depends on the bias conditions and on the ideality coefficient n.

26 Breakdown Diode Breakdown: If the reverse-bias voltage is large enough, the diode eventually breaks down and begins to conduct current in the reverse direction. The Breakdown Voltage is VZ. Avalanche breakdown occurs when the depletion region electric field is large enough to give carriers in the depletion region enough energy to free additional electron-hole pairs in the crystal. Usually VZ > 5 V for Silicon. VZ tends to increase with temperature. Zener breakdown is a quantum effect which occurs in highly doped devices with narrow depletion regions. Usually VZ < 7 V for Silicon. VZ tends to decrease with temperature. Silicon voltage regulation diodes commonly use Vz 5.7 V to achieve a very low temperature coefficient. In breakdown the resistance rz gives the relationship between small changes in the diode voltage and current: vd = rz id.

27 Semiconductors Periodic Table Segment III IV V B C N Al Si P Ga Ge As In Sn Sb

28 Physical Constants Physical Constants k = ev/k = J/K q = coulomb ɛ 0 = F/cm V T = kt/q = 25.8 mv at 300K Silicon at 300K: E G = 1.12 ev ɛ r = 11.7 n i = p i = cm 3 µ n 1350 cm 2 /V s D n 34.8 cm 2 /s µ p 480 cm 2 /V s D p 12.4 cm 2 /s

29 Moving Charge Charge Movement Mobile charge carriers include electrons located in the conduction band (and are therefore loosely bound to the crystal), and holes which indicate the absence of an electron in the valence band. The electron and hole density are denoted n and p. The charge density due to the mobile carriers is nq and pq, where q is the charge of a single electron/hole. If the temperature is nonzero (T 0) these carriers are always moving randomly. Current is the average movement of this cloud of charge carriers. DRIFT is the movement of the charge due to an applied electric field, E. Electrons and holes reach an average velocity of µ ne and µ pe respectively, where µ n and µ p are the electron and hold mobility for the crystal. The current density due to drift of carriers is (Ohm s law): J drift = pqµ pe + nqµ ne = q(pµ p + nµ n)e = E ρ, ρ = 1 q(pµ p + nµ n) = resistivity If the carrier density is not uniform (n and p depend on the position x in the crystal), then the random motion of the carriers causes a net current which tends to even out the carrier density. This net current is DIFFUSION, and is proportional to the negative of the rate of change of the charge densities: J diff = D n ( q dn dx ) D p ( q dp dx The diffusivities D n and D p increase with temperature and with mobility. The Einstein Relationship gives D n = Dp = V T = kt ( 25.8 mv for T = 300 K) µ n µ p q )

30 Resistivity Resistivity/Resistance The resistance of a sheet of material with thickness t, width W, and length L is R = ρ L ( ρ ) ( tw = W t L ) A fab is likely to let a designer control L and W, and usually provides the sheet resistance ρ/t.

31 Intrinsic Silicon Carier Density Si Approximation: n i2 doubles every 5 degrees n i =1.5 x at 300K n i 2 T 3 e E G /kt E G =1.12 ev

32 Doping Carrier densities are controlled by introducing dopants into a crystal. Group V elements are donors, which ionize to introduce a conduction-band electron. The positive-charged ion remains fixed within the crystal lattice. Group III elements are acceptors which ionize by adopting an electron in the valance band from a neighboring atom, creating a hole. In this case, the fixed ion is negatively charged. The donor and acceptor concentrations in a crystal are denoted N D and N A. The Mass-Action Law relates the carrier concentrations by np = n 2 i, where n i is the intrinsic (undoped) carrier concentration (which depends strongly on temperature). The doping concentration is used to determine the majority carrier concentration. The minority carrier concentration is determined by the mass-action law and remains highly temperature dependent. n-type: N D N A n = N D N A p = n 2 i /n p-type: N A N D p = N A N D n = n 2 i /p

33 Silicon Mobility Vs Temperature and Doping Level Carrier Mobility Trends For Silicon n 1350 at 300K (No doping) p 480 at 300K (No doping)

34 Unbiased Junction For no applied voltage, free majority carriers near a pn junction tend to diffuse into the opposite region (in the diagram, holes diffuse to the right, and electrons to the left). The result is a depletion region near the junction in which no free carriers are available, and the bound charge due to the ionized dopant atoms remain. The presence of the bound charge creates an electric field in the depletion region which opposes the diffusion of free charge carriers. The depletion region expands until the drift current associated with the electric field cancels the diffusion current. The built in potential V0 is the voltage that develops across the junction associated with the developed uncovered charge/electric field. At equilibrium (for an abrupt pn junction with no applied voltage), ( ) NAND V0 = VT ln wd0 = xn + xp = n 2 i 2ɛ q V0 ( ) NA xn0 = wd0 NA + ND ( ND ) xp0 = wd0 NA + ND ( NA ND )

35 Junction With External Voltage An external voltage applied to the pn-junction opposes the built-in potential, so that the actual voltage across the pn junction becomes V0 vd. The effect is to change the width of the depletion region. The stored charge, E-field strength, depletion region widths, etc. can be calculated using the same equations as for the zero-bias case by replacing V0 with the new junction voltage V0 vd. The result is that xn, xp and wd are all scaled by 1 vd/v0 from their zero-bias values. e.g. V0 vd wd = wd0 = wd0 1 vd V0 V0 For a reverse bias (vd < 0), the depletion region becomes wider. The majority charge carriers do not have enough energy to diffuse across the (increased) junction voltage. Only a small current ( Is) due to the drift of minority carriers through the junction remains. ( id = n 2 Dn i qa LnNA ) + Dp LpND }{{} Is A forward bias (vd > 0) decreases the width of the depletion region. The number of majority carriers with enough energy to diffuse across the junction increases exponentially as vd grows and the junction voltage decreases. ( ) ( ) e vd/vt 1 = Is e vd/vt 1 Is = Reverse Saturation Current A = Junction cross-sectional area Ln = Diffusion length of electrons in the p-type material Lp = Diffusion length of holes in the n-type material

36 Junction Capacitance The Junction or Depletion capacitance of a diode reflect change in the uncovered charge stored in the depletion-region of a pn-junction. The small-signal junction capacitance is C J = ɛa w D This is the parallel-plate capacitance for two plates separated by distance w D. For a DC bias voltage V D across the diode, the result is usually written in terms of the zero-bias value C J0 = ɛa/w D0 : C J = C J0 (1 V D /V 0 ) m (m = 0.5 for an abrupt pn junction.)

37 Diffusion Capacitance The Diffusion capacitance of a forwardbiased diode reflects change charge associated with the excess minority carriers near the pn junction. The diffusion capacitance is proportional to the diffusion current through the diode. Let τ T be the mean transit time of the diode (the average time for minority carriers to recombine). Then the smallsignal diffusion capacitance is C DIFF = τ T I s V T e V D/V T τ T V T I D

38 npn BJT Structure An npn BJT consists of two pn junctions with a shared p-type base region. By design, the n-type emitter region is heavily doped relative to the base and collector, so that electrons carry the majority of the current in the device. Depletion regions form at both the base-collector (BC) junction and at the base-emitter (BE) junction. The base width w B is kept small, so that most electrons which diffuse into the base cross the base without recombining with the free holes in the base.

39 Forward Active npn Current Flow When used as an amplifier, a BJT is normally biased in the forward-active region of operation (forward biased BE Junction, reverse biased BC junction). In this case, the current flow is controlled by setting the BE junction voltage. Since most of the carriers crossing the BE junction are electrons, and most of these diffuse across the base and are swept into the collector, very little base current is needed to control large emitter and collector currents. The collector current is relatively insensitive to the collector voltage, provided the BC junction remains reverse biased. γ F : ➀ Injection Efficiency: Fraction of BE current carried by electrons (close to one, we hope.) B T : ➁ Base Transport Factor: Fraction of electrons crossing the base without recombining (also close to one, provided w B is small) α F = γ F B T = ic i E β F = αf = ic 1 α F i B (Close to one?) (Large?)

40 npn Large Signal Models Forward-active npn large-signal model. Current swept into the collector through the BC junction depletion region is modeled as a controlled current source. Equivalent forward-active npn largesignal model relating the collector current to the base current. Ebers-Moll Model: modes of operation. Used for all ( ) I SE = Aqn 2 Dn i + Dp w BN A L pn D ( ) I S α F I SE = B T γ F I SE = B T Aqn 2 Dn i w BN A Base Width Modulation: Since the width of the BC depletion region changes with the collector voltage, the base width w B gets smaller as v CE grows. The result is that the collector current increases (slightly) with v CE. Rather than writing the (complicated) relationship between v CE and I S (and α F ), this Early Effect is modeled as a linear change by leaving I S and α F as constants, but scaling the collector current by a factor of (1 + v CE/V A). V A is the Early voltage.

41 npn BJT Large Signal Characteristics npn BJT Large-Signal Behavior Cutoff Mode: Both the BE and BC junctions are reverse-biased. Very little current flows. Saturation Mode: Both the BE and BC junctions are forward-biased. The collector and emitter voltages are within a few tenth of volts from each other (v CE < 0.2 V). Base currents may be significant. Forward Active Mode: BE junction is forward biased, and BC junction is reverse biased. Most carriers injected into the BE junction are swept out through the collector depletion region, so that base currents remain small. The collector current is determined primarily by the BE diode voltage, and is nearly independent of the collector voltage. ( ) i C = αi E = βi B = I se vbe/vt 1 + vce V A V T = kt q 25.8 mv at T = 300 K α = β β + 1

42 pnp Transistors An pnp BJT consists of two pn junctions with a shared n-type base region. The p- type emitter region is heavily doped, so that holes carry the majority of the current in the device. The base width wb is kept small, so that most holes which diffuse into the base cross the base without recombining with the free electrons in the base. Forward Active Operation: (forward biased EB Junction, reverse biased CB junction) Current flow is controlled by setting the EB junction voltage. Since most of the carriers crossing the BE junction are holes, and most of these diffuse across the base and are swept into the collector, very little base current is needed to control large emitter and collector currents. Forward-active pnp large-signal model relating the collector current to the emitter current. Equivalent forward-active pnp large-signal model relating the collector current to the base current. Ebers-Moll Model: Used for all modes of operation.

43 pnp BJT Large Signal Characteristics pnp BJT Large-Signal Behavior pnp BJTs are governed by the same voltage/current relationships as npn BJTs, except that the polarities of the voltages and currents are reversed: Cutoff Mode: Both the EB and CB junctions are reverse-biased. Very little current flows. Saturation Mode: Both the EB and CB junctions are forward-biased. The collector and emitter voltages are within a few tenth of volts from each other (v EC < 0.2 V). Base currents may be significant. Forward Active Mode: EB junction is forward biased, and CB junction is reverse biased. Most carriers injected into the EB junction are swept out through the collector depletion region, so that base currents remain small. The collector current is determined primarily by the EB diode voltage, and is nearly independent of the collector voltage. i C = αi E = βi B = I se veb/vt ( 1 + vec V A ) V T = kt q 25.8 mv at T = 300 K α = β β + 1

44 BJT Small Signal Characteristics npn BJT Small-Signal Behavior Once a DC operating point is determined (the transistor bias or quiescent point or Q-point ), deviations from the operating point can be predicted using a linear circuit model. The hybrid-π model and T-model are shown below. DC Operating Point:I C, I B, I E, V BE, V CE i X = I X + i x v XY = V XY + v xy g m = IC V T r π = β g m r e = α g m VA + VCE r 0 = VA I C I C

45 BJT Small Signal Characteristics pnp BJT Small-Signal Behavior Once a DC operating point is determined (the transistor bias or quiescent point or Q-point ), deviations from the operating point can be predicted using a linear circuit model. The hybrid-π model and T-model are shown below. DC Operating Point:I C, I B, I E, V EB, V EC i X = I X + i x v XY = V XY + v xy g m = IC V T r π = β g m r e = α g m VA + VEC r 0 = VA I C I C

46 nmos: Structure n-channel MOSFET Structure The n-channel MOSFET is formed in p-type body. The source and drain are n-type regions, separated by the channel length L. The gate is a conductor which is insulated from the body by a thin oxide layer. In operation, the body is kept at a low voltage to avoid forward biasing the PN junctions at the source and drain terminals. Voltages applied to the gate terminal create an electric field which alter the properties of the channel (directly below the gate oxide). By changing the gate voltage, current between the drain and source is regulated.

47 nmos: No Bias Voltages nmos Transistor (all terminals grounded) If all nmos terminals are grounded, no current flows in the device. Depletion regions (with the associated electric field) form at both the source and drain pn junctions. Here, the pn junction diodes are explicitely shown. For an nmos transistor, the body voltage is held at or below the source and drain voltages to ensure that these diodes never conduct significant current.

48 nmos: Subthreshold nmos Transistor (subthreshold) For a small positive gate voltage, an electric field is created which drives free holes into the body (away from the gate oxide). The depletion region extends across the channel. Positive charge stored on the gate is offset by the negative charge associated with the ionized dopants in the body (now uncovered in the depletion region). For our purposes, no significant current flows between the source and the drain. (There are actually small currents which grow exponentially as the gate voltage nears the threshold voltage... but we don t talk much about those!)

49 nmos: Ohmic/Triode nmos Transistor ( ohmic or triode operation) As the gate voltage (relative to the source) grows beyond a fixed threshold voltage (V t ), eventually free electrons are attracted to the region directly below the gate oxide. This layer of electrons in the p-type body is the inversion region. A positive voltage applied to the drain can now cause current flow between the source and drain through this conductive channel. Ohmic or Triode operation implies that the channel exists both at the source and drain ends of the channel (V GS > V t and V GD > V t ). Relative to the source terminal, the voltage conditions are V GS > V t, 0 < V DS < V GS V t

50 nmos: Saturation/Pinch-off nmos Transistor ( pinch-off or saturation operation) As the drain voltage increases beyond V GS V t, the gate voltage is not sufficient to support the inversion region near the drain terminal. The channel becomes pinched off. Current still flows in the device: free electrons at the pinched-off end of the channel are swept into the drain by the electric field in the drain-body depletion region. The current flow becomes (nearly) independent of the actual drain voltage (but changes in the channel length cause small changes in the current channellength modulation ).

51 MOSFET Large Signal Characteristics n-channel MOSFET Large-Signal Behavior Cutoff Region: No channel at the source or the drain (vgs < Vt). Very little current flows. Triode (Ohmic) Region: Channel is supported at both the source and the drain (vgs > Vt and vgd > Vt; or equivalently vov = vgs Vt > 0 and vds < vov ). The drain current is initially proportional to vds, with slope 1/rDS, but falls off as vds increases and the device enters saturation. id = k W [ (vgs Vt)vDS 1 ] L 2 v2 DS k 1 = µncox = k W rds L (vgs Vt) = W k L vov Saturation (Pinch-off) Region: Channel is supported at the source, but not at the drain (vgs > Vt and vgd < Vt; or equivalently vov > 0 and vds > vov ). The carriers in the channel are swept to the drain through the Drain-Body depletion region, so the current is nearly independent of the drain voltage. id = k W 2 L (vgs Vt)2 (1 + λvds) = k W 2 L v2 OV (1 + λvds) λ = 1 VA = λ L = 1 V A L Threshold voltage depends on VSB: Vt = Vt0 + γ [ 2φf + VSB 2φf ]

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