IPS022G/IPS024G DUAL/QUAD FULLY PROTECTED POWER MOSFET SWITCH

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1 Preliminary Data Sheet No.PD 69-G IPSG/IPSG DUAL/QUAD FULLY PROTECTED POWER MOSFET SWITCH Features Over temperature shutdown Over current shutdown Active clamp Low current & logic level input E.S.D protection Description The IPSG/IPSG are fully protected dual/quad low side SMART POWER MOSFETs respectively. They feature over-current, over-temperature, ESD protection and drain to source active clamp.these device combine a HEXFET POWER MOSFET and a gate driver. They offer full protection and high reliability required in harsh environments. The driver allows short switching times and provides efficient protection by turning OFF the power MOSFET when the temperature exceeds 65 o C or when the drain current reaches 5A. These device restart once the input is cycled. The avalanche capability is significantly enhanced by the active clamp and covers most inductive load demagnetizations. Product Summary R ds(on) V clamp I shutdown T shutdown T on/ T off Available Package 8 Lead SOIC IPSG (Dual) 5mW (max) 5V 5A 65 o C.5ms 6 Lead SOIC IPSG (Quad) Typical Connection Load R in series (if needed) IN control ƒ D S Logic signal

2 Absolute Maximum Ratings Absolute maximum ratings indicates sustained limits beyond which damage to the device may occur. All voltage parameters are referenced to SOURCE lead. (TAmbient = 5 o C unless otherwise specified). PCB mounting uses the standard footprint with 7 mm copper thickness. Symbol Parameter Min. Max. Units Test Conditions V ds Maximum drain to source voltage 7 V in Maximum input voltage Iin, max Maximum IN current - + ma Isd cont. Diode max. continuous current () (å lsd mosfets, rth=5 o C/W). Isd pulsed Diode max. pulsed current () (for ea. mosfet) Pd Maximum power dissipation () (å Pd mosfets, rth=5 o C/W) W ESD Electrostatic discharge voltage (Human Body) tbd C=pF, R=5W, ESD Electrostatic discharge voltage (Machine Model) tbd V C=pF, R=W, Tj max. Max. storage & operating junction temp o C V A Thermal Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Rth Thermal resistance with standard footprint ( mos on) ( mosfets on) 5 Rth Thermal resistance with standard footprint ( mos on) ( mosfet on) 7 Rth3 Thermal resistance with " square footprint ( mos on) ( mosfets on) 8 Rth Thermal resistance with standard footprint ( mos on) ( mosfets on) 75 Rth Thermal resistance with standard footprint (mos on) ( mosfet on) Rth3 Thermal resistance with " square footprint ( mos on) ( mosfets on) 6 o C/W SOIC-8 SOIC-6 () Limited by junction temperature (pulsed current limited also by internal wiring)

3 Recommended Operating Conditions These values are given for a quick design. For operation outside these conditions, please consult the application notes. Symbol Parameter Min. Max. Units Vds (max) Continuous drain to source voltage 35 VIH High level input voltage 6 V VIL Low level input voltage.5 Ids Continuous drain current Tamb=85 o C (TAmbient = 85 o C, IN = 5V, rth = o C/W, Tj = 85 o C) IPSG A (TAmbient = 85 o C, IN = 5V, rth = o C/W, Tj = 5 o C) IPSG.7 Rin Recommended resistor in series with IN pin.5 5 kw Tr-in (max) Max recommended rise time for IN signal (see fig. ) ms Fr-Isc () Max. frequency in short circuit condition (Vcc = V) khz Static Electrical Characteristics (Tj = 5 o C unless otherwise specified.) Symbol Parameter Min. Typ. Max. Units Test Conditions Rds(on) ON state resistance Tj = 5 o C o C Rds(on) ON state resistance Tj = 5 o C 9 6 mw Vin = 5V, Ids = o C Idss Drain to source leakage current.5 5 ma Vcc = V, Tj = 5 o o C Vin = V V clamp Drain to source clamp voltage 7 5 Id = ma (see Fig.3 & ) V clamp Drain to source clamp voltage 5 6 Id=Ishutdown (see Fig.3 & ) Vsd Body diode forward voltage.85 Id = A, Vin = V Vin clamp IN to source clamp voltage V Iin = ma Vth IN threshold voltage.6 Id = 5mA Iin, on Input supply current (normal operation) 5 8 Vin = 5V ma Iin, off Input supply current (protection mode) Vin = 5V over-current triggered Switching Electrical Characteristics Vcc = V, Resistive Load = W, Rinput = 5W, msec pulse, T j = 5 o C, (unless otherwise specified). Symbol Parameter Min. Typ. Max. Units Test Conditions Ton Turn-on delay time.5 Tr Rise time See figure Trf Time to 3% final Rds(on) 6 msec Toff Turn-off delay time See figure Tf Fall time.3 Qin Total gate charge 3.3 nc Vin = 5V () Operations at higher switching frequencies is possible. See Appl. notes. 3

4 Protection Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Tsd Over temperature threshold 65 o C See fig. Isd Over current threshold 5 A See fig. V in,min,prot Minimum IN voltage for protection 3 V Treset Minimum time for protection reset ms Vin = V EOI_OT Short circuit energy (cf application note) mj Vcc = V Functional Block Diagram All values are typical DRAIN 7 V W kw IN S Q 7.5 V 8 ma R Q T > 65 c I sense I > Isd SOURCE Lead Assignments D D D D D D D D D3 D3 D D S In S In S I S I S3 I3 S I 8 Lead SOIC (Dual) 6 Lead SOIC (Quad) IPSG Part Number IPSG

5 Case Outline - 8 Lead SOIC - 8 Case Outline - 6 Lead SOIC (narrow body) -36 5

6 Vin 5 V V Vin 9 % % Ids Isd I shutdown t < T reset t > T reset Ids Tr-in 9 % % T Tsd (65 c) T shutdown Vds Td on tr Td off tf Figure - Timing diagram Figure - IN rise time & switching time definitions T clamp Vin L V load Ids Vds Vds clamp ( Vcc ) Rem : V load is negative during demagnetization 5 v v Vin IN R D S Vds Ids + V - ( see Appl. Notes to evaluate power dissipation ) Figure 3 - Active clamp waveforms Figure - Active clamp test circuit 6

7 All curves are typical values with standard footprints. Operating in the shaded area is not recommended Tj = 5 o C Tj = 5 o C Figure 5 - Rds ON (mw ) Vs Input Voltage (V) Figure 6 - Normalised Rds ON (%) Vs Tj ( o C) ton delay rise time 3% rdson Figure 7 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) Vs Input Voltage (V) 3 toff delay fall time Figure 8 - Turn-OFF Delay Time & Fall Time (us) Vs Input Voltage (V) 7

8 delay on rise time 3% rdson delay off fall time. Figure 9 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) Vs IN Resistor (W ). Figure - Turn-OFF Delay Time & Fall Time (us) Vs IN Resistor (W ) Isd 5 C Ilim 5 C Figure - Current Iim. & Ishutdown (A) Vs Vin (V) Figure - Over-current (A) Vs Temperature ( o C) 8

9 5 Std. footprint 7 C/W mosfet on Std. footprint C/W mosfets on 5 Std. footprint 75 C/W o o mosfet mofet on on mosfet on Std. footprint C/W o mosfet on mosfets on Figure 3a - Max.Cont. Ids (A) Vs Amb. Temperature ( o C) - IPSG Figure 3b - Max.Cont. Ids (A) Vs Amb. Temperature ( o C) - IPSG T=5 C Std. footprint T= C Std footprint single pulse Hz rth= C/W dt=5 C khz rth= C/W dt=5 C Current path capability should be above this curve Load characteristic should be below this curve Figure - Ids (A) Vs Protection Resp. Time (s) IPSG/IPSG Vbat = V Tjini = T sd for single pulse all curves for mosfet active... Figure 5a - Iclamp (A) Vs Inductive Load (mh) IPSG 9

10 single pulse Hz rth= C/W dt=5 C khz rth= C/W dt=5 C. Vbat = V Tjini = T sd for single pulse all curves for mosfet active.. Figure 5b - Max. Iclamp (A) Vs Inductive Load (mh) - IPSG.. Single pulse rth mosfet active rth mosfets active Figure 6a - Transient Thermal Imped. ( o C/W) Vs Time (s) - IPSG.. Single pulse rth mosfet on rth mofets on Figure 6b - Transient Thermal Imped. ( o C/W) Vs Time (s) - IPSG

11 WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 95 Tel: (3) IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 5 Lincoln Court, Brampton, Ontario L6T 3Z Tel: (95) 53- IR GERMANY: Saalburgstrasse 57, 635 Bad Homburg Tel: IR ITALY: Via Liguria 9, 7 Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., F, 3- Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 7 Tel: IR SOUTHEAST ASIA: Kim Seng Promenade, Great World City West Tower, 3-, Singapore 3799 Tel: IR TAIWAN: 6 Fl. Suite D..7, Sec., Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice. 9/5/98

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