Advantech IP List. AT to ATX power design July

Transcription

1 Advantech IP List AT to ATX power design July

2 Introduction Wide input voltage range of +VIN_DC: 8.5V to 20V The output voltage of VO1 is 5V, VO2 is 3.3V. Built-in 100-mA 5-V/3.3-V LDO with switches. Refer to Page 22, VREG5/VREG3 Linear Regulators With/Without Out-of-Audio mode selectable light load and PWM only operation. Refer to: Page 19, PWM Operations. Page 22, Out-of-Audio Light-Load Operation. Internal 1.6-ms voltage servo soft start. Refer to Page 22, Enable and Soft Start. Adaptive On-Time control architecture with four selectable frequency setting. Refer to Page 19, Adaptive On-Time Control and PWM Frequency. Built-In output discharge. Refer to Page 23, Output Discharge Control. Power good output. Refer to Page 23, Powergood. Built-in OVP/UVP/OCP. Refer to Page 25, Current Protection and Over/Under Voltage Protection. Thermal shutdown (non-latch). Refer to page 26, Thermal Shutdown. Component selection. Refer to page 26, External Parts Selection. User-Selectable power supply mode as AT or ATX by jumper setting (PJUMP1).

3 I/O and PIN FUNCTIONS DISCUIRPTION PSON (Pin PJUMP1. 2/4): +VIN enable pin. Connect to PQ9.2 to turn on +VIN. An external jumper is connected (PJUMP1.1-PJUMP1.2) or (PJUMP1.3-PJUMP1.4) for select power mode as AT or ATX. PJUMP1 Link Pin1 and Pin2 Link Pin3 and Pin4 Power Supply mode AT Power Supply ATX Power Supply Application Note FUNCTIONS DISCUIRPTION TONSEL (Pin PU3.4): On-time adjustment pin. PWM frequencies are set by TONSEL terminal connection. TONSEL Switching Frequency Channel CH1 CH2 Connect to VREF(PR69) 245 khz 305 khz Connect to VREG5(PR70) 365 khz 460 khz SKIPSEL (Pin PU3.14): Selection pin for PWM operation mode. SKIPSEL Connect to VREG3(PR65) Connect to GND(PR66) Operation Mode *OOA auto skip **PWM only *OOA auto skip: Refer to Page 22, Out-of-Audio Light-Load Operation. **PWM only: Refer to Page 19, PWM Operations.

4 PCB Layout Considerations Certain points must be considered before starting a layout work using the TPS TPS51125 has only one GND pin and special care of GND trace design makes operation stable, especially when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF capacitor as close as possible, connect them to an inner GND plane with Power Pad, overcurrent setting resistor, EN0 pull-down resistor and EN0 bypass capacitor as shown in the thin GND line of Figure 40. This trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as possible, and connect them to another inner GND plane with GND pin of the device, GND terminal of VREG3 and VREG5 capacitors and 15-V charge-pump circuit as shown in the bold GND line of Figure 40. This trace is named Power Ground (PGND). SGND should be connected to PGND at the middle point between ground terminals of VOUT capacitors. 2. Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Power components of each channel should be at the same distance from the TPS Other small signal parts should be placed on another side (component side). Inner GND planes above should shield and isolate the small signal traces from noisy power lines. 3. PCB trace defined as LLx node, which connects to source of high-side

5 MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible. 4. VREG5 and VREG3 require at least 10-µF, VREF requires a 220-nF ceramic bypass capacitor which should be placed close to the device and traces should be no longer than 10 mm. 5. Connect the overcurrent setting resistors from ENTRIPx to SGND and close to the device, right next to the device if possible. 6. The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3 is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the device. Place on the component side and avoid vias between this resistor and the device. 7. Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace. 8. All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, ENTRIPx, PGOOD, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, DRVHx and VCLK nodes to avoid coupling. 9. Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel interference. 10. In order to effectively remove heat from the package, prepare thermal land and solder to the package s thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. This thermal land underneath the package should be connected to SGND, and should NOT be connected to PGND.

6 Schematic Component List Number Quantity Part Reference Value 1 1 JPS1 NL/ATX_2x2V_4.2mm 2 1 JPS2 DCJACK_2 3 1 PC1 10uF 4 8 PC2,PC4,PC13,PC15, PC17,PC19,PC27,PC46 100nF 5 2 PC3,PC8 10uF 6 1 PC7 22uF 7 1 PC11 220nF 8 2 PC12,PC18 1nF 9 2 PC14,PC45 10uF 10 2 PC16,PC21 330uF 11 2 PC29,PC30 NL/1uF 12 2 PC47,PC48 1uF 13 2 PD1,PD2 NL/SK36B 14 1 PD6 SMBJ24A 15 1 PFS DR 16 1 PJUMP1 PH_2x2V_2.54mm 17 1 PJUMP1(3-4) MINIJUMPER_2_2.54mm 18 1 PL1 1.0uH 19 1 PL2 1.5uH 20 2 PQ1,PQ2 CSD87330Q3D 21 1 PQ8 AON PQ9,PQ11,PQ12 2N7002DW-7-F 23 1 PQ10 AO PR2 2m

7 25 1 PR PR5 28.7K 27 2 PR6,PR9 20K 28 1 PR7 NL/100K 29 1 PR8 12K 30 1 PR10 620K 31 6 PR11,PR14,PR22, PR49,PR65,PR PR12 56K 33 1 PR13 62K 34 4 PR15,PR21,PR24,PR PR26,PR27 NL/ PR48 1K 37 1 PR50 68K 38 2 PR51,PR62 100K 39 1 PR PR61,PR63 10K 41 1 PR64 330K 42 2 PR66,PR70 NL/ PR67,PR68 NL/1M 44 1 PU3 TI_TPS51125RGET