Evaluation Kit User s Guide

Transcription

1 khz, -Bit Conversion EVK Features Buffers to drive analog inputs Full scale input level dbu F S up to khz via I S/LJ F S up to khz via AES & S/PDIF Multibit and DSD outputs ATEVK R. Low Group Delay & Pre-Ringing Filter Digital High Pass & Offset Cancellation Overflow Indicator drives LEDs Supports Logic Levels from V to V QFN- Green Package, mm x mm Analog Supply V Digital Supply V to V Reference Generator Multibit Output Formatter DSD Generator Highpass Filter Enable Sampling Rate Select Overflow Indicator Left Channel Input Right Channel Input Multibit Σ Modulator Multibit Σ Modulator bits bits Antialias & Highpass Filter Antialias & Highpass Filter DSD Generator Multibit Output Formatter Input / Output Interface Master/Slave Mode Multibit Outputs DSD Outputs PCM Outputs Output Mode Select Master Clock LJ/I S Select Serial Clock Left/Right Clock AT Block Diagram General Description The evaluation kit demonstrates the performance and features of the AT. The kit provides several methods for generating data from the ADC including PCM outputs through the natively generated I S or LJ streams, as well as using an on-board DIT to provide AES compliant output through an XLR interface, an electrical S/PDIF interface, and an optical S/PDIF interface. The multibit modulator outputs and DSD outputs are available through headers on the board for interfacing to data acquisition equipment, an FPGA board, or a DSP. Rev.. Arda Technologies, Inc. Page of

2 khz, -Bit Conversion ATEVK R. Testing the ATEVK This section describes the test setup for the evaluation board. Items Needed. AT Evaluation Board Rev... Rohde & Schwarz UPV, Audio Precision SYS- or equivalent Audio Analyzer. Power supplies for V and ±V and power cables. Two XLR male to female cables to connect signal generators to the board. An XLR cable, an S/PDIF optical cable, an RCA cable, or a -pin header with a ribbon cable to connect ADC outputs to the analyzer. Audio Interfaces and Supported Sampling Rates Some audio interfaces have speed limitations that prevent them from supporting certain audio sampling rates. The following table shows the rates supported by each interface. AES S/PDIF S/PDIF I S Optical RCA Single:./ khz Y Y Y Y Dual:./ khz Y Y Y Y Quad:./ khz Y Y Y Y Octal:./ khz N N N Y Table : Sampling Rates Supported by Various Interface Standards The I S interface has been tested successfully at khz using a Rohde & Schwarz UPV with the optional I S plug-in card. Rev.. Arda Technologies, Inc. Page of

3 khz, -Bit Conversion ATEVK R. Evaluation Board Overview Test Procedure for PCM Output. Connect signal generators to analog inputs (J and J) with XLR cables. The input buffers are configured such that full scale input corresponds to approximately V or dbu.. Connect the desired output to the signal analyzer. The EVK provides an S/PDIF Optical output. It can additionally be configured for either the AES output or the S/PDIF RCA output. To use AES XLR output, remove any jumpers from J. To make the S/PDIF RCA output functional, you must place two jumpers vertically in J.. Connect V, V and -V power supplies. Rev.. Arda Technologies, Inc. Page of

4 khz, -Bit Conversion ATEVK R.. Set the sampling rate as shown below in SW for the AT Mode SW: - M SW: - M SW: - MDIV Single Low Low High Double Low High High Quad High Low High Octal High High Low. Set the sampling rate as shown below in SW for the Digital Audio Transmitter Mode SW: - DITCK SW: - DITCK Single High High Double Low High Quad Low Low. Other settings for SW/SW/SW switches Switch Name Function SW: CLKEXT Enables external MCLK clock input SW: CLKM Enables crystal oscillator Y SW: CLKM Enables crystal oscillator Y SW: HPF_B : enable high pass filter : disable high pass filter SW: IS_LJ : left justified PCM output : I S PCM output SW: MS : PCM slave mode : PCM master mode SW: DSD_EN : disable DSD outputs : enable DSD outputs SW: MBO_EN : disable multibit outputs : enable multibit outputs SW: PCM_EN : disable PCM outputs : enable PCM outputs SW: XOK Enables khz-base XO SW: XOK Enables. khz-base XO SW: EXTWC Enables external WCLK clock input. Press the ADC reset push button followed by the DIT reset push button. The current draw should be approximately ma from the V supply and ma from the ±V supplies. Note that power consumption is sampling rate and audio interface dependent.. Repeat the reset procedure after each mode change. Rev.. Arda Technologies, Inc. Page of

5 khz, -Bit Conversion ATEVK R. Clocking Modes The ATEVK supports several mechanisms for providing a master clock to the device under test: an external MCLK clock via BNC connector J, on-board crystal oscillators Y and Y, and an optional phase-locked loop, which may be specified at the time of ordering. Source selection is performed by using switches SW:.. to select each of the MCLK sources, respectively. Note that only one of these switches should be in the HIGH position at any time, and SW: should be in the LOW position as well. By default, the evaluation kit comes with a. MHz crystal oscillator in position Y and no PLL oscillator. The default. MHz crystal oscillator provides an on-board low jitter source for operating the AT at khz, khz, khz, and khz PCM modes in addition to MBO and DSD modes. For clock rates at multiples of. khz, an oscillator can be added at position Y; this is also available upon request from Arda. PLL configuration If your EVK is supplied with a phase-locked loop XO, it can be used by introducing a base-rate (PCM mode) clock at the BNC connector, choosing the desired XO at SW: or, and enabling the external clock using SW:. The three MCLK sources at SW should be disabled, and only one XO should be enabled at a time. The clock supplied to the BNC input should be within approximately ppm above or below the desired base rate, and the AT must have PCM mode enabled (SW: HIGH) and be in Master mode (SW: HIGH) for the PLL to lock. DSD and MBO modes can also be used, though the MCLK is supplied by the EVK and locking to an external MCLK is not supported. Overflow The overflow indicator output from the IC carries overflow information for both channels as a time multiplexed signal. The indicator drives an LED directly and is demuxed to drive two other LEDs representing each channel. Buffer Gain & Bandwidth The analog input buffers, U and U, have been designed for a khz -db, single pole roll-off. The buffer bandwidth can be altered by changing passives around the operational amplifiers. This is a complicated process that can have a significant impact on the performance of the DUT. Arda Technologies will provide assistance if a different bandwidth is desired. The signal gain through the input buffers is approximately. V/V, making the full-scale input level dbu. As with the buffer bandwidth, the gain can be altered by changing passives. Arda Technologies will provide assistance if a different gain is desired. Digital Highpass Filter A first-order IIR highpass filter is present in the PCM signal path. The -db frequency is.hz at Fs = khz and scales with Fs. The filter is activated using SW:. The highpass filter can be turned on for a few seconds to acquire the signal path offset and then disabled. Once disabled, the offset continues to be subtracted from the signal, but the filter s frequency response is no longer present. Alternatively, the filter can be left enabled to operate continuously. Rev.. Arda Technologies, Inc. Page of

6 khz, -Bit Conversion ATEVK R. Test Procedure for DSD and MBO Outputs Multibit and DSD outputs are available on the evaluation board. To activate these outputs, the MBO_EN or the DSD_EN signals must first be set high in SW. The MBR.. MBR and MBL.. MBL outputs, corresponding to the right and left channels, respectively, begin to toggle when the MBO_EN signal is high. Bit is the MSB, and bit is the LSB. These logic signals must be clocked on the rising edge of the DCLK output from the DUT. The DSDR and DSDL outputs, corresponding to the right and left channels, respectively, are activated when the DSD_EN signal is high. They must be clocked on the rising edge of the DCLK output from the DUT. Board Schematics and Layout Evaluation board schematics are illustrated on the following pages. Gerber files for the board layout are available on request. Contact Arda Technologies, Inc Castro Street, Suite A Mountain View, CA - USA Tel:... Fax:... support@ardatech.com Rev.. Arda Technologies, Inc. Page of

7 khz, -Bit Conversion ATEVK R. Typical Measured Performance The following plots show typical measured performance for the AT operating in the Evaluation Kit. Unless otherwise noted, AD =.V, DD =.V, khz test tone. Figure : THDN vs Amplitude Rev.. Arda Technologies, Inc. Page of

8 khz, -Bit Conversion ATEVK R. Figure : Level THDN vs Amplitude Rev.. Arda Technologies, Inc. Page of

9 khz, -Bit Conversion ATEVK R. Figure : THD vs Amplitude Rev.. Arda Technologies, Inc. Page of

10 khz, -Bit Conversion ATEVK R. Figure : THDN vs Frequency Operating level: - db FS Rev.. Arda Technologies, Inc. Page of

11 khz, -Bit Conversion ATEVK R. Tones: Hz and Hz at - db FS Figure : Intermodulation Rev.. Arda Technologies, Inc. Page of

12 khz, -Bit Conversion ATEVK R. Figure : Interchannel Isolation Channel driven at - db FS, channel undriven. Output of channel displayed. Rev.. Arda Technologies, Inc. Page of

13 khz, -Bit Conversion ATEVK R. ELUATION BOARD LICEE AGREEMENT BY USING THIS ELUATION PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIO OF THIS AGREEMENT. DO NOT USE THIS ELUATION PRODUCT UNTIL YOU HAVE READ AND AGREED TO THE FOLLOWING TERMS AND CONDITIO. IF YOU DO NOT AGREE WITH THEM, CONTACT THE ARDA TECHNOLOGIES WITHIN TEN () DAYS OF RECEIPT FOR ITRUCTIO ON RETURN OF THE UNUSED ELUATION PRODUCT FOR A REFUND OF THE PURCHASE PRICE PAID. LICEE. Arda Technologies, Inc. ("Arda") grants you the right to use the enclosed preproduction evaluation, demonstration, development, verification, or reference design board and/or kit, including any incorporated and/or accompanying software, components and documentation (collectively, the "Evaluation Product") solely for your evaluation, design and testing purposes. Certain software included with the Evaluation Product may be covered under a separate accompanying end user license agreement, in which case the terms and conditions of such end user license agreement shall apply to that software. PRE-PRODUCTION STATUS. The Evaluation Product is a pre-production product and has not been authorized under the rules of the United States Federal Communications Commission or the rules, regulations or laws of any country applicable to production systems or finished products for distribution to third parties. The Evaluation Product is not authorized for use in production systems, and may not be offered for sale or lease, or sold, leased or otherwise distributed. If the Evaluation Product is incorporated in a demonstration system, the demonstration system may be used by you solely for your evaluation, design and testing purposes. Such demonstration system may not be offered for sale or lease or sold, leased or otherwise distributed and must be accompanied by a conspicuous notice as follows: "This device is not, and may not be, offered for sale or lease, or sold or leased or otherwise distributed". OWNERSHIP AND COPYRIGHT. Title to the software, related documentation and all copies thereof remain with Arda and/or its licensors. You may not remove the copyright notices from the Evaluation Product. You agree to prevent any unauthorized copying of the Evaluation Product and related documentation. RESTRICTIO. You may not sell or otherwise distribute the Evaluation Product for commercial purposes, in whole or in part, or use the Evaluation Product in production systems. Except as provided in this Agreement or in the Evaluation Product s documentation, you may not reproduce the board or software or related documentation, or reverse engineer, de-compile or disassemble the software, in whole or in part. You agree that neither the Evaluation Product nor any other technical data received from Arda, nor the direct product thereof, will be directly or indirectly exported, re-exported or released to any destination or country for which the United States government or any agency thereof or other applicable non-u.s. governments or agencies, at the time of export, require an export license or other governmental approval, without first obtaining such license or approval. NO WARRANTY. The Evaluation Product is provided as is and with all faults without warranty of any kind. Arda and its licensors expressly disclaim all warranties, expressed, implied or otherwise, including without limitation, warranties of merchantability, fitness for a particular purpose and non-infringement of intellectual property rights. Arda and its licensors do not warrant that Rev.. Arda Technologies, Inc. Page of

14 khz, -Bit Conversion ATEVK R. the evaluation product is compliant with European Union directives on the restriction of the use of certain hazardous substances in electrical and electronic equipment (ROHS) or waste electrical and electronic equipment (WEEE), that the evaluation product is production-worthy, that the functions contained in the Evaluation Product will meet your requirements, or that the operation of the Evaluation Product will be uninterrupted or error free. You are responsible for determining whether the Evaluation Product will be suitable for your intended use or application or will achieve your intended results. Prior to using or distributing any systems that have been evaluated, designed or tested using the Evaluation Product, you agree to thoroughly test and validate your design implementation to confirm the system functionality for your application. Arda has not authorized anyone to make any representation or warranty for the Evaluation Product, and any technical, applications or design information or advice, quality characterization, reliability data or other services provided by Arda shall not constitute any representation or warranty by Arda or alter this disclaimer of warranty, and no additional obligations or liabilities shall arise from Arda s providing such information or services. Arda does not assume or authorize any other person to assume for it any other liability in connection with its Evaluation Products. LIMITATIO OF LIABILITY. Arda or its licensors shall not be liable for any special, consequential, incidental, indirect or punitive damages, including but not limited to, the costs of labor, requalification, delay, loss of profits or goodwill, whether arising out of Arda s performance or nonperformance of this agreement or the use or inability to use the Evaluation Product, even if Arda is advised of the possibility of such damages. In no event shall Arda s aggregate liability from any obligation arising out of or in connection with the license or use of any Evaluation Product provided hereunder, under any theory of liability including but not limited to contract, tort or promissory fraud liability, exceed the purchase price paid for the evaluation product, if any. To the maximum extent permitted under law, the limitations in this paragraph shall apply even if any limited remedy specified under this Agreement is found to have failed of its essential purpose. TERMINATION. Arda may terminate this license at any time if you are in breach of any of its terms and conditions. Upon termination, you will immediately return the Evaluation Product and documentation to Arda. GOVERNING LAW. This Agreement shall be governed by the laws of Delaware, excluding its principles of conflict of laws and the United Nationals Convention on Contracts for the Sale of Goods. NO WAIVER. The waiver by either party of any breach of any provision of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. SEVERABILITY. If any term of this Agreement becomes or is declared to be invalid, illegal or unenforceable in any respect by any court of competent jurisdiction, such condition shall not affect the validity or enforceability of any of the remaining terms which remain in full force and effect. Rev.. Arda Technologies, Inc. Page of

15 PCB R.% R.% PCB D R D v VOCM U PD -v R INLP v -v -v v INLN C C C R.nF COG -v R X Test Point C nf -v v -v v -v B B VOCM R. % PD -v R.% -v R.% X Test Point INRN INRP v -v BUFREF Arda Technologies, Inc Size Document Number Rev B AT. Date: Tuesday, December, Sheet of C nf R C nf C.nF COG R - OPADGN R.% R R R C.nF COG C nf C.nF COG X Test Point X Test Point C.nF COG R C nf R.% R K X Test Point C uf V C nf C.nF COG R. % C.nF COG X Test Point R R R R X Test Point C nf - UB LMMA C uf V R K J XLR-F R R K R. % C uf V C nf C nf R U R C.nF COG C uf V R.% X Test Point R.k % C uf V R.k % R - OPADGN C.nF COG R. % C.nF COG PCB-AT- UA LMMA - C uf V R.% J XLR-F R R K R C uf V C nf R A K A

16 EXTMCLK_EN v C C C C C v nf nf nf nf nf RA SW C UB R C nf LMMA uf V D D - RA Kx Array C R R nf -v OVFLB K C uf V C uf V RA x Array U D SML-LXIC-TR DIPswitch- CLKM CLKM IS_LJ MCLK Uout -v C nf C uf V C uf.v J RA x Array Vcc OE B B B B B B B B Dir A A A A A A A A Gnd Kx Array RA x Array C uf V POLYMER RA SNAHCPWR C SDOUT MBL x Array nf REFPL MBL - REFNL C R R U CMREFL CMREFL SDOUT uf V RA J DGND RA AGND Dir Vcc x Array INLP DD INLP A OE C C INLN INLN A B U DSDL A B AT DSDR AGND AD DCLK A B AD MBR A B MBR x Array AGND A B INRN INRN MBR A B INRP MCLK_PCM R INRP DGND A B UA MCLK_PCM AGND DD Gnd B C LMMA CMREFR CMREFR RSTB nf RSTB SNAHCPWR REFNR SCLK R SCLK Header_xpin REFPR LRCK Header_xpin LRCK - C R R RA uf V R U Vcc C Dir OE pf A A B Uout C x Array RA A B J uf V A B v POLYMER A B RA v A B A B C A B uf.v x Array Gnd B SNAHCPWR x Array B B R HPFB MDIV MBL MBL MBL MBL IS_LJ DGND DD AGND AGND AGND MCLK OVFLB M M C pf UA LMMA GND BUFREF AGND AGND PCM_EN DGND DGND DGND DGND DD DGND MBO_EN DSD_EN MS MBR MBR MBR MS MBO_En MBI_En BUFREF UB LMMA C nf - RA RA RA Kx Array Kx Array -v DITCK x Array -v DITCK SW C C uf V nf Header_xpin C R nf MBI_En A A R MBO_En Uout DIPswitch- Arda Technologies, Inc Size Document Number Rev B AT. Date: Tuesday, December, Sheet of C uf V U SNAHCGDBVR

17 MS SDOUT LRCK SCLK LRCK R U Dir A A A A A A A A Gnd C nf SNAHCPWR J VIO PCM Port Header_xpin VIO VIO Out Snse Byp Gnd In nc nc En U LTEMS-#PBF U SNAHCGDBVR Vcc OE B B B B B B B B C uf V C uf V C nf R PS C nf C uf V C C R C nf IS_LJ C nf DITCK DITCK L CSS COPY/C CLK CLK MCLK VIO DGND FMT FMT SCLK SYNC SDATA M/S U DITIPW Gnd B SNAHCPWR R. B B MODE U V BLS BLSM EMPH AUDIO MONO MDAT D TX TX- DGND RST Dual Footprint T - J XLR-M R J Header_xpin R OVFLB LRCK Overflow SNAHCPWR D D A A RSTB R k Arda Technologies, Inc J Audio RCA Jack Size Document Number Rev B AT. Date: Tuesday, December, Sheet of R K C nf SW Switch Button C pf SML-LXIC-TR R R D D MCLK_PCM RA x Array C nf RA x Array C nf GND Vcc Vin C nf J Conn_FiberOptic JP Jumper_pin R R RA x Array R U Dir A A A A A A A A Vcc OE B B B B B B B C uf V RA x Array R R U C CLR D CLK PRE Q Q CLR D CLK PRE Q Q GND C nf C nf RA x Array R K SW Switch Button A Y A Y A Y GND C A Y A Y A Y U SNAHCPWR R k SML-LXIC-TR C nf R U SNAHCGDBVR U SNAHCGDBVR C nf J Header_xpin C nf C nf

18 BP Yellow Post BP Red Post BP Red Post BP Green Post BP Black Post BP Black Post v -v PS PS PLL_MCLK EXTMCLK_EN R C nf C nf C nf C nf R CLK_BNC D D C C uf V C nf C nf C uf V C uf V C uf V R R C nf D Zener.V J D Zener.V D MMSZBTG D MMSZBTG nf MCLK_PCM R U U SNAHCGDBVR SNAHCGDBVR U SNAHCGUDBVR BNC R R PS JP Jumper_pin R C nf R k R M PS JP Jumper_pin C uf V C C PS C uf V U LTEMS- U LTEMS-. In In C nf nc nc En Out Snse Byp Gnd R U nc nc En Out Snse Byp Gnd R C nf C nf R R C nf R R VR POT VR POT CW CW MCLK R JP Jumper_pin JP Jumper_pin PS C uf V R Y SMHY-.MHz lk En Vcc Gnd Out.MHz CLKM C uf V C nf U LTEMS- CLKM Y C C C R U CWX-.M nf nf uf V In C Out LTEMS-. nc R Vcc Snse En Out In C Byp nc Gnd Out Snse nc nf Gnd En C.MHz C Byp nc R nf nf Gnd En B B R R VR POT R VR POT CW CW X Test Point U LTEMS-. R CMREFL In X Mount Hole nc nc En Out Snse Byp Gnd C nf C uf V R K R K R C uf V C nf X Mount Hole X Mount Hole X Mount Hole X Mount Hole X Mount Hole R X C A A R Test Point D D uf V CMREFR Arda Technologies, Inc. Size Document Number Rev B AT Date: Tuesday, December, Sheet of LED GREEN SML-LXGC-TR SML-LXGC-TR R C uf V C nf

19 R R R D D C uf V C uf V C nf XO_K_EN R k C uf V C nf EXTWC_EN C nf D U SNAHCTGDBVR CLK- CLK- EN XO_K_EN C nf U SNAHCGDBVR CLK CLK_BNC GND U XO U HCTAPW R DEMOUT C INH SIGIN R R R PCOUT/PCPOUT PCOUT R k R C.uF R k C uf OOUT CA CB COMPIN RB C C C C R nf nf PLL_MCLK k C R R uf U C CLR R CLR D D CLK C CLK PRE uf V PRE Q R Q Q U k Q GND SNAHCTGDBVR SNAHCPWR OIN GND GND EXTWC_EN XO_K_EN C nf C nf R D U EN XO_K_EN CLK B B GND U XO EXTWC_EN C uf V C nf C nf R SNAHCTGDBVR LRCK U SNAHCTGDBVR EXTWC_EN XO_K_EN A A XO_K_EN Arda Technologies, Inc Size Document Number Rev B AT. U SNAHCGDBVR R k R R k SW DIPswitch- Date: Tuesday, December, Sheet of