Ordering Information Base Part Number Package Type Standard Pack Complete Part Number 500 I D = 100A T J = 125 C 200 I D,

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1 R DS(on), Drain-to -Source On Resistance (m Ω) I D, Drain Current (A) StrongIRFET TM Applications l Brushed Motor drive applications l BLDC Motor drive applications l Battery powered circuits l Half-bridge and full-bridge topologies l Synchronous rectifier applications l Resonant mode power supplies l OR-ing and redundant power switches l DC/DC and AC/DC converters l DC/AC Inverters G D S V DSS HEXFET Power MOSFET R DS(on) typ. max. I D (Silicon Limited) I D (Package Limited) 40V 1.0mΩ 1.3mΩ 409Ac 195A D Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l Lead-Free l RoHS Compliant, Halogen-Free* S D G TO-220AB G D S Gate Drain Source Ordering Information Base Part Number Package Type Standard Pack Complete Part Number Form Quantity TO-220 Tube I D = A 400 Limited By Package T J = 125 C T C, Case Temperature ( C) V GS, Gate -to -Source Voltage (V) Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature International Rectifier Submit Datasheet Feedback February 19, 2015

2 Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 409c I T C = C Continuous Drain Current, V V (Silicon Limited) 289c I T C = 25 C Continuous Drain Current, V V (Wire Bond Limited) 195 A I DM Pulsed Drain Current d 1524 P C = 25 C Maximum Power Dissipation 375 W Linear Derating Factor 2.5 W/ C V GS Gate-to-Source Voltage ± 20 V T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw 300 lbfx in (1.1Nx m) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 760 mj E AS (Thermally limited) Single Pulse Avalanche Energy k 1452 I AR Avalanche Currentd See Fig. 14, 15, 22a, 22b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case j 0.40 R θcs Case-to-Sink, Flat Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 40 V V GS = 0V, I D = 250μA ΔV (BR)DSS /ΔT J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1.0mAd R DS(on) Static Drain-to-Source On-Resistance mω 1.2 V GS = V, I D = A g V GS = 6.0V, I D = 50A g V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250μA I DSS Drain-to-Source Leakage Current 1.0 μa V DS = 40V, V GS = 0V 150 V DS = 40V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage na V GS = 20V Gate-to-Source Reverse Leakage - V GS = -20V R G Internal Gate Resistance 2.1 Ω Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L = 0.15mH R G = 50Ω, I AS = A, V GS =V. I SD A, di/dt 990A/μs, V DD V (BR)DSS, T J 175 C. Pulse width 400μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from 0 to 80% V DSS. ˆ R θ is measured at T J approximately 90 C.. Limited by T Jmax, starting, L = 1mH, R G = 50Ω, I AS = 54A, V GS =V. * Halogen -Free since April 30,

3 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 150 S Q g Total Gate Charge nc Q gs Gate-to-Source Charge 77 Q gd Gate-to-Drain ("Miller") Charge 98 Q sync Total Gate Charge Sync. (Q g - Q gd ) 202 t d(on) Turn-On Delay Time 32 ns t r Rise Time 5 t d(off) Turn-Off Delay Time 160 t f Fall Time C iss Input Capacitance pf C oss Output Capacitance 2130 C rss Reverse Transfer Capacitance 1460 C oss eff. (ER) Effective Output Capacitance (Energy Related) i 2605 C oss eff. (TR) Effective Output Capacitance (Time Related)h 2920 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 394c A (Body Diode) I SM Pulsed Source Current 1576 A (Body Diode)d V SD Diode Forward Voltage V dv/dt Peak Diode Recovery f 2.7 V/ns Conditions V DS = V, I D = A I D = A V DS =20V V GS = V g V DD = 20V I D = 30A R G = 2.7Ω V GS = V g V GS = 0V V DS = 25V ƒ = 1.0 MHz V GS = 0V, V DS = 0V to 32V i V GS = 0V, V DS = 0V to 32V h Conditions MOSFET symbol showing the integral reverse p-n junction diode. D G S, I S = A, V GS = 0V g T J = 175 C, I S = A, V DS = 40V t rr Reverse Recovery Time 52 ns V R = 34V, 52 T J = 125 C I F = A Q rr Reverse Recovery Charge 97 nc di/dt = A/μs g 97 T J = 125 C I RRM Reverse Recovery Current 2.3 A 3

4 C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 4.8V BOTTOM 4.5V 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 4.8V BOTTOM 4.5V 4.5V 4.5V 60μs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics 60μs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics I D = A V GS = V T J = 175 C V DS = 25V 60μs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig 5. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 6. Normalized On-Resistance vs. Temperature 000 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = A V DS = 32V V DS = 20V 00 C iss C oss C rss V DS, Drain-to-Source Voltage (V) Fig 7. Typical Capacitance vs. Drain-to-Source Voltage Q G, Total Gate Charge (nc) Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage 4

5 R DS (on), Drain-to -Source On Resistance ( mω) V (BR)DSS, Drain-to-Source Breakdown Voltage (V) Energy (μj) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) 0 00 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C 0 1msec μsec Limited by package msec V GS = 0V V SD, Source-to-Drain Voltage (V) Fig 9. Typical Source-Drain Diode Forward Voltage Id = 1.0mA 1 Tc = 25 C DC Tj = 175 C Single Pulse V DS, Drain-toSource Voltage (V) Fig. Maximum Safe Operating Area 2.5 V DS = 0V to 32V T J, Temperature ( C ) Fig 11. Drain-to-Source Breakdown Voltage V DS, Drain-to-Source Voltage (V) Fig 12. Typical C OSS Stored Energy V GS = 5.5V V GS = 6.0V V GS = 7.0V V GS = 8.0V V GS =V I D, Drain Current (A) Fig 13. Typical On-Resistance vs. Drain Current 5

6 E AR, Avalanche Energy (mj) Avalanche Current (A) 1 Thermal Response ( Z thjc ) C/W D = E-006 1E t 1, Rectangular Pulse Duration (sec) 0 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤ j = 25 C and Tstart = 150 C E E E E E E-01 tav (sec) Fig 15. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM 1.0% Duty Cycle I D = A Notes on Repetitive Avalanche Curves, Figures 14, 15: (For further info, see AN-5 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 13) Starting T J, Junction Temperature ( C) Fig 16. Maximum Avalanche Energy vs. Temperature P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc I av = 2DT/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av 6

7 Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) I F = 60A 3.5 V R = 34V T J = 125 C 2.5 I D = 250μA I D = 1.0mA I D = 1.0A T J, Temperature ( C ) di F /dt (A/μs) Fig 17. Threshold Voltage vs. Temperature Fig Typical Recovery Current vs. di f /dt 12 I F = A 300 I F = 60A V R = 34V 250 V R = 34V 8 T J = 125 C T J = 125 C di F /dt (A/μs) Fig Typical Recovery Current vs. di f /dt di F /dt (A/μs) Fig Typical Stored Charge vs. di f /dt I F = A V R = 34V T J = 125 C di F /dt (A/μs) Fig Typical Stored Charge vs. di f /dt 7

8 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG V DD Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - Re-Applied Voltage Body Diode Inductor Current Curent Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 15V tp V (BR)DSS V DS L DRIVER R G 20V V GS tp D.U.T IAS 0.01Ω - V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 90% R G - V DD VV GS Pulse Width 1 µs Duty Factor 0.1 % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 50KΩ Vgs 12V.2μF.3μF V GS D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr 8 Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

9 TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at 9

10 Qualification information Qualification level Industrial (per JEDEC JESD47F guidelines) Moisture Sensitivity Level TO-220 Not applicable RoHS compliant Yes Qualification standards can be found at International Rectifier s web site: Applicable version of JEDEC standard at the time of product release. Revision History Date 4/22/2014 2/19/2015 Comment Updated data sheet with new IR corporate template. Updated package outline and part marking on page 9. Added bullet point in the Benefits "RoHS Compliant, Halogen -Free" on page 1. Updated E AS (L =1mH) = 1452mJ on page 2 Updated note 9 Limited by T Jmax, starting, L = 1mH, R G = 50Ω, I AS = 54A, V GS =V. on page 2 IR WORLD HEADQUARTERS: 1 N. Sepulveda Blvd., El Segundo, California 90245, USA To contact International Rectifier, please visit