In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Transcription

1 Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of or use Instead of sales.addresses@ or sales.addresses@ use salesaddresses@nexperia.com ( ) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - NXP N.V. (year). All rights reserved or Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

2 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC File under Integrated Circuits, IC04 January 1995

3 DESCRIPTION The has four independent analogue switches (transmission ). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to V DD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to V SS the switch is disabled and a high impedance between Y and Z is established (OFF condition). Current through a switch will not cause additional V DD current provided the voltage at the terminals of the switch is maintained within the supply voltage range; V DD (V Y, V Z ) V SS. Inputs Y and Z are electrically equivalent terminals. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING E 0 to E 3 Y 0 to Y 3 Z 0 to Z 3 enable inputs input/output terminals input/output terminals P(N): 14-lead DIL; plastic (SOT27-1) D(F): 14-lead DIL; ceramic (cerdip) (SOT73) T(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America APPLICATION INFORMATION Some examples of applications for the are: Signal gating Modulation Demodulation Chopper Fig.3 Schematic diagram (one switch). January

4 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch P max. 100 mw For other RATINGS see Family Specifications DC CHARACTERISTICS T amb =25 C; V SS = 0 V (unless otherwise specified) PARAMETER V DD V SYMBOL TYP. MAX. UNIT CONDITIONS Ω E n at V IH ; V is = 0 to V DD ; see Fig.4 ON resistance 10 R ON Ω Ω Ω E n at V IH ; V is =V SS ; see Fig.4 ON resistance 10 R ON Ω Ω Ω E n at V IH ; V is =V DD ; see Fig.4 ON resistance 10 R ON Ω Ω ON resistance Ω E n at V IH ; V is = 0 to V DD ; see Fig.4 between any two 10 R ON 15 Ω channels Ω PARAMETER V DD V SYMBOL T amb ( C) UNIT CONDITION MIN. MAX. MIN. MAX. MIN. MAX. Quiescent 5 1,0 1,0 7,5 µa V SS = 0; all valid device 10 I DD 2,0 2,0 15,0 µa input combinations; V I =V SS or V current 15 4,0 4,0 30,0 µa DD Input leakage ± I IN current at E n na En at V SS or V DD OFF-state leakage 5 na E n at V IL ; current, any 10 I OZ na V is =V SS or V DD ; V os =V DD or V channel OFF na SS E n input 5 1,5 1,5 1,5 V switch OFF; see voltage LOW 10 V IL 3,0 3,0 3,0 V Fig.9 for I OZ 15 4,0 4,0 4,0 V E n input 5 3,5 3,5 3,5 V low-impedance voltage HIGH 10 V IH 7,0 7,0 7,0 V between Y and Z (ON condition) 15 11,0 11,0 11,0 V see R ON switch January

5 Fig.4 Test set-up for measuring R ON. E n > V IH I is = 100 µa V SS =0 V Fig.5 Typical R ON as a function of input voltage. January

6 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V SYMBOL TYP. MAX. Propagation delays V is V os ns HIGH to LOW 10 t PHL ns ns ns LOW to HIGH 10 t PLH ns ns Output disable times E n V os ns HIGH 10 t PHZ ns ns ns LOW 10 t PLZ ns ns Output enable times E n V os ns HIGH 10 t PZH ns ns ns LOW 10 t PZL ns ns Distortion, sine-wave 5 % response 10 0,08 % 15 0,04 % Crosstalk between 5 MHz any two channels 10 1 MHz 15 MHz Crosstalk; enable 5 mv input to output mv 15 mv OFF-state 5 MHz feed-through 10 1 MHz 15 MHz ON-state frequency 5 MHz response MHz 15 MHz note 1 note 1 note 2 note 2 note 2 note 2 note 3 note 4 note 5 note 6 note 7 January

7 Notes V is is the input voltage at a Y or Z terminal, whichever is assigned as input. V os is the output voltage at a Y or Z terminal, whichever is assigned as output. 1. R L = 10 kω to V SS ; C L = 50 pf to V SS ; E n =V DD ; V is =V DD (square-wave); see Figs 6 and R L = 10 kω; C L = 50 pf to V SS ; E n =V DD (square-wave); V is =V DD and R L to V SS for t PHZ and t PZH ; V is =V SS and R L to V DD for t PLZ and t PZL ; see Figs 6 and R L = 10 kω; C L = 15 pf; E n =V DD ; V is = 1 2 V DD(p-p) (sine-wave, symmetrical about 1 2 V DD ); f is = 1 khz; see Fig R L =1 kω; V is = 1 2 V DD(p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os (B) 50 db; E V is (A) = n (A) = V SS ; En (B) = V DD ; see Fig R L = 10 kω to V SS ; C L = 15 pf to V SS ; E n =V DD (square-wave); crosstalk is V os (peak value); see Fig R L =1 kω; C L = 5 pf; E n =V SS ;V is = 1 2 V DD(p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os = 50 db; see Fig. 7. V is 7. R L =1 kω; C L = 5 pf; E n =V DD ;V is = 1 2 V DD(p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os = 3 db; see Fig. 7. V is V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) (1) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) Note 1. All enable inputs switching. January

8 Fig.6 Fig.7 Fig.8 Fig.9 January

9 Fig.10 Waveforms showing propagation delays from V is to V os. (1) V is at V DD (2) V is at V SS Fig.11 Waveforms showing output disable and enable times. January