A PFC power supply with minimized energy storage components and a new control technique for cascaded SMPS. Damien F. Frost

Transcription

1 A PFC power supply with minimized energy storage components and a new control technique for cascaded SMPS by Damien F. Frost A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 009 by Damien F. Frost

2 Abstract A PFC power supply with minimized energy storage components and a new control technique for cascaded SMPS Damien F. Frost Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 009 This Master of Applied Science thesis proposes a new design of low power, power factor corrected (PFC), power supplies. By lifting the hold up time restriction for devices that have a battery built in, the energy storage elements of the converter can be reduced, permitting a small and inexpensive power converter to be built. In addition, a new control technique for controlling cascaded converters is presented, named duty mode control (DMC). Its advantages are shown through simulations. The system was proven using a prototype developed in the laboratory designed for a universal ac input voltage (85-65V RMS at 50-60Hz)anda40W output at V. It consisted of two interleaved phases sensed and digitally controlled on the isolated side of the converter. The prototype was able to achieve a power factor of greater than 0.98 for all operating conditions, and input harmonic current distortion well below any set of standards. ii

3 To my parents, Sam and Geraldine Frost. iii

4 Acknowledgements I would like to express my gratitude to both of my supervising professors, Professor Peter Lehn and Professor Aleksandar Prodić, who gave me both the opportunity to study with them and this exciting project for my thesis. Furthermore, their guidance and support were invaluable assets that led to the completion of this work. I also would like to thank all of the fellow students in the SMPS laboratory for their insight and patience, especially Zdravko Lukić and Amir Parayandeh. I would also like to acknowledge all of my friends and the members of The Attic for their constant support and for all of the great memories I have from my graduate studies. Finally, I would like to thank my family for their unconditional love and support throughout all of my studies. iv

5 Contents Introduction and Background. Background Simple active PFCs Motivation Literary review PFCs Control of cascaded SMPS Objectives Proposed System 0. Energy storage in PFCs New PFC design Duty mode control Centralized digital control Capacitor Ripple Voltage and Steady State Analysis 5 3. Limitations on the capacitor voltage ripple Flyback in steady state Differential equations of the converter The flyback converter in steady state Control for unity power factor operation v

6 3..4 A comment on theory System Modeling and Control 5 4. Duty mode control (DMC) Advantages of DMC Two stage DMC example DMC model with downstream PID compensator State space model Control to output transfer function DMC vs. conventional control System models Lossy buck converter in state space Lossy flyback converter in state space Additional parts of the system model Complete system model in state space Controller design Voltage controller design for buck converter Current controller design for the flyback converter DMC controller design for the flyback converter Experimental Results 6 5. Flyback component selection Flyback transformer Main energy storage capacitor Converter specifications Steady state operation Power factor and THD Transient response vi

7 5.6 Energy storage comparison Limitations of the proposed system Current measurement Loss in main energy storage capacitor Hold up time Conclusions and Future Work Conclusions Future work PFC supplies with minimized energy storage DMC On chip integration Appendices 80 A Circuit Schematic 80 A. Circuit schematics A. Bill of materials B Measurement Devices 89 Bibliography 94 vii

8 List of Tables 3. Parameters of the flyback converter simulation Parameters used to compare DMC and conventional control Parameters used in the buck converter developed in lab Parameters used in the flyback converter developed in lab Parameters from the laboratory used in the complete system model Technical specifications for the main energy storage capacitor Technical specifications of the main energy storage capacitor Performance specifications of the converter designed in the laboratory Technical specifications of each phase of the converter Voltage ripple on the main energy storage capacitor Energy storage comparison B. Table of measurement devices used viii

9 List of Figures. The traditional diode bridge rectifier used as an ac to dc power supply.. 3. The voltage and current waveforms of the diode bridge rectifier Topology of the flyback converter The averaged switch model of the flyback converter in DCM A typical two stage PFC supply Topology of the proposed system Block diagram depicting DMC The ripple current in the capacitor The ac power absorbed by the storage capacitor The flyback converter with the main switch, Q, on The flyback converter with the main switch, Q, off Flyback operating at unity power factor simulation Block diagram depicting DMC Converter used to illustrate DMC The linearized model of the buck converter with losses Complete model of two converters in series to show the properties of DMC Transfer functions of DMC vs. conventional control Step response simulation of conventional control vs. DMC The buck converter with losses and switching network shown ix

10 4.8 The flyback converter with losses A PI controller in state space The complete small signal model of the system Bode plot of G B vc (s) Compensated bode plot of G B vc (s) Bode plot of G A ic (s) Compensated bode plot of G A ic (s) Bode plot of DMC transfer function Compensated bode plot of DMC transfer function input voltage and current of prototype Voltage of energy storage capacitor while operating at full load Comparing the theoretical and experimental duty cycles The measured power factor of the converter developed in the laboratory The THD of the prototype converter Harmonic current emissions from the prototype vs. IEC Transient response of the prototype - load increase Transient response of the prototype - load decrease Current sensing waveform The CBEMA Curve [] Hold up time of the prototype A. Overall circuit schematic of the converter built in the laboratory A. Circuit schematic for the ADCs, ADC circuit.schdoc A.3 Circuit schematic for the linear regulators, LinearRegulator.SchDoc A.4 Circuit schematic for the non inverting operational amplifier A.5 Circuit schematic for the power stage, PowerStage.SchDoc A.6 Circuit schematic of the gate drivers, GateDriver.SchDoc x

11 A.7 Circuit schematic for the inverting operational amplifiers A.8 Bill of materials for one phase of the power stage xi

12 List of Abbreviations ac ADC CBEMA CCM dc DCM DMC DPWM ESR FFT FPGA IC ICS IEC IEEE IT ITIC PF PFC PI PID RMS SMPS THD Alternating Current Analog to Digital Converter Computer and Business Equipment Manufacturers Association Continuous Conduction Mode Direct Current Discontinuous Conduction Mode Duty Mode Control Digital Pulse Width Modulator Equivalent Series Resistance Fast Fourier Transform Field Programmable Gate Array Integrated Circuit Input Current Shaper International Electrotechnical Commission Institute of Electrical and Electronics Engineers Information Technology Information Technology Information Council Power Factor Power Factor Correction Proportional Integral Proportional Integral Differential Root Mean Square Switch Mode Power Supply Total Harmonic Distortion xii

13 Notation X (t), x (t) time dependent quantity x (t) Ts time averaged quantity over period Ts ˆx small signal X dc signal or constant quantity X constant matrix or vector x vector of small signals X (s) continuous time transfer function x [n] discrete time quantity xiii

14 Chapter Introduction and Background This chapter introduces the main topic of this work, low power, power factor corrected (PFC), power supplies. In this area, two main foci will be addressed. First, the reduction of the size of energy storage elements in PFC supplies and second, a new control method to control cascaded switch-mode power supplies. The size of energy storage elements in the converter is reduced by allowing a large ripple voltage to appear on the main energy storage capacitor, greatly reducing the size of this component. This ripple voltage is as much as 37% of the nominal value. The new control method proposed utilizes the duty cycle of the downstream converter to control the output voltage of the upstream stage. This reduces the number of sensors required by one, and also provides a better transient response. First a brief introduction to power factor correction is presented, followed by the motivation of this work. A review of existing solutions is then presented and the chapter concludes with the goals of this thesis. The rest of the work is organized as follows: Chapter contains a description of the proposed system and describes its novel aspects. Chapter 3 demonstrates how to use a capacitor in a PFC to its designed limits,

15 Chapter. Introduction and Background utilizing its full energy storage capabilities. Chapter 4 models the proposed system in state space and introduces a new control method for cascaded converters, duty mode control (DMC). From this model, controllers are designed for the proposed system that are verified in the laboratory. Chapter 5 shows the results from the prototype converter built in the laboratory. Chapter 6 summarizes the results from this work and suggests future directions that can be investigated.. Background Power factor is a measure of how effectively energy is transmitted between a source and a load in a system. From [] there are two different definitions for power factor and these are shown in Equations (.) and (.). Equation (.) calculates the power factor in the presence of harmonics in either the supply voltage or supply current. Equation (.) calculates the power factor assuming the voltage and current are purely sinusoidal and is only a function of the angle between the voltage phasor and current phasor, φ. (power factor) = (average power) (rms voltage) (rms current) (.) (power factor) =cos(φ) (.) For this work, Equation (.) will be used to calculate the power factor. Both equations stipulate that the power factor is a value between zero and one, and in order to have the most efficient energy transmitting network, a power factor of one is necessary. However, this only occurs when the load is a perfect resistor. Other loads such as reactive and non linear loads introduce imaginary power and distortion into the system and will cause current to flow from the source to the load and back again without doing any real

16 Chapter. Introduction and Background 3 Figure.: The traditional diode bridge rectifier used as an ac to dc power supply. Source Voltage Voltage Time (s) Source Current Current Time (s) Figure.: The voltage and current waveforms of the diode bridge rectifier of Figure. work. This additional current requires all the components in the system to have higher ratings and it also contributes to the heating of power transformers and transmission lines. Therefore, it would be ideal if all loads had a power factor of one. For this reason, many high power, and now low power, loads are required to meet government regulations on current harmonic limits through standards set by the institute of Electrical and Electronics Engineers (IEEE) and the International Electrotechnical Commission (IEC). An example of such a non linear load is the traditional diode bridge rectifier, shown in Figure., used as an ac to dc power supply. This circuit is highly non linear and the current and voltage waveforms are shown in Figure.. The power factor of this circuit is typically around 0.55 to 0.65 []. The power factor of the diode bridge rectifier circuit can be improved either passively or actively. A passive solution is to add a filter to the input of the diode bridge. This is rarely done in practice, as the filter required would be large, expensive and would only work for a certain input frequency. The second way to improve the power factor of this circuit is to add a switching network after the diode bridge to regulate the input current.

17 Chapter. Introduction and Background 4 :n D C R Q D Figure.3: Topology of the flyback converter. p(t) T L D n T C R D Figure.4: The averaged switch model of the flyback converter in DCM. This is commonly implemented and is discussed in greater detail in the next section... Simple active PFCs Simple active PFCs are circuits that emulate an ideal resistance when attached to an ac system. The analysis of power converters based on average switch modeling [], shows that many common topologies are natural PFCs when operated in the discontinuous conduction mode (DCM), without additional control. These converters include the buckboost, flyback, SEPIC and Ćuk []. Therefore, using one of these converters as a PFC is a simple choice. Figure.4 shows the averaged switch model of the flyback converter of Figure.3. As shown, the input port of the converter is modeled as a lossless resistor whose power is transferred over to the power source, connecting the load. The duty cycle of the boost converter simply changes the value of the loss-less resistor to either increase or decrease the input, and by consequence the output, power. Although theoretically very effective, in a practical implementation of this system an

18 Chapter. Introduction and Background 5 electromagnetic interference (EMI) filter will be required to filter out the discontinuous input current.. Motivation Until recently, power factor correction has been limited to high power loads, through standards like IEEE59 [3]. However in 00 the European Union adopted the International Electro-Technical Commission s IEC standard for electrical equipment which puts harmonic current limits on all devices that draw up to 6A and consume more than 75W in a 0Vacsystem [4]. Since then, Britain, China and Japan have adopted similar standards [5]. These standards have yet to be adopted for North America, however one can assume that they will be at least as strict as the IEC in the near future. The inconsistency in restrictions is due to the differences between the European and North American distribution systems. North American distribution systems are predominantly a wye-wye system and therefore, are more susceptible to triplen harmonics (3rd, 9th, 5th, etc.). As a result, any limitations that might be imposed in North America will most likely be very different from those set in the IEC standard [6]. Furthermore, the restrictions are being applied to lower power devices most likely because there are an increasing number of highly non-linear loads being used by consumers everyday, as seen in Canada [7], [8]. If all of the ac-dc power supplies found in an average household were implemented with the diode bridge rectifier of Figure., the spikes in the current generated by these circuits would not go unnoticed. Finally, there are significant indications that there will be a market for inexpensive, low power, PFC supplies. This work will fill this area by proposing a solution that provides power factor correction with minimized energy storage elements, thus producing lower cost, more compact power supplies.

19 Chapter. Introduction and Background 6.3 Literary review.3. PFCs As shown in [9], PFC converters can be categorized into two main groups: sinusoidal line current and non-sinusoidal line current. Converters with a non-sinusoidal line current are the converters that meet harmonic specifications like the IEC , however they may not be able to meet future harmonics specifications. Therefore, the discussion here focuses on sinusoidal line current PFC converters..3.. The boost PFC The boost topology operating in discontinuous conduction mode (DCM) is one of the most natural PFC topologies. However, it has a few drawbacks, two of which are outlined here. First, the energy storage capacitor must be able to handle voltages above the peak line voltage of any input. Second, the input current harmonics are fairly high because the current goes to zero after every switching cycle, putting more stress on the input filter of the converter [0]. A reduction of voltage stresses on the main energy storage capacitor of the boost converter has been achieved through a modified boost topology as presented in []. The topology is called The series inductance interval and it is able to achieve a low voltage on the storage capacitor as well as a low voltage swing depending on the input voltage. A more detailed analysis of this converter and an improved version is presented in []. Many solutions to reduce the input current switching harmonics have also been proposed and a common solution is to interleave many boost cells into a converter. By using two cells one can reduce the switching harmonics by half [0] or eliminate them completely with a slight modification to the boost topology as demonstrated in [3]. Furthermore, [4] provides a solution to optimize the number of boost cells to use based on the design specifications of the converter.

20 Chapter. Introduction and Background 7 Many variations of the topology have been developed in order to improve its performance. Reference [5] provides a good survey of single stage PFC circuits with a boost type input current shaper (ICS). In this review, many different topologies are examined and are grouped into two categories of converters: converters with a two terminal ICS cell and converters with a three terminal ICS cell. These two categories of ICSs are also consistent with grouping of boost ICSs in [6]..3.. The flyback PFC As shown in [7] and [8], the flyback converter is one of the best topologies that is able to achieve near unity power factor as well as direct power transfer to the load. Furthermore, in comparison to the PFC boost, the flyback converter electrically isolates the ac and dc sides. However, just like the boost converter, much research has been published analyzing its performance [9], [0] and improving aspects of the converter. The flyback has also been combined with other topologies to create novel single stage converters, as mentioned in [5] Digital control of PFC converters Digital control of converters is becoming the preferred option for designers because it allows for more flexible designs, shorter development times, the elimination of tuning discrete components and increased reliability []. There have been many works published on the digital control of PFC converters like the one shown in []. Therefore the digital control of PFC converters has been shown to be successful. To completely design a digital controller, an extremely useful resource is [3]. In this work the authors give a complete overview of designing a digital controller. A good complement to this work is [4], where three different digital control design techniques are compared experimentally.

21 Chapter. Introduction and Background Reducing the size of energy storage components In the literature, all of the PFC topologies are designed such that they meet the hold up time standard set by the Information Technology Industry Council (ITIC) []. However, this hold up time was designed for devices that do not have a battery built in. Devices that would benefit from a smaller PFC supply are those designed for portability, for example laptops and battery chargers. Furthermore, one can expect these devices to be more prevalent in the future considering for the first time in 008, worldwide laptop sales have outpaced those of desktop sales [5]. Devices such as laptops and battery chargers are low power electronics that will likely have to abide by input current harmonic limits set by governments. They are also devices that can withstand a temporary fault in the power system quite easily because battery charging can be interrupted without consequence, just as it can in a laptop since it contains a battery built in. Furthermore, smaller and lighter power supplies are more desirable and usually must be taken along with the device they power..3. Control of cascaded SMPS The discussion around the control and stability analysis of cascaded switch mode power supplies (SMPS) has been largely limited to defining impedance criteria which the power supplies must meet in order to preserve stability [6], [7], [8]..4 Objectives The main goal of this work is to create a prototype of a low power, PFC supply, suitable for portable electronic applications where the hold up time is not a necessity. The objectives of this work are as follows: Reduce the size of energy storage components in the converter by increasing the

22 Chapter. Introduction and Background 9 switching frequency, allowing a large ripple voltage on the main energy storage capacitor and creating an integrated design of the system. Introduce a new method for controlling cascaded SMPS and combine all the controllers of the system into a single FPGA. Exploit low cost and low voltage components by appropriately designing the power stages.

23 Chapter Proposed System This chapter introduces the proposed system. It consists of two parallel converter systems operated with interleaved switching, to reduce input current switching harmonics. These are referred to as interleaved phases. Each phase is rated for a 0W load and consists of a flyback converter connected in series with a buck converter. The flyback acts as a power factor corrector in the system, and its output capacitor is the main energy storage component of the system. This capacitor is targeted for size reduction. As a consequence, a large ripple voltage on this capacitor exists with a nominal value around 50Vdc.The buck converter acts as a constant power load on the flyback converter, outputting a regulated Vdc. The total output power of the system is rated for a 40W load. The system was designed for low power PFC applications where hold up time is not critical. However, being an interleaved system, more phases could be added to increase the output power to the desired amount. The rest of the chapter will introduce the main problem with unity power factor ac/dc conversion, followed by the proposed converter topology. It will conclude by introducing a novel control method for controlling cascaded converters. 0

24 Chapter. Proposed System. Energy storage in PFCs One of the largest problems PFC supplies face when powering a dc load is dealing with the second harmonic power ripple. The problem may be understood by studying the power entering a PFC, as shown in Equation (.) below. P ac (t) =V g cos (ωt) I g cos (ωt) = V gi g ( + cos (ωt)) (.) From this equation it is clear that the input power into a PFC supply contains a second harmonic ripple component. The output dc power is defined by the average value of Equation (.) over a period, (V g I g ) /. During times when the input power is less than the output power, the PFC must have sufficient energy storage to supply the dc load. Providing this power is conventionally done with a large capacitor, and in the case of a boost converter acting as a PFC operating in CCM, a large high voltage capacitor. A capacitor of this type is very large, bulky and expensive. Moreover, its energy storage capabilities are under utilized. In the proposed solution the capacitor will be reduced in size so as to maximize the use of its energy storage capabilities. As a consequence, there will be a large ripple voltage on the main energy storage capacitor of the system at twice the frequency of the line voltage and this will introduce control challenges that have not previously been addressed.. New PFC design Traditional PFC supplies comprise of two stages [9] and require sensing and control on the non-isolated, ac side as well as the isolated side for any downstream converter. An example is shown in Figure.. The design of these power supplies is such that the output voltage of the PFC, the voltage on capacitor C in Figure., remains relatively constant. This requires a large,

25 Chapter. Proposed System I g T Q Vg D C Q3 C Load Q Main Energy Storage Capacitor PFC Controller Voltage Controller Figure.: A typical two stage PFC supply. expensive, and in the case of boost converter acting as a PFC in CCM, a high voltage capacitor as the main storage element. The proposed PFC design eliminates these requirements on the main energy storage capacitor. The topology of the proposed system was chosen such that a few basic criteria could be met: Galvanic isolation Universal input voltage (85-65V rms at 50 60Hz) Convenient output voltage for household electronics (V ) In addition, the topology was chosen such that other novel criteria could be met, which would also reduce the cost and size of the converter: A small, low voltage energy storage capacitor A single, centralized controller Reduced voltages in the converter Taking these points into account, a conventional topology of a series connection of a flyback and buck converter was chosen as shown in Figure.. Both converters operate in continuous conduction mode (CCM) to reduce peak currents in the system. To decrease the switching harmonics, an interleaved, two phase PFC stage was implemented.

26 Chapter. Proposed System 3 I g :0.3 Q V g D C Q 3 C Load Q Main Energy Storage Capacitor PFC and Voltage Controller Figure.: Topology of the proposed system. The turns ratio on the flyback transformer was chosen to provide a step down in voltage. This allows the main energy storage capacitor of the system, C in Figure., to be an inexpensive, low voltage component. The turns ratio chosen for the system was :0.3. Isolation is maintained through the use of a single optical coupler to send a gating pulse to the main switch, Q. Finally, a significant innovation in the proposed converter is the location of input current and voltage sensors. Both sensors are placed on the secondary side of the transformer, allowing all sensing and control to be done on this side. Voltage sensing is accomplished when the main switch Q is in the on state. During this time, the voltage across the primary side of the transformer is reflected to the secondary side and thus can be read by a sensor. Current sensing is accomplished when the main switch turns off, forcing the magnetizing current of the flyback transformer to flow through the secondary side, and therefore through the sensing resistor. In this way the controller can be combined into a single chip, as shown in Figure.. As shown in Chapter 4, this will allow us to further reduce the size of the energy storage capacitor.

27 Chapter. Proposed System 4.3 Duty mode control Combining both controllers for the PFC stage and the downstream converter on a single chip allows a novel control technique to be developed, which will be referred to as duty mode control (DMC). Similar to how voltage and current mode control operate, the voltage on the main storage capacitor will be controlled such that the duty cycle of the downstream converter is held at a reference value. System dynamic studies presented in Chapter 4 show that this control method allows us to further reduce the size of the main energy storage capacitor C. A simplified block diagram of the controller is shown in Figure.3. I g :0.3 Q Vg D C Q3 C Load Q PWM PWM Flyback Current Compensator Duty Mode Controller Buck Voltage Compensator V ref Dref Centralized Digital Controller Figure.3: Block diagram depicting DMC..4 Centralized digital control The proposed centralized control method allows the entire controller to be implemented on a single field programmable gate array (FPGA). Digital control permits the use of control techniques that would be difficult or impossible to implement with standard analog control. These include DMC and a self adjusting dead zone controller as described in [30].

28 Chapter 3 Capacitor Ripple Voltage and Steady State Analysis This chapter begins by deriving an equation that allows one to use an energy storage capacitor to its designed limits. Following this, the steady state analysis of the flyback converter powering a dc load at unity power factor is carried out. In particular, the consequences of allowing a large ripple voltage on its capacitor are studied. 3. Limitations on the capacitor voltage ripple First, an expression for the ripple voltage on the capacitor is derived based on the rated ripple current the capacitor can handle, I r, which is measured in amps rms. Figure 3. shows the ripple current in the capacitor. The shaded region is the amount of charge, ΔQ, that is deposited onto the capacitor when the current is positive. This charge is added to the charge residing on the capacitor when it is at its lowest voltage, V MIN. Therefore the maximum voltage on the capacitor is given by Equation (3.): V MAX = Q MIN +ΔQ C (3.) 5

29 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 6 Δ Q Current (A) Time (s) Figure 3.: The ripple current in the capacitor. The shaded region represents the charge deposited on the capacitor after t =0. where Q MIN is the charge on the capacitor initially at t =0andC is the capacitance. Defining ΔV r = V MAX V MIN we find that: ΔV r = ΔQ C. (3.) Integrating the current over one half cycle to obtain ΔQ yields: ΔQ = Ir πf r, (3.3) where f r is the frequency of the second harmonic of the system. Substituting Equation (3.3) into Equation (3.) the peak to peak ripple voltage on the capacitor is obtained in Equation (3.4). ΔV r = Ir πf r C (3.4) Next, in an ideal PFC circuit, the current and voltage waveforms are sinusoidal and in phase with each other. Therefore we can easily obtain an expression for the instantaneous input power:

30 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 7 P in (t) =V g cos (ωt) I g cos (ωt) = V gi g ( + cos (ωt)) (3.5) where ω is the line frequency. Equation (3.5) can be separated into a dc and ac component yielding: P in (t) =P dc + P ac (t) (3.6) where, P dc = V gi g (3.7) and P ac (t) = V gi g cos (ωt) =P dc cos (ωt). (3.8) Assuming that the ac component of the input power is absorbed completely by the storage capacitor, we can determine the ripple on the capacitor that will result in this oscillating power. This assumption is valid as long as the magnetizing inductance and current are small enough such that 0.5L m I m << 0.5C V C. The shaded region in Figure 3. represents the energy absorbed by the capacitor for one half cycle. This absorption of energy will increase the capacitor voltage according to Equation (3.9). Let this energy be called ΔE. ΔE = C ( Vf V ) i (3.9) where V f, V i and C are the final capacitor voltage, initial capacitor voltage and the capacitance, respectively. Integrating the ac power over a half cycle to obtain ΔE yields:

31 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 8 Δ E Power (W) P DC Time (s) Figure 3.: The ac power absorbed by the storage capacitor. The shaded region represents the energy absorbed by the capacitor during one half cycle. ΔE = P dc ω. (3.0) Now substitute Equation (3.0) into Equation (3.9) and let V i = V MAX ΔV r and V f = V MAX : P dc = Cω( ) V MAX ΔV r ΔVr. (3.) Finally substituting Equation (3.4) into Equation (3.) for ΔV r yields the final result: P dc = V MAX I r I r πf r C. (3.) Equation (3.) is an expression for the maximum dc power one can draw from an ac source at unity power factor while effectively filtering out the ac ripple power and using the capacitor to its designed limits.

32 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 9 3. Flyback in steady state This section goes through the analysis of the flyback converter, which is the first stage in each phase. This converter will be considered in steady state when it provides constant power for a dc load at unity power factor. First, the time averaged differential equations for the converter are found and a solution for the duty cycle is solved for. 3.. Differential equations of the converter To find the time averaged differential equations of the converter in CCM, the converter is analyzed in its two possible states, as shown in Figures 3.3 and 3.4. ig :n V g im L m D i c C V i l Q Figure 3.3: The flyback converter with the main switch, Q,on. ig :n V g im L m D i c C V i l Q Figure 3.4: The flyback converter with the main switch, Q,off. When the transistor is on (depicted as an ideal switch Q in the figure) the voltage across the magnetizing inductance is v g and its current is i g. The output capacitor current is simply the load current, i l. When the transistor is off, the diode (ideal switch D in the figure) conducts and the voltage across the magnetizing inductance becomes v/n. The

33 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 0 output capacitor current is the difference in the current in the magnetizing inductance reflected to the secondary side minus the load current, i m /n i l. The differential equations representing the system become Equations (3.3) - (3.5). L di m (t) v g (t) = dt v(t) n dv (t) i l (t) C = dt i m(t) i n l (t) i m (t) i g (t) = 0 0 <t d (t) T sw d (t) T sw <t T sw (3.3) 0 <t d (t) T sw d (t) T sw <t T sw (3.4) 0 <t d (t) T sw d (t) T sw <t T sw (3.5) Averaging these equations over one period yields the large signal time averaged nonlinear differential equations of the flyback converter, shown below. L d i m (t) Ts dt C d v (t) Ts dt = d (t) v g (t) Ts ( d (t)) v (t) Ts n (3.6) =( d (t)) i m (t) Ts i l (t) n Ts (3.7) i g (t) Ts = d (t) i m (t) Ts (3.8) 3.. The flyback converter in steady state To obtain the equations for the steady state operation of the flyback converter in CCM, the small ripple approximation can be applied to Equation (3.6) and the principle of charge balance to Equation (3.7). This yields the following relationships:

34 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis V D = n V g ( D), (3.9) I M = ni l ( D). (3.0) Equation (3.9) can be solved for the duty cycle: D = V nv g + V. (3.) 3..3 Control for unity power factor operation The flyback converter will operate with unity power factor when the input current is in phase with the input voltage. The duty cycle of the converter can be solved for using this constraint Output voltage of the flyback At unity power factor, the input power is: ( ) +cos(ωt) P in (t) =V g I g. (3.) Assuming that the flyback converter is ideal and the downstream converter is powering a dc load, the power delivered by the flyback is the dc component: V g I g /. The second, ac, term is the power that must be absorbed by the filtering elements of the flyback. Additionally by noticing that the capacitor has significantly more energy storage capability than the inductor as shown in Equation (3.3), it will again be assumed that all of the ac power will be absorbed by the capacitor. This is shown in Equation (3.4).

35 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis LIL CV (3.3) v (t) i c (t) = V gi g cos (ωt) (3.4) where i c is the current in the capacitor and can be replaced with the differential equation which governs the behavior of a capacitor as shown in Equation (3.5). v (t) dv (t) dt C = V gi g cos (ωt). (3.5) Equation (3.5) is a separable differential equation and can be solved by integration, resulting in Equation (3.8). Vg I g cos (ωt) v (t) dv = dt (3.6) C v (t) = V gi g sin (ωt) + V 0 (3.7) 4ωC Vg I g sin (ωt) v (t) = + V0 (3.8) ωc where V 0 is the constant of integration and is the voltage of the capacitor at t =0. Equation (3.8) defines the voltage that must exist on the output capacitor of the flyback converter during unity power factor operation. This equation assumes that all the ac power is absorbed by this capacitor and the flyback converter is powering a dc load Duty cycle of the flyback Combining Equation (3.8) and Equation (3.), we can find the duty cycle needed to achieve unity power factor when operating in CCM. The result is shown in Equation (3.9).

36 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 3 D flyback (t) = V gi g sin(ωt) n V g cos (ωt) + + V ωc 0 V gi g sin(ωt) + V ωc 0 (3.9) Using this solution for the duty cycle, the system described by Equations (3.6) - (3.8) was simulated with the parameters shown in Table 3.. Note that a small equivalent series resistance was added to the capacitor for numerical reasons. Table 3.: Parameters used to simulate the flyback converter operating at unity power factor. Parameter Value Units C B μf R ESR 0.05 Ω L B 7.00 μh f line Hz P out 5.00 W The results of the simulation are shown in Figure 3.5 which shows an excellent input current shape and a total harmonic distortion of 5.%, validating the duty cycle of Equation (3.9) A comment on theory The derivation in this section relies on Equation (3.) which was found based on the assumption that the input voltage and output voltage remain constant. However, this equation will hold even though the input and output voltage will vary at twice the line frequency due to the fact that the proposed converter will use a very high switching frequency, at 400kHz. At this time scale, the input and output voltages will appear constant to the controller over each switching cycle.

37 Chapter 3. Capacitor Ripple Voltage and Steady State Analysis 4 Duty Voltage (V) Current (A) Voltage (V) Theoretical flyback duty cycle 0 /0 /60 Time (s) Rectified input voltage /0 /60 Time (s) Rectified input current /0 /60 Time (s) Output voltage /0 /60 Time (s) Figure 3.5: The simulation results of operating the flyback converter with the duty cycle calculated in Equation (3.9).

38 Chapter 4 System Modeling and Control This chapter investigates duty mode control and illustrates its advantages over conventional control methods for cascaded converters. Following this, the proposed system is analyzed dynamically and controllers are designed. Finally, some limitations of the system are presented. 4. Duty mode control (DMC) This section discusses the theory behind DMC. First an intuitive argument for DMC is presented, and then a state space model of a system is derived. Using this model, DMC is compared to conventional voltage control. Figure.3 shows the block diagram of the proposed system with DMC, and it is repeated here in Figure 4. for convenience. 4.. Advantages of DMC DMC control is advantageous in two major ways. Firstly, since the duty cycle of the downstream converter is being controlled instead of the midpoint voltage between the two converters, a voltage sensor is not required. This will reduce the cost and footprint of the converter. 5

39 Chapter 4. System Modeling and Control 6 I g :0.3 Q Vg D C Q3 C Load Q PWM PWM Flyback Current Compensator Duty Mode Controller Buck Voltage Compensator V ref Dref Centralized Digital Controller Figure 4.: Block diagram depicting DMC. Secondly, DMC control allows for smaller energy storage elements to be used. This is shown with control theory later in this chapter. However, to motivate this discussion consider a load step in a system with two converters connected in series. Conventionally, this is the sequence of events during a load step increase:. Load step increase occurs.. Voltage on output capacitor drops. 3. Voltage controller of downstream converter compensates by increasing its duty cycle. 4. Current into the downstream converter increases. 5. Midpoint voltage between converters drops. 6. Voltage controller of upstream converter compensates by increasing the duty cycle. With DMC a similar load step yields this order of events:. Load step increase occurs.. Voltage on output capacitor drops.

40 Chapter 4. System Modeling and Control 7 3. Voltage controller of downstream converter compensates by increasing the duty cycle. 6. Voltage controller of upstream converter compensates by increasing the duty cycle. Therefore, the dynamics of the upstream converter (events 4 and 5) are bypassed. This can be used to help reduce the size of the bulky energy storage capacitor in between the two converters. This is also extremely advantageous because the upstream converter will generally have a slower response than the downstream converter. 4.. Two stage DMC example To simplify the analysis of DMC, a model of two cascaded buck converters is used as shown in Figure 4.. In this model, the transistors are modeled with the same on resistance of R A Q and RB Q for the upstream and downstream converters respectively. This is a valid assumption because in the prototype developed in the laboratory, the same transistor was used for the high and low side and each was driven by the same gate source voltage. The inductors are modeled with internal resistances of RL A and RB L. First, a state space model is derived for one of the buck converters, in this case, the downstream converter. This model is identical to the model for the upstream converter. Using this model and a state space representation of the downstream controller, the complete state space model of the system can be built. Equations (4.) and (4.) show the definition of that state space model that is derived. ẋ B = A B x + B B u B (4.) y B = C B x + E B u B (4.) To derive the state space model, time averaged switch modeling is employed to lin-

41 Chapter 4. System Modeling and Control 8 L A i Switching Network i L B v g A R Q A R Q A R L A C A v A =v g B B B B R Q R L i L B R Q B i C C B v v v B R B Figure 4.: Converter used to illustrate DMC. earize the switching network as described in []. Using the network of Figure 4., the equations for v, v, i and i averaged over one switching period are found, shown in Equations (4.3) - (4.6). v (t) Ts = vg B (t) Ts (4.3) v (t) Ts = d B (t) ( vg B (t) Ts i B L (t) ( TsRQ) B d B (t) )( i B L (t) ) TsRQ B (4.4) i (t) Ts = d B (t) i B L (t) Ts (4.5) i (t) Ts = i B L (t) Ts (4.6) Equation (4.3) and (4.6) are substituted into Equation (4.4) to get a voltage equation in terms of switching network parameters only. Similarly, an equation for the input current is found by dividing Equation (4.5) by (4.6). The results are shown in Equations (4.7) and (4.8). v (t) Ts = d B (t) v (t) Ts i (t) Ts R B Q (4.7) i (t) Ts = d B (t) i (t) Ts (4.8) Perturbing the equations above yields the linearized equations that describe the converter which is used to generate the state space model. To do so, let all the time varying

42 Chapter 4. System Modeling and Control 9 terms be represented as a sum of a dc term and an ac term, as shown in Equation (4.9). The results are shown in Equations (4.0) and (4.). x (t) =X +ˆx (4.9) V +ˆv = D B (V +ˆv )+ ˆd ) B V (I + î RQ B (4.0) ( ) I + î = D B I + î + ˆd B I (4.) A linearized dc and ac model of a lossy buck converter is built using Equations (4.0) and (4.), and is shown in Figure 4.3. B î g dˆ B :D B Vg B L B i ob (t) v gb (t) dˆ B I L B RQ B + RL B i LB (t) C B v B (t) R B Figure 4.3: The linearized model of the buck converter with losses. From Figure 4.3 the small signal state equations for the inductor current and capacitor voltage are derived. Setting all dc sources to zero and noting that at dc, V = V B g,these equations are shown below: L B dîb L dt = DBˆv B g C B dˆvb dt + ˆdV B g î B L ( ) R B Q + RL B ˆv B (4.) = î B L ˆvB R B (4.3) The state space model can be built letting the states, inputs and output be defined as shown in Equations (4.4), (4.5) and (4.6), respectively. Note that there are two outputs of this converter. y B is the output voltage that is required to control the buck

43 Chapter 4. System Modeling and Control 30 converter, and y B is the input current into the buck converter, which is required in the interconnection between this converter and the upstream converter in the final model. The state matrices are shown in Equations (4.7) - (4.0). x B = u B = y B = xb x B u B u B u B 3 yb y B = = = A B = (RB B B = Q +RB L) L B C B D B L B 0 0 î B L ˆv B ˆv B g î B o ˆd B ˆvB î B g V B g L B 0 C B (4.4) = L B C B R B x B ˆd B I B L + îb L DB (4.5) (4.6) (4.7) (4.8) C B = 0 (4.9) D B 0 E B = IL B (4.0) 4..3 DMC model with downstream PID compensator Using the model developed in the previous section and setting all the loss resistances (RQ A, RB Q, RA L, RB L ) to zero, the entire model to analyze DMC can be built. Figure 4.4 shows the lossless model of the system shown in Figure 4. with a PID compensator added to the downstream converter.

44 Chapter 4. System Modeling and Control 3 A vˆg D A dˆ A Vg A A sl A î o A sc vˆ A IL A A î g B vˆg D B dˆ B V g B B sl B sc B vˆ I L B B î g B î o Kp B B vˆref K i B x 5 s K d B s Figure 4.4: Complete model of two converters in series to show the properties of DMC State space model The state space model of the system is built based on the linearized block diagram model of Figure 4.4. The model is defined in Equations (4.) and (4.). ẋ = Ax + Bu (4.) y = C DMC x + E DMC u (4.)

45 Chapter 4. System Modeling and Control 3 where x and u are the inputs and outputs of the system, respectively, defined by: x = x x x 3 x 4 = î A L ˆv A î B L ˆv B (4.3) x 5 x 5 u = u u u 3 u 4 = ˆv g A î B o ˆv ref B ˆd A (4.4) Assuming that the derivative of input u 3 is zero, the state equations can be found and are shown in Equation (4.5). This assumption is valid because input u 3 is the reference signal for the downstream converter and is constant during operation. ẋ = D x + u A Vg L A + u A L A 4 L A x C A + x 3 ( I B L K B d C A C B x D B L B Kd x BV g B 3 x 3 C B u C B x 4 + u 3 C B L B x 4 ( ) DB IL + x BKB p C A 4 C A L B x 5 K B i IB L C A ) + KB p V g B Vg + x BKB i L B 5 L B u K B d IB L C A C B Vg + u BKB d C B L B u 3 I B L KB p C A Kp + u BV g B 3 L B (4.5) For DMC control, the only output that is required is the duty cycle of the downstream converter. Using y to denote the output of this model, it is found from Figure 4.4 to be: y = x 3 K d B C B x 4 K B p + x 5K B i + u K B d C B u 4 K B p (4.6)

46 Chapter 4. System Modeling and Control 33 Using Equations (4.5) and (4.6) the A, B, C DMC and E DMC matrices can be found, shown in Equations (4.7) - (4.30). A = B = 0 0 C A 0 D B L B L A ( ) I B L Kd B DB IL BKB p C A C B C A C ( A ) KB d V g B + KB p Vg B C B L B L B L B KB i IB L C A Vg B Ki B L B C B D A L A KB d IB L C A C B 0 Vg BKB d C B L B V A g L A IB L KB p C A 0 K B p V B g L B 0 0 C B ] [ C DMC = 0 0 KB d K B C B p Ki B [ ] E DMC = 0 KB d K B C B p 0 (4.7) (4.8) (4.9) (4.30) 4..5 Control to output transfer function Using the results of the previous section, the control to output transfer function, G DMC, can be derived. Using Equation (4.3), G DMC is found and is shown in Equation (4.3). G DMC (s) = ( C DMC (si A) ) B + E DMC (4.3)

47 Chapter 4. System Modeling and Control 34 where I is the 5 5 identity matrix. G DMC (s) = ˆd B ˆd = V g ADB Kd B A C A C B L A L B s + s KB p Kd B den (s) + KB i K B d (4.3) where, den (s) =s 5 + KB d V g B s 4 + CA Vg BLA Kp B LA D B Kd BIB L +CB L A (D B ) +C B L B +C A L A s 3 C B L B L A C A C B L B + KB d V g B IL BLA D B Kp B +C A Vg B L A C A C B L B K B i LA s + KB i IB L LA D B +K B p V B g L A C A C B L B s + V B g K B i C A L A L B C B (4.33) Comparing this transfer function to a conventional voltage control technique, the control input remains the same (d A ), however the output is the mid-point voltage of the system, v A. Using the same A and B matrices, the output equation becomes that of Equation (4.34). Therefore the new C and E matrices are shown in Equations (4.35) and (4.36). y = x (4.34) [ ] C c = (4.35) [ ] E c = (4.36) Solving for the conventional transfer function yields: G c = ˆvA ˆd A = V g A s3 + s KB d V B g C B L B C A L A + s (+KB p Vg B ) + V g B Ki B C B L B C B L B (4.37) den (s) where the denominator is given by Equation (4.33).

48 Chapter 4. System Modeling and Control DMC vs. conventional control Control to output transfer functions This section will compare the control to output transfer functions of a system using DMC versus one using conventional output voltage control, as described by Equations (4.3) and (4.37). Table 4. lists the parameters used to compare the two control methods. The PID voltage controller for the downstream buck converter was designed using the transfer function method. It was designed to be a fairly fast, but very robust controller therefore the phase margin is 85. and the unity gain crossover frequency is 39.kHz. Table 4.: Parameters used to compare DMC and conventional control. Parameter Value Units C A μf L A 0.70 mh D A 0.50 Vg A V V A V C B μf L B 4.70 μh D B 0.4 Vg B V V B.00 V Kp B.9 0 Kd B KB i Io B 4.7 A To illustrate the advantages of DMC, both control to output transfer functions are plotted on the same graph with normalized dc gains, as shown in Figure 4.5(a). The plot depicts the system with a large midpoint capacitance, of 00.0μF. As this capacitance decreases, the normalized gain plot of the system changes dramatically, as shown in Figure 4.5(b). The capacitance value in this case has been reduced to 0.05μF. The transfer function representing the conventional control approach begins to develop a large resonant peak at around 65kHz.

49 Chapter 4. System Modeling and Control 36 Application of the Nyquist criterion shows that instability will result if loop gain at the secondary resonant frequency exceeds unity. This constrains controller design and limits the available bandwidth. For this comparison, the DMC approach offers a 5.8dB higher gain margin, thus allowing higher feedback gain and providing a faster response to a disturbance Conventional DMC 0 Conventional DMC Magnitude (db) Magnitude (db) Frequency (Hz) (a) C A = 00µF (b) C A Frequency (Hz) =0.05µF Figure 4.5: Gains of the control to output transfer functions of DMC and conventional control. Another property of these transfer functions is the steeper slope at high frequencies, seen in both Figures 4.5(a) and 4.5(b), that DMC exhibits. This makes the DMC system more robust to noise Simulation results Figure 4.6 shows the simulation results of a reference voltage step at the output of the linearized state space model of two cascaded lossy buck converters using conventional control and DMC. For both control methods, the same controller was used to control the downstream converter and the size of the mid-point capacitor in between the converters was 0.05μF. The upstream controllers were designed using the normalized bode plots of the system, and both controllers had the same zero. Therefore, the compensated bode plots of each system had the same dc gain.

50 Chapter 4. System Modeling and Control 37.4 Conventional DMC. Voltage (V) Time (s) Figure 4.6: The output voltage of two cascaded converters in response to a voltage step reference command controlled conventionally and with DMC. As shown in Figure 4.6, the output voltage of the DMC system reaches the new reference voltage more quickly than the system using conventional control. The DMC system reached 63% of the new reference step 3.47 times faster than the conventionally controlled system. These results are even better than might be predicted from the Bode plot analysis. This is because the faster DMC response increases the mid-point voltage and therefore increase the voltage across the inductor on the downstream stage, allowing its voltage to increase more rapidly than the system under conventional control Discussion This section has merely presented one example showing the benefits of DMC control for cascaded converters. Although limited, the examples in Sections and illustrate its significant advantages for systems with both a small and large energy storage capacitor. DMC has opened new avenues for high bandwidth two stage converters with minimal energy storage. However, to fully explore DMC, a more general analysis should be performed, which is out of the scope of this work.

51 Chapter 4. System Modeling and Control System models This section derives state space models of the proposed system. State space was chosen to simplify the process of combining converter models together as controllers are designed and added to the system. Using these models, the appropriate transfer functions will be extracted and then controllers will be designed using the transfer function method as described in [] and direct digital redesign as described in [3]. 4.. Lossy buck converter in state space Figure 4.7 shows the model of the lossy buck converter that is used for controller design. Its state space model was derived in Section 4.. and is described by Equations (4.7) - (4.0). i Switching Network i L B RQ B RL B V g B R Q B v v C B V B R B Figure 4.7: The buck converter with losses and switching network shown. 4.. Lossy flyback converter in state space A state space representation of a lossy flyback converter is derived based on Figure 4.8. As shown in the figure, numerous losses are taken into account. R A Q is the on resistance of the transistor Q, R A L is the resistance of magnetizing inductance, RA C is the equivalent series resistance of the capacitor C A, RA s is the sense resistor and V A D is the voltage drop across the diode.

52 Chapter 4. System Modeling and Control 39 :n i L A L A D VD A R C A C A A vˆo i o A A RL Rs A vg A ig A RQ A Q Figure 4.8: The flyback converter with losses. Due to the complexity of the model, a different approach from the previous section will be taken to obtain a linearized state space model. The state space averaging technique will be employed as described in [], [3]. This technique averages the entire circuit over one switching cycle, not just the switching components, as it is in the time averaged switch model. To begin, let the states, inputs and outputs be defined by Equations (4.38), (4.39) and (4.40), respectively.

53 Chapter 4. System Modeling and Control 40 x A = u A = xa y A = x A u A u A u A 3 y A y A y A 3 = = = î A L ˆv A ˆv A g ˆv A D î A o î A L î A g ˆv A o (4.38) (4.39) (4.40) Let matrices A A, BA, CA and EA represent the system during the first half of the switching cycle, and matrices A A, BA, CA and EA represent the system during the second half of the switching cycle. Averaging the circuit over one switching cycle yields the non linear state equations: LA 0 0 C A dxa (t) dt = ( A A xa (t)+b A ua (t) ) d A (t) + ( A A xa (t)+b A ua (t) )( d A (t) ) (4.4) y A (t) = ( C A xa (t)+e A ua (t) ) d A (t)+ ( C A xa (t)+e A ua (t) )( d A (t) ) (4.4) Define the matrix Z A by Equation (4.43) and replace each time dependent term in Equations (4.4) and (4.4) with a dc component and an ac component as shown in Equation (4.9). Eliminating second order terms yields the linearized state space model

54 Chapter 4. System Modeling and Control 4 of the system, shown in Equations (4.44) and (4.45). Z A = LA 0 0 C A (4.43) Z A dxa = A A x A + B A u A + F A ˆdA dt y A = C A x A + E A u A + G A ˆdA (4.44) (4.45) where: F A = (( A A ) AA X A + ( B A ) ) BA U A (4.46) G A = (( ) C A C A X A + ( ) E A E A U A (4.47) A A = D A A A + ( D A) A A (4.48) B A = D A B A + ( D A) B A (4.49) C A = D A C A + ( D A) C A (4.50) E A = D A E A + ( D A) E A (4.5) In the above equations (Equations (4.46) - (4.5)), vectors X A and U A represent the dc states and inputs respectively. It can be shown that the dc value of the states and outputs can be calculated using Equations (4.5) and (4.53). X A = ( A A) B A U A (4.5) Y A = ( C ( A A A) ) B A + E A U A (4.53)

55 Chapter 4. System Modeling and Control 4 where the dc inputs are defined by: U A = V A g V A D I A o. (4.54) Using Figure 4.8, the state equations for both parts of the switching cycle can be written. Beginning with the first part of the switching cycle when transistor Q is on, the state and output equations are shown in Equations (4.55) - (4.59). L A dxa = u A dt ( xa R A L + RQ) A (4.55) C A dxa = u A 3 dt (4.56) y A = x A (4.57) y A = x A (4.58) y A 3 = xa ua 3 RA C (4.59) From these equations, state matrices can be derived, and are shown in Equations (4.60) - (4.63).

56 Chapter 4. System Modeling and Control 43 A A = ( RL A + ) RA Q 0 (4.60) 0 0 B A = C A = E A = RC A (4.6) (4.6) (4.63) For the second part of the switching cycle diode D conducts and the state and output equations are shown in Equations (4.64) - (4.68). L A dxa dt dx A C A dt = n ( ( ) ) u A + x A n u A 3 RC A + xa + xa RA s R A n L xa (4.64) = xa n ua 3 (4.65) y A = xa (4.66) y A = 0 (4.67) ( ) x y3 A A = xa + n ua 3 RC A (4.68) The state matrices for the second part of the switching cycle can be written:

57 Chapter 4. System Modeling and Control 44 A A = ( n ( ) ) R A C + Rs A R A L B A = 0 R A C n n C A = 0 0 R A C n E A = RC A n 0 n (4.69) (4.70) (4.7) (4.7) Using Equations (4.60) - (4.63) and (4.69) - (4.7), the matrices required for the ac state space model of Equations (4.44) and (4.45) are found and shown in Equations (4.73) - (4.78).

58 Chapter 4. System Modeling and Control 45 A A = B A = F A = ( DA RL A ) ( )( RA Q + D A n DA ( D A ) n ( D A )R A C n 0 0 (D A V A g +I A o R A L n+nia o R A Q V A g ) ( +D A ) ( +D A )Io A 0 C A = D A 0 ( R ) C A D A E A = RC A 0 G A = n ( +D A )Io A R A C nia o ( +D A ) ( ) ) R A C + Rs A R A L ( D A )/n ( D A ) 0 n (4.73) (4.74) (4.75) (4.76) (4.77) (4.78) 4..3 Additional parts of the system model In addition to state space models of the converters, transfer functions must be defined to complete the system model. They are described below Additional gain in current loop Since the flyback current controller will be acting as a PFC in this system, it must track the input current. From the ideal large signal model of the flyback converter, the input current and inductor current are related as shown in Equation (3.8), repeated below for

59 Chapter 4. System Modeling and Control 46 convenience: i A g (t) Ts = d (t) i A L (t) Ts (4.79) However, in the proposed system, the inductor current will be measured on the secondary side. Thus an additional factor of n from the turns ratio of the transformer must also be added, resulting in Equation (4.80). i A g (t) Ts = nd (t) i A L (t) Ts (4.80) This gain will be incorporated into the loop gain of the current controller to deduce the input current from the measured current. It is important to include this value (instead of absorbing it into the controller) because while the converter is operating as a PFC, the duty cycle will be varying considerably as shown in Section Additional components used in digital control As stated in Section.4, digital techniques will be used to implement the controller. Therefore, a digital pulse-width modulator (DPWM) block and an analog to digital converter (ADC) block must be modeled in continuous time. Both of these models can be found in [3], and are repeated below: G dpwm (s) = e st dpwm (4.8) L dpwm ( n adc ) G adc (s) = e st adc (4.8) V maxadc where L pwm is the number of discrete steps in the DPWM, T pwm is the period of the DPWM, n adc is the number of bits of the ADC, V maxadc is the maximum input voltage into the ADC and T adc istheupdateperiodoftheadc.

60 Chapter 4. System Modeling and Control 47 However, since the dynamics of the system that we are interested in are much slower than the switching period, the analog to digital converter and the digital pulse width modulator will be approximated with gains as shown in Equations (4.83) and (4.84). G dpwm (s) L dpwm = K dpwm (4.83) G adc (s) n adc V maxadc = K adc (4.84) Digital filter To control the midpoint voltage of the converter, DMC control is implemented. However, before the duty cycle of the buck converter can be fed into the voltage loop of the flyback converter, it must be filtered. This is because a large ripple will appear on the duty cycle as a consequence from the large ripple voltage on the midpoint capacitor. The filter is implemented digitally as an eight point moving average filter, operating at 480Hz. However, in continuous time it will be modeled as a second order filter for simplicity, as shown in Equation (4.85). G f (s) = State space representation of controller,ω + Q f s f =π30,q f = (4.85) ω f + s ωf In order to combine the flyback and buck converter models to find an open loop transfer function that can be used to design the DMC controller, the voltage and current controllers of the buck and flyback converters are represented in state space to simplify the integration process. The general form of a PI controller in state space is shown in Figure 4.9. From this figure the state matrices can be found and are described in Equations (4.86) - (4.88).

61 Chapter 4. System Modeling and Control 48 p i s Figure 4.9: A PI controller in state space. A PI = [0] (4.86) B PI = [] (4.87) C PI =[K i ] (4.88) E PI =[K p ] (4.89) 4..4 Complete system model in state space Using the models built in Sections 4.., 4.. and 4..3, the complete small signal system model can be built, and it is shown in Figure 4.0. A vˆg u A d A u3 A Flyback Converter Z A x A = A A x A + B A u A + F A d y A = C A x A + D A u A + G A d y3 A y A u B u B Buck Converter x B = A B x B + B B u B y B = C B x B + D B u B y B y B Kadc 3 Kdpwm A nd A Kadc Kdpwm B Gv B (s) V B ref Gi A (s) Gv A (s) Gf(s) k A Kadc Vg A D B ref d B Figure 4.0: The complete small signal model of the system. In order to be able to design a controller for DMC controller, the control to output transfer function must be extracted from the model of Figure 4.0. To obtain this transfer function, the A SYS, B SYS, C SYS and E SYS state matrices of the system are derived.

62 Chapter 4. System Modeling and Control 49 This uses the state space models of the lossy buck, lossy flyback and controllers already created. Using Equation (4.3), the transfer function from input k A to output d B (as shown on Figure 4.0) can be extracted. Multiplying this by the filter, G f (s), yields the control to output transfer function sought. To find the system state space matrices, the voltage controller of the buck converter and the current controller of the flyback converter are replaced with PI controllers, defined by state Equations (4.90), (4.9) and (4.9), (4.93), respectively. ẋ B PI = ub PI (4.90) ypi B = KB i xb PI + KB p ub PI (4.9) ẋ A PI = ua PI (4.9) ypi A = Ki A x A PI + Kp A u A PI (4.93) To combine all the models derived in previous sections, an augmented system with superscripts TOT is created and defined in Equations (4.94) and (4.95). ẋ TOT = A TOT x TOT + B TOT u TOT (4.94) y TOT = C TOT x TOT + E TOT u TOT (4.95) The states, inputs and outputs are defined by Equations (4.96) - (4.98).

63 Chapter 4. System Modeling and Control 50 x TOT = x A x A PI x B x B PI (4.96) u TOT = y TOT = u A ˆd A u A PI u B u A PI y A ypi A y B (4.97) (4.98) y B PI The total state matrices are defined by Equations (4.99) - (4.0).

64 Chapter 4. System Modeling and Control 5 A TOT = ( Z A ) A A A A PI A B 0 (4.99) B TOT = A B PI ( ) Z A B A ( Z A) F A B A PI B B 0 (4.00) B B PI C A C TOT 0 C A PI 0 0 = 0 0 C B 0 (4.0) E TOT = C B PI E A G A E A PI E B 0 (4.0) E B PI The system model will have the same states as the augmented model, and for simplicity the outputs will also be the same, as given in Equations (4.03) and (4.04). x TOT = x SYS (4.03) y TOT = y SYS (4.04) However, the inputs into the system model will be different and are defined in Equation (4.05).

65 Chapter 4. System Modeling and Control 5 u SYS = u SY S u SY S u SY S 3 = u A u A k A = ˆv A g ˆv A D k A (4.05) Using Figure 4.0, interconnection of the systems is described by Equations (4.06). u TOT = Ny TOT + Mu SYS (4.06) where, N = Kpwm A nd A K adc Kpwm B K adc M = (4.07) (4.08)

66 Chapter 4. System Modeling and Control 53 yields: Substituting Equations (4.03), (4.04) and (4.06) into Equations (4.96) and (4.98) ẋ SYS = A TOT x SYS + B TOT ( Ny SYS + Mu SYS) (4.09) y SYS = C TOT x SYS + E TOT ( Ny SYS + Mu SYS) (4.0) Solving for y SY S yields Equations (4.). y SYS = ( I E TOT N ) C TOT x SYS + ( I 7 7 E TOT N ) E TOT Mu SYS (4.) where I is the 7 7 identity matrix. Substituting equation(4.) into Equation (4.09) and rearranging yields Equation (4.). ( ẋ SYS = A TOT + B TOT N ( I 7 7 E TOT N ) ) C TOT x SYS ( + B TOT M + B TOT N ( I 7 7 E TOT N ) ) E TOT M u SYS (4.) From Equations (4.) and (4.), the state matrices of the system are found and are shown in Equations (4.3) - (4.6). ( A SYS = A TOT + B TOT N ( I 7 7 E TOT N ) ) C TOT ( B SYS = B TOT M + B TOT N ( I 7 7 E TOT N ) ) E TOT M C SYS = ( I 7 7 E TOT N ) C TOT (4.3) (4.4) (4.5) E SYS = ( I 7 7 E TOT N ) E TOT M (4.6)

67 Chapter 4. System Modeling and Control 54 Using these state matrices, the control to output transfer function can be found. 4.3 Controller design This section goes through the analysis and controller design of the proposed system as shown in Figure.3. There are three controllers to design: a voltage controller for the downstream buck converter, a voltage controller for the flyback which will utilize DMC and a current controller for the flyback Voltage controller design for buck converter Using parameters from the converter designed in the laboratory, a controller will be designed for the buck converter. The control to output transfer function can be found by using Equation (4.3), and is shown in Equation (4.7). G B vc (s) = ˆvB ˆd B = + (RB Q +RB L) R B + s V B g ( L B R B + R B Q CB + R B L CB ) + s C B L B (4.7) Table 4. lists all the parameters of the buck converter and appropriate ADC and DPWM. The bode plot of the system can be obtained by substituting these parameters into Equation (4.7) and multiplying by the transfer functions of the DPWM and ADC, yielding Figure 4.. For this converter, a proportional integral (PI) controller was designed. The zero was chosen to be as close to the natural frequency of the buck converter as possible to maximize the bandwidth, while maintaining a large phase margin for all operating conditions. This zero was placed at 0.98kHz. The gain was adjusted to provide a large phase margin for all operating conditions. Figure 4. shows the compensated loop gain of the buck converter at the operating point

68 Chapter 4. System Modeling and Control 55 Table 4.: Parameters used in the buck converter developed in lab. Parameter Value Units C B μf L B 4.70 μh D B Vg B V V B.00 V RQ B 0.5 Ω RL B 9.50 mω R B Ω L B dpwm 5 Tdpwm B.6 μs K adc3.4 0 Magnitude 30 Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.: The bode plot of the uncompensated[bode plot of G A ic (s)] control to output transfer function of the buck converter, G B vc (s). with the worst phase margin. Its phase margin can be calculated to be 8.4. Knowing this, the designed controller can be implemented digitally. To do this, the bilinear transform [33] was used to transform the controller from continuous time to discrete time. The result is shown in Equation (4.8).

69 Chapter 4. System Modeling and Control Magnitude 40 Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.: The bode plot of the compensated control to output transfer function of the buck converter, G B vc (s), under the operating condition with the smallest phase margin. d [n] =e [n] [n]+d [n] (4.8) 4.3. Current controller design for the flyback converter In this section, a controller is designed for the current controller of the flyback converter. The design is based on parameters of the actual prototype designed in the lab. To determine the control to output transfer function, convert Equation (4.44) to the Laplace domain, solve for the states x, substitute the result into equation(4.45), set all other inputs to zero and solve for y (s) /d (s). The result is shown below: G id (s) = îa L ˆd A = [ 0 0 ] ( C A ( K A s A A) F A + G A ) (4.9) Using the matrices found in Section 4.., the transfer function is found and is shown in Equation (4.0).

70 Chapter 4. System Modeling and Control 57 s ω A z + G id (s) =G A d0 a A s + b A s + (4.0) where, ni A o G A d0 = ( D A ) (4.) ( ωz A I ) o A D A = ( ) nc A Io A R A Q RL A + CA Vg A ( (4.) DA ) a A = n C A L A ( D A ) (4.3) b A = n C ( A RL A + ) DA R ( Q A + C A D A)( RC A + ) RA s ( D A ) (4.4) Table 4.3 lists all the parameters of the flyback converter developed in the laboratory that were substituted into Equation (4.0). Figure 4.3 shows the bode plot of the uncompensated control to output transfer function. Table 4.3: Parameters used in the flyback converter developed in lab. Parameter Value Units C A μf L A 0.70 μh D A Vg A V RMS V A V RQ A.70 Ω RL A 0.5 Ω Rs A.00 Ω RC A 0.0 Ω Io A A n 0.3 VD A.50 V L A dpwm 500 Tdpwm A.50 μs K adc 446.8

71 Chapter 4. System Modeling and Control Magnitude 40 Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.3: The bode plot of the uncompensated control to output transfer function of the flyback converter. For this system, a PI controller was designed. The zero of the controller was chosen to be placed after the zero of the plant which causes the gain to decrease at low frequencies. Therefore, the zero of the controller was placed at 8.9kHz. This results in a constant gain at low frequencies in the compensated system which gradually tapers off, as shown in Figure 4.4. The designed controller can be implemented digitally using the bilinear transform [33]. The result is shown in Equation (4.5). d [n] =6e [n] e [n ] + d [n] (4.5) DMC controller design for the flyback converter In this section, a controller is designed to execute DMC control to regulate the average duty cycle of the buck converter. It is based on parameters used in laboratory, as shown in Tables 4., 4.3 and 4.4 and the controllers designed in Sections 4.3. and The

72 Chapter 4. System Modeling and Control Magnitude 40 Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.4: The bode plot of the compensated control to output transfer function of the flyback converter. control to output transfer function is derived using the state matrices derived in Equations (4.3) to (4.6). Additionally, the transfer function derived is then multiplied by the transfer function used to estimate the low pass filter as defined by Equation (4.85). The resulting control to output transfer function for DMC control is shown in Figure 4.5. Table 4.4: Parameters from the laboratory used in the complete system model. Parameter Value Units K adc 3.86 As shown in the figure, the system exhibits a 80 phase shift at dc. This is correct because the output of this transfer function is a duty cycle of a constant power converter. Hence, when the duty cycle of the flyback converter increases, the mid point voltage will increase, and then the duty cycle of the buck converter will decrease. This transfer function is dominated by the slow filter used to filter out the ripple duty cycle on the downstream buck converter. Therefore a slow PI controller was designed with a corner frequency of 3.09Hz. The compensated system is shown in Figure 4.6.

73 Chapter 4. System Modeling and Control Magnitude Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.5: The bode plot of the uncompensated control to output transfer function of the system using DMC control. Note that the system appears to have a negative phase margin, and should be unstable. However, the system is indeed stable. This negative phase margin can be attributed to the DMC architecture of the system, which should be studied more rigorously in future work. The designed controller can be implemented digitally using the bilinear transform [33]. This particular controller does not execute every switching cycle. It executes every time the digital filter is updated, which occurs at a frequency of 480Hz. The result is shown in Equation (4.6). d [n] = 50e [n] 47e [n ] + d [n] (4.6)

74 Chapter 4. System Modeling and Control 6 00 Magnitude 50 Magnitude (db) Frequency (Hz) Phase Phase (deg) Frequency (Hz) Figure 4.6: The bode plot of the compensated control to output transfer function of the system using DMC control.

75 Chapter 5 Experimental Results This chapter presents the results obtained with an experimental prototype of the ac/dc system described in the previous chapters. The prototype was fully fabricated in the laboratory with off-shelf discrete components for the power stages and an FPGA development board to implement the controller. First, some discussion is presented on the component selections made for the flyback converter. This is because the main storage capacitor will have a large ripple voltage and it must be properly designed. Following this, performance results from steady state and transient tests are presented. Finally this chapter will conclude with advantages and limitations of the designed system. 5. Flyback component selection 5.. Flyback transformer The flyback transformer was chosen in order to meet the following criteria: The primary coil can be excited with a rectified, universal ac input voltage of 85 65V RMS. The turns ratio of no more than : 0.5 tostepdownthevoltage. 6

76 Chapter 5. Experimental Results 63 A power rating of at least 40W. Readily available for purchase. Using this criteria, the flyback transformer chosen was model number Z960-AL manufactured by Coilcraft R. 5.. Main energy storage capacitor The main energy storage capacitor is also the output capacitor of the flyback converter. Since this capacitor has a large ripple voltage on it, it must be designed in accordance with Equation (3.). The technical specifications of this capacitor for one phase of the converter are shown in Table 5.. Table 5.: Technical specifications for the main energy storage capacitor. Parameter Value Units P out 0 W η Buck 80 % V nominal 50 V ΔV MAX 5 V Using these specifications, an electrolytic 00μF capacitor was chosen manufactured by Panasonic R, model number: EEUFCJ0L. Its specifications are shown in Table 5., and they can be substituted into Equation (3.). The result of the power it can provide is shown in Equation (5.), and is well within the design criteria of Table 5. with a factor of safety of.. Table 5.: Technical specifications of the main energy storage capacitor chosen, Panasonic R EEUFCJ0. Parameter Value Units I ripple at 0Hz 83 ma V MAX 63 V R ESR 0.30 Ω

77 Chapter 5. Experimental Results 64 P dc = V MAX I ripple I ripple πf ripple C =55.36W (5.) The capacitor chosen is a low cost, readily available capacitor. Furthermore, it can handle a relatively large ripple current, which is ideal for the proposed application. As shown later in Table 5.6, this capacitor greatly contributes to the up to 9 times reduction in energy storage when compared to conventional solutions. Another consequence of reducing the main energy storage capacitor s size and voltage, is the possibility of using ceramic capacitors for this component. By doing so, the overall reliability of the converter is increased because ceramic capacitors are more robust then electrolytic ones. 5. Converter specifications The converter designed in the laboratory has the performance specifications shown in Table 5.3. Technical specifications are shown in Table 5.4 with a detailed schematic of one phase of the converter shown in Appendix A. Table 5.3: Performance specifications of the converter designed in the laboratory. Input Voltage 85 65V RMS,50 60Hz Output Voltage Vdc± 0.7V Max. Output Power 40W Power Factor 0.98 for loads 0W Interleaved Phases 5.3 Steady state operation Figure 5. shows the input voltage and current under full load conditions (40W ). The input voltage in this case was set to 0V RMS at 60Hz. As shown, the converter is

78 Chapter 5. Experimental Results 65 Table 5.4: Technical specifications of each phase of the converter designed in the laboratory. Note that capacitor C A is the main energy storage component of the system. Flyback Converter Parameter Value Units L A 0.7 mh C A 50 μf Vnominal A 50 V f sw 400 khz Buck Converter Parameter Value Units L B 4.7 μh C B 47 μf f sw 800 khz operating with excellent power factor correction and in this particular case, the power factor is The total harmonic distortion is 7.4%. Vg Ig Figure 5.: The input voltage and current of the converter under full load. V g = 0V RMS, 60Hz. From top to bottom: Vg line voltage on CH3 at 00V/Div and Ig line current on CH at A/Div. Time scale: 0ms/Div Figure 5. shows the voltage on the energy storage capacitor, the output voltage and the duty cycle of the flyback converter for the same load and input voltage conditions as in Figure 5.. In this figure, the large ripple voltage on the capacitor is clearly visible

79 Chapter 5. Experimental Results 66 at twice the line frequency. It has a peak to peak voltage of 3.98V,or3.4% as a percentage of the nominal value. Table 5.5 shows the percentage ripple voltage that is obtained at half and full loads for input line frequencies of 50Hz and 60Hz. The output voltage also exhibits some ripple, due to the well known problem of a limited resolution of the DPWM for the buck converter. There are many solutions to this problem, for example, a sigma delta DPWM as shown in [34], however this is not a focus of this work. Finally, the duty cycle of the flyback converter shown in Figure 5. exhibits the behaviour expected by the theoretical duty cycle from Equation (3.9). To obtain this waveform, the duty cycle signal was connected to an RC filter. Figure 5.3(a) shows the theoretical and experimental duty cycles on the same axes and Figure 5.3(b) shows the FFT of both the theoretical and experimental duty cycles without a dc component, normalized to their fundamental frequency of 0Hz. From these figures, it can be seen that the experimental duty cycle closely matches the theoretical duty cycle at low frequencies, and begins to loose this similarity at high frequencies, in the khz range. This is due to the fact that the experimental duty cycle is purposefully limited as a safety precaution and will be discussed further in Section 5.7. Vm Vo Flyback Duty Figure 5.: From top to bottom: Vm the voltage on the energy storage capacitor on CH at 0V/Div, Vo the output voltage on CH3 at 0V/Div and the duty cycle of the flyback converter on CH4 at 500mV/Div. Time scale: 5ms/Div

80 Chapter 5. Experimental Results 67 Table 5.5: The percentage voltage ripple on the main energy storage capacitor at different loads and line frequencies. 50Hz 60Hz 0W 3.9% 9.3% 40W 37.06% 3.44% Experimental Theoretical 0 Experimental Theoretical Duty Normalized Magnitude (db) Time (a) The theoretical and experimental duty cycle of the flyback converter plotted together Frequency (Hz) (b) The FFT of the theoretical and experimental duty cycles without dc and normalized to 0Hz. Figure 5.3: Comparing the theoretical and experimental duty cycles. 5.4 Power factor and THD This section summarizes the performance of the converter as a power factor regulator and evaluates it on two criteria: the power factor as measured by the power supply used and the total harmonic distortion as calculated from the input current measured by the oscilloscope. The details of both instruments can be found in Appendix B. Figures 5.4(a) and 5.4(b) show the measured power factor. As shown, the converter maintains a power factor of 0.98 or more for all input voltages under full and half load. The power factor decreases at high voltages due to the limitations on measuring small currents which will be discussed in Section 5.7. Figures 5.5(a) and 5.5(b) show the calculated total harmonic distortion from the converter developed in the laboratory for all input voltages under full and half load. In a similar manner and reason that the power factor decreases at high voltages, the THD

81 Chapter 5. Experimental Results W Load 40W Load W Load 40W Load Power Factor Power Factor Input Voltage (V RMS ) (a) f line =50Hz Input Voltage (V RMS ) (b) f line =60Hz Figure 5.4: The measured power factor of the converter developed in the laboratory. increases, as shown in the figures. 0 0W Load 40W Load 0 0W Load 40W Load Total Harmonic Distortion (%) 4 0 Total Harmonic Distortion (%) Input Voltage (V) Input Voltage (V) (a) f line =50Hz (b) f line =60Hz Figure 5.5: The calculated total harmonic distortion of the converter developed in the laboratory. Figure 5.6 shows the worst case odd harmonic content over all loads, input frequencies and voltages plotted against the harmonic current emission limits provided by the IEC standard. As shown, the converter developed in the laboratory emitted at most half the harmonic current limit as provided by this standard, this minimum occurring at the 9th harmonic current. This also shows that a low cost, PFC supply can be built with sensing on the secondary side that exceeds any input harmonic current

82 Chapter 5. Experimental Results 69 standards currently enforced. 0 IEC Limits Proposed Harmonic Current ma/w Harmonic Number Figure 5.6: Harmonic current emissions from the converter built in the laboratory plotted against the maximum allowable harmonic current emission as stated in the IEC standard [4]. 5.5 Transient response The transient response of the converter was tested with an input voltage of 0V RMS at 60Hz under a 50% load step from 0W to 40W. Figures 5.7(a) and 5.8(a) show the results. The transient responses were obtained by using a self tuning dead zone controller [30] and DMC. Without the use of a dead zone controller, the transient responses become very poor and are shown in Figures 5.7(b) and 5.8(b) From the figures it is evident that despite the large ripple voltage on the main energy storage capacitor and the little amount of energy stored on it, digital control enabled the development of a suitable controller that can successfully maintain the mid-point voltage of the converter through large transients.

83 Chapter 5. Experimental Results 70 Vm Vm Vo Vo Load Step Load Step (a) with dead zone controller (b) without dead zone controller Figure 5.7: The transient response of the converter developed in the laboratory under a 50% load step increase, with and without the dead zone controller. From top to bottom: Vmthe voltage on the main energy storage capacitor on CH at 0V/Div, Vothe output voltage on CH3 at 0V/Div and the load step signal on CH4 at 0V/Div. Time scale: 0ms/Div Vm Vm Vo Vo Load Step Load Step (a) with dead zone controller (b) without dead zone controller Figure 5.8: The transient response of the converter developed in the laboratory under a 50% load step decrease, with and without the dead zone controller. From top to bottom: Vmthe voltage on the main energy storage capacitor on CH at 0V/Div, Vothe output voltage on CH3 at 0V/Div and the load step signal on CH4 at 0V/Div. Time scale: 0ms/Div 5.6 Energy storage comparison One of the main features of the proposed system is its reduced energy storage. Table 5.6 compares the proposed system to three other PFC supplies supplied by three different manufacturers. As shown, the proposed solution has a significant reduction in energy storage from

84 Chapter 5. Experimental Results 7 Table 5.6: The energy storage elements of the proposed converter in comparison with other PFC power supplies. Topology L L current C C voltage P out Energy Storage (mh) (A) (μf ) (V ) (W ) (mj/w ) Proposed Boost [35] Boost [36] Interleaved Boost [37] the conventional solutions. It has up to 9 times less energy storage capacity which translates into a lower cost and smaller size of the converter, as energy storage components significantly contribute to both of these factors. This is a substantial improvement over other topologies and this proposed system has opened new opportunities in PFC design. 5.7 Limitations of the proposed system 5.7. Current measurement As mentioned earlier in this chapter, the power factor of the converter decreases at high voltages, when the current is decreased. The main source of harmonic distortion occurs near the zero crossings of the input voltage when the duty cycle is large. This problem can be attributed to the current sensing circuit. Figure 5.9 shows the waveform that goes into the current sensing ADC. When the main switch of the flyback converter is switched off, current begins to flow in the secondary winding of the flyback transformer and a voltage is sensed on the current sensing resistor. Due to a small capacitance at this node created by an anti-parallel voltage protection diode, the sensed voltage exhibits an exponential waveform as seen in Figure 5.9. Therefore at large duty cycles, the current measurement is not consistent with the actual input current into the converter, and the actual current is much larger than the measured input current. To overcome this limitation, the duty cycle is digitally limited at higher voltages. If it is not, the input current exhibits spikes near the zero crossings of the voltage waveform.

85 Chapter 5. Experimental Results 7 Duty Cycle Measured Current Figure 5.9: Current sensing waveform. From top to bottom: the duty cycle of the flyback converter on CH at V/Div and the input to the current sensing ADC on CH at 00mV/Div. Time scale: μs/div 5.7. Loss in main energy storage capacitor A trade off of the proposed converter is energy storage for a large ripple voltage on the main energy storage capacitor of the system. As a consequence, the ripple current in this capacitor will generate some losses proportional to the ESR of the capacitor, and this loss can be calculated using the theoretical capacitor voltage obtained in Equation (3.8). Taking the derivative of this equation, multiplying by the capacitance and substituting V g I g /forp dc yields the current in the capacitor, described in Equation (5.). cos (ωt) i c (t) = P dc P dc sin(ωt) + V ωc 0 (5.) Using this equation the power lost in the energy storage capacitor, P C, is determined by Equation (5.3). P C = ω π (π/ω) 0 i c (t) R ESR dt (5.3) Therefore in the worst case scenario where the average efficiency of the buck converter is 70%, the power lost in the main energy storage capacitor can be calculated to be

86 Chapter 5. Experimental Results mW. This analysis shows that even with a larger ripple current on the main energy storage capacitor, the losses due to this current are very small compared with the output power of the converter. This occurs because typical manufactured capacitors exhibit a direct relationship between energy storage and ESR, as the energy storage decreases, the ESR also decreases Hold up time Hold up time, also known as ride through time, is a converter s ability to provide a continuous output voltage in the event of a temporary fault in the ac voltage. For manufacturers of dc power supplies for information technology (IT) applications, there is a standard created by the Information Technology Industry Council which they should adhere to if the voltage sags, swells or is interrupted for a certain period of time. This standard is summarized in Figure 5.0, which is commonly known as the CBEMA Curve. From the figure, the ITIC recommends that a power supply have a hold up time of at least 0ms, or one line cycle at 50Hz. For the proposed system, the hold up time in the worst case is about 4ms. Figure 5. shows the hold up time of the proposed converter built in the laboratory under full load conditions with an input voltage of 0V RMS at 50Hz. As shown, the voltage is switched off near zero, and the output voltage is able to remain constant for only another 4ms after the switch off. However this does not mean the proposed system is not a viable solution. The proposed solution can be implemented for devices that do not require such a stringent hold up time, like battery powered devices such as laptops. The CBEMA Curve was developed to protect sensitive and essential equipment. Furthermore, battery charging applications is an area of the market where it is more desirable to have a power supply that is smaller and lighter at the expense of hold up time because it must be carried around with the device.

87 Chapter 5. Experimental Results 74 Figure 5.0: The CBEMA Curve [].

88 Chapter 5. Experimental Results 75 Vm Vo Vg measured Figure 5.: Hold up time of the converter developed in the laboratory under full load conditions with an input voltage of 0V RMS at 50Hz. From top to bottom: Vm the voltage on the main energy storage capacitor on CH at 0V/Div, Vothe output voltage on CH3 at 0V/Div and the input voltage sensed on the secondary side on CH4 at V/Div. Time scale: 5ms/Div