Future Power Architectures for Servers and Proposed Technologies
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1 1 Future Power Architectures for Servers and Proposed Technologies by Ming Xu Sep. 12, 2006 Center For Power Electronics Systems A National Science Foundation Engineering Research Center Virginia Tech, University of Wisconsin - Madison, Rensselaer Polytechnic Institute North Carolina A&T State University, University of Puerto Rico - Mayaguez
2 Present Power Delivery System AC PSU 93%X86% Eng. St. D2D 12V 5V 3.3V 80% 86% 85% 26% VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ 1.5V/ 3(6)A/ 1(2)A /ns 1.2V/ 3.6(7.2)A/ 1(2)A /ns 1.8V/ (0.65)A / (0.025)A /ns 1.3V/ (0.5)A/ (1)A /ns 3.3V/ 0.14(0.23)A/ 0.36(0.55)A /ns Processor1 Processor2 Chipset D2D 5VSB 86% 1.8V 0.9V Memory Low efficiency on power delivering path Large holdup capacitor 12V 5V 12V 5V 3.3V HDD Other 2
3 Single Regulated Bus Structure AC PSU 93%X93% Eng. St. D2D 12V 80% 86% 85% 26% VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ 1.5V/ 3(6)A/ 1(2)A /ns 1.2V/ 3.6(7.2)A/ 1(2)A /ns 1.8V/ (0.65)A / (0.025)A /ns 1.3V/ (0.5)A/ (1)A /ns 3.3V/ 0.14(0.23)A/ 0.36(0.55)A /ns Processor1 Processor2 Chipset D2D 5VSB Higher efficiency PSU Standardized 12V s can be used to generate 3.3 and 5V Large holdup caps 96% 96% 86% 1.8V 12V 5V 12V 5V 3.3V 0.9V Memory HDD Other 3
4 One Vision from Intel 95% 400V 92% D2D D2D 12V 80% Socket 0 Socket 1 Memory IO AC HTEC D2D 88% 3.3V Chipset D2D 90% D2D D2D 5V 5VSB 5V 3.3V HDD Fans Other En. St. on board High voltage distribution; Flexibility for higher efficiency and lower cost; Low efficiency D2D because of wide input range; Low frequency, Low efficiency CPU s; 4
5 Vision from a Computer Giant DCX 90 ~ 260Vac 12V DCX High Density Flexibility and Low Cost Building Block and Standardization High System Efficiency for whole load range 5
6 Conventional Building Blocks 99% PWM Poor low Line Efficiency 98% 97% 96% 95% 94% 93% 100 khz 92% 300 khz 600 khz 91% Vin (VAC) 0V Q1 Q2 Q3 Q4 T np:ns D1 D2 Lo Co 48V Vout PWM DC/DC Poor HF and wide Vin Efficiency Vin(V) Optimized for fixed input at 400V only 92 designed for V to 400V V in Q1 Q3 Q5 Q7 Q2 Q4 Q6 Q8 Q2 Q4 Q6 Q8 L L L L Co RL PWM / Poor High Frequency Efficiency kHz 1MHz Output Current 6
7 New Building Blocks Available from CPES 400V/200V Voltage Divider, 1kW/in 3, >99% efficiency Voltage Dividers 12V/6V Voltage Divider, 2kW/in 3, 98% efficiency 1MHz 400V/48V SRBC 76W/in3 1MHz, 5V/1.2V 100A 2MHz, 5V/1.2V 100A 1MHz 400V/12V SRBC 113W/in3 400kHz 200V/12V SRBC BMP Semi-Regulated Bus Converters (SRBC) MHz Converter Low voltage devices 7
8 High Voltage Divider and its Benefits C Line Interleaving S S 200V/400V D o C o D o C o Voltage Divider Doubler 200V Volume (cu. in.) % Reduction EMI Filter Inductor Heat Sink 99% 98% 97% P o = 650 W, f s = 600 khz khz 600 khz Interleaving 100kHz 600kHz Efficiency 96% 95% 94% 93% 92% 90% volume reduction 91% Vin (VAC) 60% volume reduction 8
9 Voltage Dividers from CPES Q 1 C 1 Q 1 Q 1 C 2 Q 2 Q 2 Q 2 V in Q 3 + V in Q 3 + V in Q 3 + Q 4 C 3 - V O V O Q 4 - Q 4 Q 4 - V O 70W 12V-to-6V (V o = V in / 2 ) 2000W/in 3 - Efficien 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% Po (W ) variable frequency Over power ~98% 70W; 95.5% 130W; 99% light load; Efficiency is not sensitive to the devices 9
10 Energy Storage Requirement % Holdup capacitance (uf) % 600 Efficiency Volume DC/DC stage input voltage variation (V) 700W, 90% DC/DC efficiency Wide DC/DC stage operation range can reduce holdup time capacitor requirement DC/DC stage has lower efficiency with large input voltage range 10
11 Semi-Regulated Bus Converter (SRBC) and its Benefits D 2 Full load No load S 2 Va S 1 Ir Cr Lr Lm ZVS Vin=300V Vin=400V LLC Resonant DC/DC 97 Line change vs. Efficiency D 1 ZCS 96 Efficiency LLC Asym. HB AHB optimized for 400V Design with 300~ 400V input range Transformer turns-ratio Normalized frequency n = V in / 2 V o Vin(V) Test condition: Vo=48V Po=1000W Normal condition 11
12 Comparison between PWM DC/DC and LLC 18 Primary Conduction loss(w) PWM LLC Input voltage(v) Primary Switching Loss (W) Asym. HB LLC Vin (V) PWM LLC Loss(W) Primary conduction loss Primary switching loss Secondary conduction loss PWM LLC Primary conduction loss 9.7W 9.5W Primary switching loss 13.8W 6.1W Secondary conduction loss 24.0W 13.0W Secondary switching loss? 0W Total 47.5+? W 28.6W 12
13 Unregulated Semi-Regulated BCX ( DC/DC BCX Transformer) (SRBC) V Holdup time Holdup time V V V bus V bus >20mS Unregulated Bus t >20mS Semi-regulated Bus t During normal operation, Semi-Regulated Bus Converter (SRBC) works un-regulated, which can maximize the efficiency of SRBC During holdup-time, SRBC regulates output voltage by lowing f s Don t need to redesign s 13
14 CPES s LLC SRBC LLC vs. Asym. Half Bridge Asym. Half Bridge LLC 1MHz 400V/48V SRBC, 76W/in 3 Efficiency Output Power(W) Test condition: Vin=400V, Vo=48V, 200KHz Efficiency of LLC SRBC Efficiency (%) kHz 400kHz 1MHz Output power (W) 14
15 Two-Stage MHz /M From CPES Voltage Divider Multi-Phase Buck 2 nd Stage 12V in 6V out Q1 Q2 io1 io Co RL Q3 Q4 io2 Efficiency (%) Efficiency vs. 1.2V 12V 300kHz 5V 2MHz 85.8% Q5 Q6 io Io (A) * Two top and two bottom switches for each phase 15
16 Benefits of Low Input Voltage on / Efficiency 95% 90% 85% 80% 75% 70% 65% 1.2V/20A OUTPUT 6V input 12V input Low Voltage Device 60% fs (khz) 6V input case: 1 Si7106 (20V) + 1Si7104 (12V) 12V input case: 1 Si7112 (30V) + 2Si7112 (30V) High Efficiency, Smaller output inductor Lower noise 16
17 Improved Architecture with Single-Output SRBC 80% VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ Processor1 AC PSU 93% Eng. St. 96.5% SRBC ~11V 86% 85% 26% VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ 1.5V/ 3(6)A/ 1(2)A /ns 1.2V/ 3.6(7.2)A/ 1(2)A /ns 1.8V/ (0.65)A / (0.025)A /ns 1.3V/ (0.5)A/ (1)A /ns 3.3V/ 0.14(0.23)A/ 0.36(0.55)A /ns Processor2 Chipset D2D 5VSB Unregulated bus voltage by using high efficiency bus converter During holdup time bus voltage is regulated * M quarterly review, Oct % 96% 98.5% 86% 1.8V 12V 5V 12V 5V 3.3V 0.9V Memory HDD Other 17
18 Improved Architecture with Dual-Output SRBC AC PSU 93% 96.5% Eng. St. SRBC D2D ~5.5V 84% 86% 85% 26% VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ VID:0.95~1.7V/ 100A/ 100A/µs 1.2V/ 7.2A/ 50A/µs 3.3V/ 30mA/ 1.5V/ 3(6)A/ 1(2)A /ns 1.2V/ 3.6(7.2)A/ 1(2)A /ns 1.8V/ (0.65)A / (0.025)A /ns 1.3V/ (0.5)A/ (1)A /ns 3.3V/ 0.14(0.23)A/ 0.36(0.55)A /ns Processor1 Processor2 Chipset 5VSB ~11V High Efficiency of s 96% 96% 5V 86% 3.3V 1.8V 12V 5V 0.9V Memory HDD Large distribution loss in 5.5V voltage bus 98.5% 12V 5V 3.3V Other 18
19 Possible Future Power Architecture I-AI for Entry Level Server Isolated DCX (SRBC) ~12V Non-Isolated BCX Isolated DCX (SRBC) ~12V Non-Isolated BCX High Efficiency Lower distribution loss Flexibility 19
20 Possible Future Power Architecture I-BI for Entry Level Server Isolated DCX (SRBC) ~12V ~6V Isolated DCX (SRBC) ~12V ~6V High Efficiency Simple 20
21 Possible Future Power Architecture II for Entry Level Server 200V/400V VD 2:1 VD 2:1 200V Isolated DCX (SRBC) Isolated DCX (SRBC) ~12V ~6V ~12V ~6V High Efficiency for whole line voltage and load range 21
22 Device Comparison Part # V ds Q gd R dson FOM (Q gd *R dson ) C oss (@V ds =25V) Packaging SUM45N V 34 nc 58 mω 1.97n 300 pf D 2 PAK (TO-263) IRFP460A 500V 42 nc 270 mω 11.3n 480 pf TO-247 CoolMOS IPP60R099CS 600V 20 nc 99 mω 1.98n 130 pf (@100V) TO-220 D 2 PAK (TO-263) TO-220 TO V MOSFET has superior performance over conventional 500V MOSFET 22
23 Benefits on SRBC From 200V Bus 400V in Version D-Pak VD-MOS 100W 400KHz 12V SRBC 200V in Version Power-Pak Trench-MOS 32(16) : 1 16(8) : 1 Efficiency % 1.1% 400V SRBC 200V SRBC Io (A ) 23
24 Summary New Building Blocks from CPES are introduced Potential architectures are proposed for investigation. Observations: 1. Low output voltage of helps s efficiency 2. Low input voltage of DC/DC helps DC/DC efficiency 3. Managing the system smartly and digitally 24
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