ORDERING INFORMATION. T A PACKAGE ORDERABLE PART NUMBER MARKING PDIP N Tube SN74AHC4066N SN74AHC4066N QFN RGY Tape and reel SN74AHC4066RGYR HA4066

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1 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE V to 5.5-V Operation Supports Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low rosstalk Between Switches Individual Switch ontrols Extremely Low Input urrent ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V harged-device Model (101) description/ordering information This quadruple silicon-gate MOS analog switch is designed for 2-V to 5.5-V operation. This switch is designed to handle both analog and digital signals. Each switch permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Each switch section has its own enable-input control (). A high-level voltage applied to turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. D, DB, DGV, N, NS, OR PW PAKAGE (TOP VIEW) 1B 2B 2A 2 3 1A 1B 2B 2A RGY PAKAGE (TOP VIEW) 1A A V 1 4 4A 4B 3B 3A N No internal connection 1 4 4A 4B 3B ORDERING INFORMATION T A PAKAGE ORDERABLE TOP-SIDE PART NUMBER MARKING PDIP N Tube SN74AH4066N SN74AH4066N QFN RGY Tape and reel SN74AH4066RGYR HA4066 Tube SN74AH4066D SOI D Tape and reel SN74AH4066DR AH4066 Tube SN74AH4066NS 40 to 85 SOP NS Tape and reel SN74AH4066NSR AH4066 SSOP DB TSSOP PW Tube Tape and reel Tube Tape and reel SN74AH4066DB SN74AH4066DBR SN74AH4066PW SN74AH4066PWR HA4066 HA4066 TVSOP DGV Tape and reel SN74AH4066DGVR HA4066 Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2003, Texas Instruments Incorporated POST OFFIE BOX DALLAS, TEXAS

2 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 FUNTION TABLE (each switch) INPUT ONTROL SWITH () L OFF H ON logic diagram (positive logic) A B One of Four Switches absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, (see Note 1) V to 7 V Input voltage range, V I (see Note 1) V to 7 V Switch I/O voltage range, V IO (see Notes 1 and 2) V to V ontrol-input clamp current, I IK (V I < 0) ma I/O diode current, I IOK (V IO < 0 or V IO > ) ±50 ma On-state switch current, I T (V IO = 0 to ) ±25 ma ontinuous current through or ±50 ma Package thermal impedance, θ JA (see Note 3): D package /W (see Note 3): DB package /W (see Note 3): DGV package /W (see Note 3): N package /W (see Note 3): NS package /W (see Note 3): PW package /W (see Note 4): RGY package /W Storage temperature range, T stg to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD POST OFFIE BOX DALLAS, TEXAS 75265

3 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 recommended operating conditions (see Note 5) MIN MAX UNIT Supply voltage V V IH V IL High-level input voltage, control inputs Low-level input voltage, control inputs = 2 V 1.5 = 2.3 V to 2.7 V 0.7 = 3 V to 3.6 V 0.7 = 4.5 V to 5.5 V 0.7 = 2 V 0.5 = 2.3 V to 2.7 V 0.3 = 3 V to 3.6 V 0.3 = 4.5 V to 5.5 V 0.3 V I ontrol input voltage V V IO Input/output voltage 0 V = 2.3 V to 2.7 V 200 Δt/Δv Input transition rise or fall rate = 3 V to 3.6 V 100 ns/v = 4.5 V to 5.5 V 20 T A Operating free-air temperature With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. Only digital signals should be transmitted at these low supply voltages. NOTE 5: All unused inputs of the device must be held at or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS Inputs, literature number SBA004. V V POST OFFIE BOX DALLAS, TEXAS

4 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) T A = 25 PARAMETER TEST ONDITIONS MIN TYP MAX MIN MAX UNIT I T = 1 ma, 2.3 V On-state V r I = or, on 3 V Ω switch resistance V =V IH (see Figure 1) 4.5 V I = V Peak T ma, r on(p) V = 3 V on-state resistance I to, Ω V = V IH 4.5 V Δr on Difference in on-state resistance between switches I T = 1 ma, 2.3 V V I = to, 3 V Ω V = V IH 4.5 V I I ontrol input current V I = 5.5 V or 0 to 5.5 V ±0.1 ±1 μa I S(off) I S(on) Off-state switch leakage current On-state switch leakage current V I = and V O =, or V I = and V O =, V = V IL (see Figure 2) V I = or, V = V IH (see Figure 3) 5.5 V ±0.1 ±1 μa 5.5 V ±0.1 ±1 μa I Supply current V I = or 5.5 V 20 μa ic io F ontrol input capacitance Switch input/output capacitance Feed-through capacitance 1.5 pf 5.5 pf 0.5 pf 4 POST OFFIE BOX DALLAS, TEXAS 75265

5 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH switching characteristics over recommended operating free-air temperature range, = 2.5 V ± 0.2 V (unless otherwise noted) SLS511 JUNE 2003 t PLH t PHL t PZH t PZL t PLZ t PHZ t PLH t PHL t PZH t PZL t PLZ t PHZ PARAMETER Propagation delay time Switch turn-on time Switch turn-off time Propagation delay time Switch turn-on time Switch turn-off time FROM TO TEST T A = 25 (INPUT) (OUTPUT) ONDITIONS MIN TYP MAX B or A B or A L = 15 pf, (see Figure 4) L = 15 pf, R L = 1 kω (see Figure 5) L = 15 pf, R L = 1 kω (see Figure 5) L = 50 pf, (see Figure 4) L = 50 pf, R L = 1 kω (see Figure 5) L = 50 pf, R L = 1 kω (see Figure 5) MIN MAX UNIT ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, = 3.3 V ± 0.3 V (unless otherwise noted) t PLH t PHL t PZH t PZL t PLZ t PHZ t PLH t PHL t PZH t PZL t PLZ t PHZ PARAMETER Propagation delay time Switch turn-on time Switch turn-off time Propagation delay time Switch turn-on time Switch turn-off time FROM TO TEST T A = 25 (INPUT) (OUTPUT) ONDITIONS MIN TYP MAX B or A B or A L = 15 pf, (see Figure 4) L = 15 pf, R L = 1 kω (see Figure 5) L = 15 pf, R L = 1 kω (see Figure 5) L = 50 pf, (see Figure 4) L = 50 pf, R L = 1 kω (see Figure 5) L = 50 pf, R L = 1 kω (see Figure 5) MIN MAX UNIT ns ns ns ns ns ns POST OFFIE BOX DALLAS, TEXAS

6 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 switching characteristics over recommended operating free-air temperature range, = 5 V ± 0.5 V (unless otherwise noted) t PLH t PHL t PZH t PZL t PLZ t PHZ t PLH t PHL t PZH t PZL t PLZ t PHZ PARAMETER Propagation delay time Switch turn-on time Switch turn-off time Propagation delay time Switch turn-on time Switch turn-off time FROM TO TEST T A = 25 (INPUT) (OUTPUT) ONDITIONS MIN TYP MAX B or A B or A L = 15 pf, (see Figure 4) L = 15 pf, R L = 1 kω (see Figure 5) L = 15 pf, R L = 1 kω (see Figure 5) L = 50 pf, (see Figure 4) L = 50 pf, R L = 1 kω (see Figure 5) L = 50 pf, R L = 1 kω (see Figure 5) MIN MAX UNIT ns ns ns ns ns ns analog switch characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER Frequency response (switch on) TO FROM TEST T A = 25 (OUTPUT V (INPUT) ONDITIONS ) MIN TYP MAX UNIT L = 50 pf, R L = 600 Ω, 2.3 V 30 B or A f in = 1 MHz (sine wave) 3 V 35 MHz 20log 10 (V O /V I ) = 3 db (see Figure 6) 4.5 V 50 rosstalk (between any switches) B or A rosstalk (control input to signal output) Feed-through h attenuation ti (switch off) B or A Sine-wave distortion B or A 2.3 V 45 L = 50 pf, R L = 600 Ω, 3 V 45 db f in = 1 MHz (sine wave) (see Figure 7) 4.5 V V 15 L = 50 pf, R L = 600 Ω, 3 V 20 mv f in = 1 MHz (square wave) (see Figure 8) 4.5 V V 40 L = 50 pf, R L = 600 Ω, f in = 1 MHz 3 V 40 db (see Figure 9) 4.5 V 40 L = 50 pf, R L =10kΩ kω, V I = 2 V p-p 2.3 V 0.1 f in = 1 khz (sine wave) V I = 2.5 V p-p 3 V 0.1 % (see Figure 10) V I = 4 V p-p 4.5 V 0.1 operating characteristics, T A = 25 PARAMETER TEST ONDITIONS TYP UNIT pd Power dissipation capacitance L = 50 pf, f = 10 MHz 4.5 pf 6 POST OFFIE BOX DALLAS, TEXAS 75265

7 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH PARAMETER MEASUREMENT INFORMATION SLS511 JUNE 2003 V = V IH V I = or (ON) V O r on V I V O ma V V I V O Figure 1. On-State Resistance Test ircuit V = V IL V I A (OFF) V O ondition 1: V I = 0, V O = ondition 2: V I =, V O = 0 Figure 2. Off-State Switch Leakage-urrent Test ircuit V = V IH V I A (ON) Open V I = or Figure 3. On-State Leakage-urrent Test ircuit POST OFFIE BOX DALLAS, TEXAS

8 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 PARAMETER MEASUREMENT INFORMATION V = V IH V I (ON) V O 50 Ω L TEST IRUIT t r t f V I 90% 90% 50% 50% 10% 10% 0 V t PLH t PHL V O B or A 50% 50% VOLTAGE WAVEFORMS V OH V OL Figure 4. Propagation Delay Time, Signal Input to Signal Output 8 POST OFFIE BOX DALLAS, TEXAS 75265

9 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH PARAMETER MEASUREMENT INFORMATION SLS511 JUNE 2003 S1 50 Ω V I V V O R L = 1 kω S2 TEST S1 S2 t PZL t PZH t PLZ t PHZ L TEST IRUIT V 0 V 50% 0 V 50% t PZL t PZH V O 50% V OL V OH 0 V 50% (t PZL, t PZH ) V 0 V 50% 0 V 50% t PLZ t PHZ V O V OL V OL V V OH 0 V V OH 0.3 V (t PLZ, t PHZ ) VOLTAGE WAVEFORMS Figure 5. Switching Time (t PZL, t PLZ, t PZH, t PHZ ), ontrol to Signal Output POST OFFIE BOX DALLAS, TEXAS

10 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH SLS511 JUNE 2003 PARAMETER MEASUREMENT INFORMATION 0.1 μf VI f in (ON) V O 50 Ω R L = 600 Ω L = 50 pf /2 Figure 6. Frequency Response (Switch On) V = f in 50 Ω 0.1 μf 600 Ω V I (ON) R L = 600 Ω V O1 L = 50 pf /2 V I V = (OFF) V O2 600 Ω R L = 600 Ω L = 50 pf /2 Figure 7. rosstalk Between Any Two Switches 50 Ω V V O 600 Ω R L = 600 Ω L = 50 pf /2 /2 Figure 8. rosstalk (ontrol Input Switch Output) 10 POST OFFIE BOX DALLAS, TEXAS 75265

11 SN74AH4066 QUADRUPLE BILATERAL ANALOG SWITH PARAMETER MEASUREMENT INFORMATION SLS511 JUNE 2003 V = 0.1 μf VI f in (OFF) V O 50 Ω 600 Ω R L = 600 Ω L = 50 pf /2 /2 Figure 9. Feed-Through Attenuation (Switch Off) V = 10 μf VI 10 μf f in (ON) V O 600 Ω R L = 10 kω L = 50 pf /2 Figure 10. Sine-Wave Distortion POST OFFIE BOX DALLAS, TEXAS

12 PAKAGE OPTION ADDENDUM 24-Aug-2018 PAKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74AH4066D ATIVE SOI D Green (RoHS & no Sb/Br) SN74AH4066DBR ATIVE SSOP DB Green (RoHS & no Sb/Br) SN74AH4066DBRG4 ATIVE SSOP DB Green (RoHS & no Sb/Br) SN74AH4066DG4 ATIVE SOI D Green (RoHS & no Sb/Br) SN74AH4066DGVR ATIVE TVSOP DGV Green (RoHS & no Sb/Br) SN74AH4066DR ATIVE SOI D Green (RoHS & no Sb/Br) SN74AH4066N ATIVE PDIP N Pb-Free (RoHS) SN74AH4066NE4 ATIVE PDIP N Pb-Free (RoHS) SN74AH4066NSR ATIVE SO NS Green (RoHS & no Sb/Br) SN74AH4066NSRG4 ATIVE SO NS Green (RoHS & no Sb/Br) SN74AH4066PW ATIVE TSSOP PW Green (RoHS & no Sb/Br) SN74AH4066PWR ATIVE TSSOP PW Green (RoHS & no Sb/Br) SN74AH4066RGYR ATIVE VQFN RGY Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( ) Device Marking (4/5) U NIPDAU Level UNLIM -40 to 85 AH4066 U NIPDAU Level UNLIM -40 to 85 HA4066 U NIPDAU Level UNLIM -40 to 85 HA4066 U NIPDAU Level UNLIM -40 to 85 AH4066 U NIPDAU Level UNLIM -40 to 85 HA4066 U NIPDAU Level UNLIM -40 to 85 AH4066 U NIPDAU N / A for Pkg Type -40 to 85 SN74AH4066N U NIPDAU N / A for Pkg Type -40 to 85 SN74AH4066N U NIPDAU Level UNLIM -40 to 85 AH4066 U NIPDAU Level UNLIM -40 to 85 AH4066 U NIPDAU Level UNLIM -40 to 85 HA4066 U NIPDAU Level UNLIM -40 to 85 HA4066 U NIPDAU Level YEAR -40 to 85 HA4066 Samples (1) The marketing status values are defined as follows: ATIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

13 PAKAGE OPTION ADDENDUM 24-Aug-2018 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of hlorine (l) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDE industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus AS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to ustomer on an annual basis. Addendum-Page 2

14 PAKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74AH4066DBR SSOP DB Q1 SN74AH4066DGVR TVSOP DGV Q1 SN74AH4066DR SOI D Q1 SN74AH4066NSR SO NS Q1 SN74AH4066PWR TSSOP PW Q1 SN74AH4066RGYR VQFN RGY Q1 Pack Materials-Page 1

15 PAKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AH4066DBR SSOP DB SN74AH4066DGVR TVSOP DGV SN74AH4066DR SOI D SN74AH4066NSR SO NS SN74AH4066PWR TSSOP PW SN74AH4066RGYR VQFN RGY Pack Materials-Page 2

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20 MEHANIAL DATA MPDS006 FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTI SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDE: 24/48 Pins MO /16/20/56 Pins MO-194 POST OFFIE BOX DALLAS, TEXAS 75265

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25 MEHANIAL DATA MSSO002E JANUARY 1995 REVISED DEEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTI SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDE MO-150 POST OFFIE BOX DALLAS, TEXAS 75265

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