Introduction. Features. Applications

Transcription

1 70-70/70P T/S/R-L Features Precision supply-voltage monitor -.V (70L/70, L, 70L/707) -.V (70M/70, M, 70M/70) -.0V (70T, T, 70T) -.9V (70S, S, 70S) -.V (70R, R/70P, 70R) -.V (70Z, Z, 70Z) -.0V (70Y, Y, 70Y) 00ms reset pulse width Debounced TTL/CMOS-compatible manualreset input Independent watchdog timer.sec time-out (not available for 707/70/70T/70S/R/Z/Y) Reset output signal: - Active-low only (70/70/70T/S/R/Z/Y) - Active-high only (L/M/T/S/R/70P) - Active-high and active-low (707/70/70T/S/R) Voltage monitor for power-fail or low battery warning Guaranteed / valid at V CC =.V Introduction The 70X/X/70X family microprocessor (µp) supervisory circuits are targeted to improve reliability and accuracy of power-supply circuitry in µp systems. These devices reduce the complexity and number of components required to monitor powersupply and battery functions. The main functions are:. Asserting reset output during power-µp, powerdown and brownout conditions for µp system;. Detecting power failure or low-battery conditions with a.v threshold detector;. Watchdog functions (not for 70x). Applications Power-supply circuitry in µp systems

2 70-70/70P T/S/R-L Contents Features... Block Diagram... Introduction... Pin Information... Pin Configuration... Pin Description... Functional Description... Reset Output... Watchdog Timer... Manual Reset... Power-Fail Comparator... Function Reference Table... Detailed Specifications... 7 Absolute Maximum Ratings... 7 Recommended Operation Condition... 7 DC Electrical Characteristics... AC Electrical Characteristics... 9 Ordering Information... 0 Mechanical Information... Notes...

3 70-70/70P T/S/R-L Block Diagram Figure. Block Diagram of 70X/707, X/70P Watchdog WDI Watchdog Timer Transition Detector 0uA Timebase for Reset & Watchdog Reset Generator *70X ( *X,70P) V RST.V Figure. Block Diagram of 70X / 707 0uA Reset Generator V RST.V

4 70-70/70P T/S/R-L Pin Information Pin Configuration Figure. Pin Configuration 70L/M/T/S/RESA 70L/M/T/S/REPA -Pin SOIC/-Pin PDIP L/M/T/S/R/70PESA L/M/T/S/R/70PEPA -Pin SOIC/-Pin PDIP 70L/M/T/S/RESA 70L/M/T/S/REPA -Pin SOIC/-Pin PDIP V CC 7 V CC 7 V CC 7 WDI WDI NC Top View Pin Description Table. Pin Description P in Name WDI NC T yp e I Power Ground I O I O O Descriptio n M anual-reset: t riggers a reset pulse when pulled below 0.V, active low. It has an internal 0µA pull-up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch. Power Suppl y G round Referenc e for all signals P ower-fail Voltage Monitor Inpu t: When is less than.v, goes low. Connect to or when not used. P ower-fail Output: it gets low and sinks current when is less than.v; otherwise stays high. W atchdog Inpu t: If WDI remains high or low for.sec, the internal watchdog timer runs out and goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted. WDI is three- stated, or WDI sees a rising or falling edge. No Connect R eset Output pulses: low for 00ms when triggered, and stays low whenever is below the reset threshold. It remains low for 00ms after rises above the reset threshold or goes from low to high. A watchdog timeout will not trigger unless is connected to. W atchdog Output t: pulls low when the internal watchdog timer finishes its.sec count and does not go high again until the watchdog is cleared. also goes low during low-line conditions. Whenever is below the reset threshold, stays low; however, unlike, does not have minimum pulse width. As soon as rises above the reset threshold, goes high with no delay. O T he inverse of RES E T: active high. Whenever is high, is low.

5 70-70/70P T/S/R-L Functional Description The xxx family can assert reset output during power-up, power-down and brownout conditions for up system, detect power failure or low-battery conditions with a.v threshold detector and have watchdog functions. Refer to Table for their individual features. The typical application see Figure. Reset Output The supervisory circuits can assert reset for a microprocessor during power-up, power-down and brownout to prevent code execution errors. On power-up, once V CC reaches about.v, is a guaranteed logic low of 0.V or less. As V CC rises, stays low. When V CC rises above the reset threshold, an internal timer releases after about 00ms. pulses low whenever V CC drops below the reset threshold (brownout condition). If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 0ms. On power-down, once V CC falls below the reset threshold, stays low and is guaranteed to be 0.V or less until drops below V. The x and 70P active-high output is simply the complement of the output, and is guaranteed to be valid with V CC down to.v. Some µps, such as Intel s 0C, require an active-high reset pulse. Figure. Typical Application Circuit Watchdog Timer The watchdog circuit monitors the µp s activity. If the µp does not toggle the watchdog input (WDI) within.sec and WDI is not in high impedance, goes low. As long as is asserted or the WDI input is in high impedance, the watchdog timer will stay cleared and will not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as short as 0ns can be detected. Typically, will be connected to the non-maskable interrupt input (NMI) of a µp. When V CC drops below the reset threshold, will go low whether or not the watchdog timer has timed out yet. Normally this would trigger an NMI interrupt, but goes low simultaneously, and thus overrides the NMI interrupt. If WDI is left unconnected, can be used as a low-line output. Since floating WDI disables the internal timer, goes low only when V CC falls below the reset threshold, thus functioning as a low-line output. Manual Reset The manual-reset input () allows reset to be triggered by a push-button switch. The switch is effectively debounced by the 0ms minimum reset pulse width. is TTL/CMOS logic compatible, so it can be driven by any logic reset output. Power-Fail Comparator The power-fail comparator will send out a Low signal once detects a voltage lowered than.v. It can be used for various purposes because its output and non-inverting input are not internally connected. The inverting input is internally connected to a.v reference. IN DC Linear Regulator OUT µp µp Supervisory Circuit WDI I/O Line NMI Interrupt

6 70-70/70P T/S/R-L Function Reference Table Table. Function Table of PT7A7xx Family Part No. Reset Threshold Reset Active Low or High Nom. Reset Time (ms), t RS Nom. Watch dog Time (sec), t WD Power Fail Comp. Manual Reset Input 70L/70.V LOW 00..V detector Yes L.V HIGH 00..V detector Yes 70L/707.V LOW, HIGH 00 unavailable.v detector Yes 70M/70.V LOW 00..V detector Yes M.V HIGH 00..V detector Yes 70M/70.V LOW, HIGH 00 unavailable.v detector Yes 70T.0V LOW 00..V detector Yes T.0V HIGH 00..V detector Yes 70T.0V LOW, HIGH 00 unavailable.v detector Yes 70S.9V LOW 00..V detector Yes S.9V HIGH 00..V detector Yes 70S.9V LOW, HIGH 00 unavailable.v detector Yes 70R.V LOW 00..V detector Yes R/70P.V HIGH 00..V detector Yes 70R.V LOW, HIGH 00 unavailable.v detector Yes 70Z.V LOW 00..V detector Yes Z.V HIGH 00..V detector Yes 70Z.V LOW, HIGH 00 unavailable.v detector Yes 70Y.0V LOW 00..V detector Yes Y.0V HIGH 00..V detector Yes 70Y.0V LOW, HIGH 00 unavailable.v detector Yes

7 70-70/70P T/S/R-L Mechanical Information Figure 7. -Pin SOIC