MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, TTL, FLIP-FLOPS, MONOLITHIC SILICON. Inactive for new design after 7 September 1995.

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1 INC POUND MI-M-38510/17 3 May 2005 SUPERSEDING MI-M-38510/17(USF) 1 May 1979 MIITRY SPECIFICTION MICROCIRCUITS, DIGIT, TT, FIP-FOPS, MONOITIC SIICON This specification is approved for use by all Departments and gencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MI-PRF SCOPE Inactive for new design after 7 September Scope. This specification covers the detail requirements for monolithic, silicon, TT, bistable logic gating microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MI-M have been superseded by MI-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MI-PRF-38535, and as specified herein Device types. The device types are as follows: Device type Circuit 01 ex, D-type, positive edge triggered flip-flops with clear and single outputs 02 Quad, D-type, positive edge triggered flip-flops with clear and complementary outputs Device class. The device class is the product assurance level as defined in MI-PRF Case outlines. The case outlines are as designated in MI-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat-pack Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, TTN: DSCC-VS, P. O. ox 3990, Columbus, O , or ed to bipolar@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the SSIST Online database at MSC N/ FSC 5962

2 MI-M-38510/ bsolute maximum ratings. Supply voltage range V dc to +7.0 V dc Input voltage range V dc at -12 m to +5.5 V dc Storage temperature range C to +150 C Maximum power dissipation per flip-flop, (P D ) 1/ Device type mw Device type mw ead temperature (soldering 10 seconds) C Thermal resistance, junction-to-case (θ JC )... (See MI-STD-1835) Junction temperature (T J ) 2/ C 1.4 Recommended operating conditions. Supply voltage V dc minimum to 5.5 V dc maximum Minimum high level input voltage V dc Maximum low level input voltage V dc Normalized fanout (each output) 3/ maximum Case operating temperature range (T C ) C to 125 C Input setup time Data input ns Clear inactive state ns Input hold time... 5 ns 2.0 PPICE DOCUMENT 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents Specifications and standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPRTMENT OF DEFENSE SPECIFICTIONS MI-PRF Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPRTMENT OF DEFENSE STNDRDS MI-STD Test Method Standard for Microelectronics. MI-STD Interface Standard Electronic Component Case Outlines (Copies of these documents are available online at or or from the Standardization Document Order Desk, 700 Robbins venue, uilding 4D, Philadelphia, P ) 1/ Must withstand the added P D due to short circuit condition (e.g. I OS ). 2/ Maximum junction temperature should not be exceeded except in accordance with allowable short duration burn-in screening condition in accordance with MI-PRF / Device will fanout in both high and low levels to the specified number of inputs of the same device type as that being tested. 2

3 MI-M-38510/ Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MI-PRF and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MI-PRF and herein ogic diagram and terminal connections. The logic diagram terminal connections shall be as specified on figure 1 and 2, respectively Truth tables and logic equations. The truth tables and logic equations shall be as specified on figure Schematic circuit. The schematic circuit shall be maintained by the manufacturer and made available to the qualifying activity and the preparing activity upon request Case outlines. Case outlines shall be as specified in ead material and finish. ead material and finish shall be in accordance with MI-PRF (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table 1 and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements for each device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MI-PRF Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 3 (see MI-PRF-38535, appendix ). 3

4 MI-M-38510/17 Test TE I. Electrical performance characteristics. Symbol igh-level output voltage V O V CC = 4.5 V; I O = -800 µ Conditions 1/ -55 C T C +125 C unless otherwise specified Device imits Unit type Min Max ll 2.4 V ow-level output voltage V O V CC = 4.5 V; I IN = 16 m ll 0.4 V Input clamp voltage V IC V CC = 4.5 V; I IN = -12 m; ll -1.5 V T C = 25 C ow-level input current I I1 V CC = 5.5 V; V IN = 0.4 V 2/ ll m I I2 V CC = 5.5 V; V IN = 0.4 V 3/ ll m I I3 V CC = 5.5 V; V IN = 0.4 V 4/ ll m igh-level input current I I1 V CC = 5.5 V; V IN = 2.4 V ll 40 µ I I2 V CC = 5.5 V; V IN = 5.5 V ll 100 µ Short-circuit output current I OS V CC = 5.5 V; V IN = 0 ll m Supply current per device I CC V CC = 5.5 V; V IN = 5.5 V m m Maximum clock frequency f MX V CC = 5 V; ll 25 Mz C = 50 pf ± 10% Propagation delay to high logic level (clear to Q) t P1 R = 390 Ω ± 5% ns Propagation delay to low logic level (clear to Q) Propagation delay to high logic level (clock to Q) Propagation delay to low logic level (clock to Q) Propagation delay to high logic level (clock to Q) Propagation delay to low logic level (clock to Q) t P1 ll 5 50 ns t P2 ll 5 43 ns t P2 ll 5 43 ns t P ns t P3 1/ See table III for complete terminal conditions. 2/ Clock input for device types 01 and 02. 3/ Clear input for device types 01 and 02. 4/ ll D inputs for device types 01 and ns 4

5 MI-M-38510/17 TE II. Electrical test requirements. MI-PRF Test requirement Interim electrical parameters Subgroups (see table III) Class S Devices Class Devices 1 1 Final electrical test parameters 1*, 2, 3, 7, 9, 10, 11 Group test requirements 1, 2, 3, 7, 8, 9, 10, 11 Group electrical test parameters when using the method 5005 QCI option 1, 2, 3, 9, 10, 11 Groups C end point electrical parameters 1, 2, 3, 9, 10, 11 1*, 2, 3, 7, 9 1, 2, 3, 7, 9, N/ 1, 2, 3 dditional electrical subgroups for Group C periodic inspections None 10, 11 Group D end point electrical parameters 1, 2, 3 1, 2, 3 *PD applies to subgroup VERIFICTION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MI-PRF or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. 4.2 Qualification inspection. Qualification inspection shall be in accordance with MI-PRF Screening. Screening shall be in accordance with MI-PRF and shall be conducted on all devices prior to qualification and conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MI-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review oard (TR) in accordance with MI-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MI-STD-883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. dditional screening for space level product shall be as specified in MI-PRF

6 MI-M-38510/ Technology Conformance Inspection (TCI). Technology conformance inspection shall be in accordance with MI-PRF and herein for groups,, C, and D inspections (see through 4.4.4) Group inspection. Group inspection shall be in accordance with table III of MI-PRF and as follows: a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, and 6, shall be omitted Group inspection. Group inspection shall be in accordance with table II of MI-PRF Group C inspection. Group C inspection shall be in accordance with table IV of MI-PRF and as follows: a. End point electrical parameters shall be as specified in table II herein. b. Subgroups 3 and 4 shall be added to the group C inspection requirements for class devices and shall consist of the tests, conditions, and limits specified for subgroups 10 and 11 of group. c. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MI-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review oard (TR) in accordance with MI-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MI-STD Group D inspection. Group D inspection shall be in accordance with table V of MI-PRF End-point electrical parameters shall be as specified in table II herein. 4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows: Voltage and current. ll voltages given are referenced to the microcircuit ground terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 6

7 MI-M-38510/17 Figure 1. ogic diagrams. 7

8 MI-M-38510/17 Figure 1. ogic diagrams - Continued. 8

9 MI-M-38510/17 Terminal number Device type 01 Cases E and F Device type 02 Cases E and F 1 CER CER 2 1Q 1Q 3 1D 1 Q 4 2D 1D 5 2Q 2D 6 3D 2 Q 7 3Q 2Q 8 GND GND 9 COCK COCK 10 4Q 3Q 11 4D 3 Q 12 5Q 3D 13 5D 4D 14 6D 4 Q 15 6Q 4Q 16 V CC V CC Figure 2. Terminal connections. 9

10 MI-M-38510/17 Truth table for each flip-flop CER COCK D Q Q * X** X X Q0 Q0 * Device type 02 only. ** Input may be high, low or open circuit. NOTE: Clear is independent of clock. Information at the D input meeting the setup time requirements is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive going pulse. When the clock input is either high or low level, the D input signal has no effect at the output. FIGURE 3. Truth table. 10

11 MI-M-38510/17 NOTES: 1. Clock input has the following characteristics: Vgen = 3 V minimum, t P = 20 ns, t T = t T 10 ns, and PRR 1 Mz. When testing f MX PRR = 25 Mz. 2. D input pulse has the following characteristics: Vgen = 3 V minimum, t T = t T 10 ns, t P = 30 ns, t SETUP = 25 ns, t OD = 5 ns and PRR 0.5 Mz. When testing f MX PRR = 12.5 Mz at 50% ± 15% duty cycle. 3. R = 390 Ω ± 5%; C = 50 pf ± 10% (including jig and probe capacitance). 4. ll diodes are 1N3064 or equivalent. 5. Q output applies to device type 02 only. Figure 4. Synchronous switching test circuit (high level data) for device types 01 and

12 MI-M-38510/17 NOTES: 1. Clock input has the following characteristics: Vgen = 3 V minimum, t P = 20 ns, t T = t T 10 ns, and PRR 1 Mz. When testing f MX PRR = 25 Mz. 2. D input pulse has the following characteristics: Vgen = 3 V minimum, t T = t T 10 ns, t P = 30 ns, t SETUP = 25 ns, t OD = 5 ns and PRR 0.5 Mz. When testing f MX PRR = 12.5 Mz at 50% ± 15% duty cycle. 3. R = 390 Ω ± 5%; C = 50 pf ± 10% (including jig and probe capacitance). 4. ll diodes are 1N3064 or equivalent. 5. Q output applies to device type 02 only. Figure 5. Synchronous switching test circuit (low level data) for device types 01 and

13 MI-M-38510/17 NOTES: 1. Clock input pulse is a preconditioning pulse and has the following characteristics: Vgen = 3 V minimum, t P 100 ns, t SETUP = 25 ns, and PRR 1 Mz. 2. Clear input pulse has the following characteristics: Vgen = 3 V minimum, t T = t T 10 ns, t P = 30 ns, and PRR 1 Mz. 4. ll diodes are 1N3064 or equivalent. 3. R = 390 Ω ± 5%; C = 50 pf ± 10% (including jig and probe capacitance). Figure 6. Clear switching test circuit and waveforms for device type

14 MI-M-38510/17 NOTES: 1. Clock input pulse is a preconditioning pulse and has the following characteristics: Vgen = 3 V minimum, t P 100 ns, t SETUP = 25 ns, and PRR 1 Mz. 2. Clear input pulse has the following characteristics: Vgen = 3 V minimum, t T = t T 10 ns, t P = 30 ns, and PRR 1 Mz. 4. ll diodes are 1N3064 or equivalent. 3. R = 390 Ω ± 5%; C = 50 pf ± 10% (including jig and probe capacitance). Figure 7. Clear switching test circuit and waveforms for device type

15 TE III. Group inspection for device type 01. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 15 Subgroup Symbol 1 T C = 25 C V IC V O V O MI- STD-883 method I I I I2 I I2 Case E & F Meas. Test limits Test No. Clear 1Q 1D 2D 2Q 3D 3Q GND Clock 4Q 4D 5Q 5D 6D 6Q V CC terminal Min Max Unit CKT,C,D 21 CKT 21 CKT E 22 CKT,D,E 22 CKT,C m 2.0V 0.8V 0.4V 0.4V -12m -.8m 2.0V 16m -12m 2.0V -.8m 16m -12m 2.0V -.8m 16m GND -12m 0.4V 0.4V 0.4V -12m -.8m 2.0V 16m -12m -.8m 2.0V 16m -12m 2.0V -.8m I I3 0.4V V 0.4V 0.4V 0.4V I I V 2.4V 2.4V 2.4V 2.4V 2.4V 2.4V 2.4V I I V Clear V 1D V 2D V 3D V Clock V 4D V 5D V 6D I OS V GND 5.5V 1Q V GND 2Q V GND 3Q 48 GND 5.5V 4Q 49 GND 5.5V 5Q V GND 6Q I CC V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V V CC 65 16m 4.5V 5.5V Clear 1D 2D 3D Clock 4D 5D 6D 1Q 2Q 3Q 4Q 5Q 6Q 1Q 2Q 3Q 4Q 5Q 6Q Clock Clock Clock Clear Clear 1D 2D 3D 4D 5D 6D Clear 1D 2D 3D Clock 4D 5D 6D V m µ µ m MI-M-38510/17 See notes at end of device type 01.

16 TE III. Group inspection for device type 01. Continued. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 16 Subgroup Symbol MI-STD- 883 method Case E & F Meas. Test limits Test No. Clear 1Q 1D 2D 2Q 3D 3Q GND Clock 4Q 4D 5Q 5D 6D 6Q V CC terminal Min Max Unit 2 Same tests, terminal conditions and limits as subgroup 1, except T C = 125 C and V IC tests are omitted. 3 Same tests, terminal conditions and limits as subgroup 1, except T C = -55 C and V IC tests are omitted. 7 2/ 4/ T C = 25 C Truth table test / 4/ Repeat subgroup 7 at T C = 125 C and T C = -55 C. 9 T C = 25 C f MX 5/ (Fig 4) V 10 T C = 125 C t P1 t P2, t P2 f MX 5/ t P1 t P2, t P (Fig 6) 3003 (Fig 4 & 5) (Fig 4) 3003 (Fig 6) 3003 (Fig 4 & 5) & & & & & & & & & & & & 112 IN 5.0 V 5.0 V IN 5.0 V OUT 5.0 V OUT 5.0 V IN OUT 5.0 V OUT IN OUT IN OUT 5.0 V OUT IN OUT 11 Same tests, terminal conditions and limits as subgroup 10, except T C = -55 C. IN OUT 5.0 V OUT IN IN OUT OUT 5.0 V OUT IN OUT GND GND IN OUT 5.0 V OUT 5.0 V OUT 5.0 V OUT 5.0 V IN OUT 5.0 V OUT IN IN OUT OUT 5.0 V OUT IN OUT 5.0 V 5.0 V ll outputs 1Q 2Q 3Q 4Q 5Q 6Q Clear-1Q Clear-2Q Clear-3Q Clear-4Q Clear-5Q Clear-6Q Clock-1Q Clock-2Q Clock-3Q Clock-4Q Clock-5Q Clock-6Q 1Q 2Q 3Q 4Q 5Q 6Q Clear-1Q Clear-2Q Clear-3Q Clear-4Q Clear-5Q Clear-6Q Clock-1Q Clock-2Q Clock-3Q Clock-4Q Clock-5Q Clock-6Q / Mz ns Mz ns MI-M-38510/17

17 TE III. Group inspection for device type 01. Continued. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 1/ = Momentary GND, then V CC. 2/ The tests in subgroups 7 and 8 shall be performed in the sequence specified. 3/ Output voltages shall be either: (a) = 2.4 V minimum and = 0.4 V maximum when using a high-speed checker double comparator, or (b) > 1.5 V and < 1.5 V when using a high-speed checker single comparator. 4/ Only a summary of attributes data is required. 5/ f MX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency. MI-M-38510/17 17

18 TE III. Group inspection for device type 02. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 18 Subgroup Symbol MI- Case E & F Meas. Test limits STD-883 Test No. Clear 1Q method 1 Q 1D 2D 2 Q 2Q GND Clock 3Q 3 Q 3D 4D 4 Q 4Q V terminal CC Min Max Unit 1 V I C 1-12 m GND 4.5 V Clear -1.5 V T C = 25 C " 2-12 m " " 1D " " " 3-12 m " " 2D " " " 4 " -12 m " Clock " " " 5 " -12 m " 3D " " " 6 " -12 m " 4D " " V O V -.8 m 2.0 V " " 1Q 2.4 " " " 8 " 2.0 V -.8 m 2Q " " " " m 2.0 V " 3Q " " " " V -.8 m " 4Q " " " " V -.8 m " " 1 Q " " " " 12 " -.8 m " " 2 Q " " " " 13 " " -.8 m " 3 Q " " " " 14 " " -.8 m " 4 Q " " V O " V 16 m 2.0 V " " 1 Q 0.4 V " " " 16 " 2.0 V 16 m 2 Q " " " " m 2.0 V " 3 Q " " " " V 16 m " 4 Q " " " " V 16 m " " 1Q " " " " 20 " 16 m " " 2Q " " " " 21 " " 16 m " 3Q " " " " 22 " " 16 m " 4Q " " I I CKT,C,D " 0.4 V 5.5 V Clock m " " 23 CKT " 0.4 V " Clock " " " 23 CKT E " 0.4 V " Clock " I I2 " 24 CKT,D,E 0.4 V " " Clear " I I2 " 24 CKT,C 0.4 V " " Clear " I I3 " V " " 1D " " " V " " 2D " " 27 " 0.4 V " 3D " " 28 " 0.4 V " 4D I I V " " Clear 40 µ " " V " " 1D " " " " V " " 2D " " " " 32 " 2.4 V " Clock " " " " 33 " 2.4 V " 3D " " " " 34 " 2.4 V " 4D " " I I2 " V " " Clear 100 " " " V " " 1D " " " " V " " 2D " " " " 38 " 5.5 V " Clock " " " " 39 " 5.5 V " 3D " " " " 40 " 5.5 V " 4D " " MI-M-38510/17 See notes at end of device type 02.

19 TE III. Group inspection for device type 02. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 19 Subgroup Symbol MI- Case E & F Meas. Test limits STD-883 Test No. Clear 1Q method 1 Q 1D 2D 2 Q 2Q GND Clock 3Q 3 Q 3D 4D 4 Q 4Q V terminal CC Min Max Unit 1 I OS V GND 5.5 V GND 5.5 V 1Q m T C = 25 C " " 42 " 5.5 V GND 2Q " " 43 GND 5.5 V " 3Q " " V GND " 4Q " " 45 GND GND " " 1 Q " " 46 " GND " " 2 Q " " 47 " " GND " 3 Q " " 48 " " GND " 4 Q I CC V 5.5 V 5.5 V 5.5 V 5.5 V V CC 45 " 2 Same tests, terminal conditions and limits as subgroup 1, except T C = 125 C and V IC tests are omitted. 3 Same tests, terminal conditions and limits as subgroup 1, except T C = -55 C and V IC tests are omitted. 7 2/ 4/ I OS GND 5.0 V ll T C = 25 C " " 51 " " outputs " " 52 " " " " " 53 " " " " " 54 " " " " " " " " " " 55 " " " " " " " " " " 56 " " " " 3/ " " 57 " " " " " " 58 " " " " " " 59 " " " " " " 60 " " " " " " " " " " 61 " " " " " " " " " " 62 " " " " " " " 8 2/ 4/ Repeat subgroup 7 at T C = 125 C and T C = -55 C. 9 f MX Fig V GND IN 5.0 V 1Q 25 Mz T C = 25 C 5/ " 64 " IN OUT 2Q " " " " 65 " 3Q " " " " 66 IN OUT " 4Q " " t P IN OUT 5.0 V Clear-1 Q 5 28 ns " Fig 7 68 " 5.0 V OUT Clear-2 Q " " 69 OUT 5.0 V " Clear-3 Q " " V OUT " Clear-4 Q t P1 " 71 " OUT 5.0 V Clear-1Q " 38 " " " 72 " 5.0 V OUT Clear-2Q " " 73 OUT 5.0 V " Clear-3Q " " V OUT " Clear-4Q t P2, & V Clock-1Q " 33 " t P2 Fig 4 & 5 77 & 78 " IN OUT Clock-2Q " " 79 & 80 " Clock-3Q " " 81 & 82 IN OUT " Clock-4Q t P3, " 83 & 84 " Clock-1 Q t P3 " 85 & 86 " IN OUT Clock-2 Q " " 87 & 88 " Clock-3 Q " " 89 & 90 IN OUT " Clock-4 Q MI-M-38510/17 See notes at end of device type 02.

20 TE III. Group inspection for device type 02. Terminal conditions (pins not designated may be high 2.0V or low 0.8 V or open). 20 Subgroup Symbol MI- Case E & F Meas. Test limits STD-883 Test No. Clear 1Q method 1 Q 1D 2D 2 Q 2Q GND Clock 3Q 3 Q 3D 4D 4 Q 4Q V terminal CC Min Max Unit 10 f MX Fig V GND IN 5.0 V 1Q 25 Mz T C = 125 C 5/ " 92 " IN OUT 2Q " " " " 93 " 3Q " " " " 94 IN OUT " 4Q " " t P IN OUT 5.0 V Clear-1 Q 5 36 ns " Fig 7 96 " 5.0 V OUT Clear-2 Q " " 97 OUT 5.0 V " Clear-3 Q " " V OUT " Clear-4 Q t P1 " 99 " OUT 5.0 V Clear-1Q " 50 " " " 100 " 5.0 V OUT Clear-2Q " " 101 OUT 5.0 V " Clear-3Q " " V OUT " Clear-4Q t P2, & V Clock-1Q " 43 " t P2 Fig 4 & & 106 " IN OUT Clock-2Q " " 107 & 108 " Clock-3Q " " 109 & 110 IN OUT " Clock-4Q t P3, " 111 & 112 " Clock-1 Q t P3 " 113 & 114 " IN OUT Clock-2 Q " " 115 & 116 " Clock-3 Q " " 117 & 118 IN OUT " Clock-4 Q 11 Same tests, terminal conditions and limits as subgroup 10, except T C = -55 C. 1/ = Momentary GND, then V CC. 2/ The tests in subgroups 7 and 8 shall be performed in the sequence specified. 3/ Output voltages shall be either: (a) = 2.4 V minimum and = 0.4 V maximum when using a high speed checker double comparator, or (b) > 1.5 V and < 1.5 V when using a high speed checker single comparator. 4/ Only a summary of attributes data is required. 5/ f MX minimum limit specified is the frequency of the input pulse. The output frequency shall be one half of the input frequency. MI-M-38510/17

21 MI-M-38510/17 5. PCKGING 5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see 6.2). When packaging of materiel is to be performed by DoD or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. Packaging requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense gency, or within the military service's system command. Packaging data retrieval is available from the managing Military Department's or Defense gency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity. 6. NOTES (This section contains information of a general or explanatory nature that may be helpful, but it is not mandatory) 6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing equipment. 6.2 cquisition requirements. cquisition documents should specify the following: a. Title, number, and date of the specification. b. PIN and compliance identifier, if applicable (see 1.2). c. Requirements for delivery of one copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. Requirement for certificate of compliance, if applicable. e. Requirements for notification of change of product or process to acquiring activity in addition to notification to the qualifying activity, if applicable. f. Requirements for failure analysis (including required test condition of method 5003), corrective action and reporting of results, if applicable. g. Requirements for product assurance options. h. Requirements for carriers, special lead lengths or lead forming, if applicable. These requirements shall not affect the part number. Unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the Government. i. Requirements for "JN" marking. j. Packaging requirements (see 5.1). 6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers ist QM whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. road Street, Columbus, Ohio Superseding information. The requirements of MI-M have been superseded to take advantage of the available Qualified Manufacturer isting (QM) system provided by MI-PRF Previous references to MI-M in this document have been replaced by appropriate references to MI-PRF ll technical requirements now consist of this specification and MI-PRF The MI-M specification sheet number and PIN have been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists. 6.5 bbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined in MI-PRF and MI-DK-1331, and as follows: GND... Electrical ground (common terminal) V IN... Voltage level at an input terminal 21

22 MI-M-38510/ ogistic support. ead materials and finishes (see 3.3) are interchangeable. Unless otherwise specified, microcircuits acquired for Government logistic support will be acquired to device class (see 1.2.2), lead material and finish (see 3.4). onger lead lengths and lead forming shall not affect the part number. 6.7 Substitutability. The cross-reference information below is presented for the convenience of users. Microcircuits covered by this specification will functionally replace the listed generic-industry type. Generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to MI-M device types and may have slight physical variations in relation to case size. The presence of this information should not be deemed as permitting substitution of generic-industry types for MI-M types or as a waiver of any of the provisions of MI-PRF Device type Commercial type Manufacturers" designations. Manufacturers" circuits included in this specification are designated as shown in table IV. Device type National Semiconductor Table IV. Manufacturers" designations Texas Instruments Signetics Motorola Inc. Fairchild Circuits C D E 01 X X X X X 02 X X X X X 6.9 Changes from previous issue. Marginal notations are not used in this revision to identify changes with respect to the previous issue due to the extensiveness of the changes. Custodians: Preparing activity: rmy - CR D - CC Navy - EC ir Force - 11 (Project ) D - CC Review activities: rmy - MI, SM Navy - S, CG, MC, S, TD ir Force - 03, 19, 99 NOTE: The activities listed above were interested in this document as of the date of this document. Since organizations and responsibilities can change, you should verify the currency of the information above using the SSIST Online database at 22