Tema 12 Transistores. 12.a. El transistor bipolar 12.b. El transistor MOS

Transcription

1 Tema 12 Transistores. 12.a. El transistor bipolar 12.b. El transistor MOS 1

2 Capítulo12.a El Transistor Bipolar 2

3 El transistor bipolar de unión, BT, npn Figure 5.1 A simplified structure of the npn transistor. Fifth Edition 3

4 El transistor bipolar de unión, BT, pnp Figure 5.2 A simplified structure of the pnp transistor. Fifth Edition 4

5 Símbolos Figure 5.13 Circuit symbols for BTs. Microelectronic Circuits 5- Fifth Edition 5

6 El transistor BT npn en zona activa directa Figure 5.3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current components due to drift of thermally generated minority carriers are not shown.) Fifth Edition 6

7 Distribución de portadores minoritarios Figure 5.4 Profiles of minority-carrier concentrations in the base and in the emitter of an npn transistor operating in the active mode: v 0 and v CB 0. Fifth Edition 7

8 Corrientes de portadores Proporción de minoritarios que consigue atravesar la base na BC FI nd nae BC FI pd nd Flujos de carga proporcionales a la distribución de Maxwell-Boltzmann: d pd nd pde e qv KT nde e qv KT Corriente en la unión : 0 d d Corriente en la unión CB: CB a a 0 e qv qvcb 0 KT BC e 1 KT 1 F (Corriente diodo directa) 8

9 9 Circuito equivalente en zona activa directa F BC F C B F B F F C E C B F E F C C B E I I I I I I I I I I I I I I I I 1 0

10 Curva característica del BT npn Figure 5.19 (a) Conceptual circuit for measuring the i C v CE characteristics of the BT. (b) The i C v CE characteristics of a practical BT. Fifth Edition 10

11 Polarización en Emisor Común 11

12 El BT como amplificador Modelo de pequeña señal 12

13 El BT como conmutador 13

14 Lógica DTL (Diode-Transistor Logic) Circuito inversor DTL: Función de transferencia aproximada para el inversor DTL: 14

15 Lógica TTL (Transistor-Transistor Logic) Circuito inversor TTL 15

16 Circuito inversor TTL con salida en colector abierto 16

17 Lógica ECL (Emitter-Coupled Logic) Basada en el amplificador diferencial: 17

18 Capítulo12.b El Transistor MOS (Metal Oxide Semiconductor) 18

19 Estructura Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. Fifth Edition 19

20 Estructura Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device. Fifth Edition 20

21 Símbolo Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant. Fifth Edition 21

22 Polarización Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate. Fifth Edition 22

23 Polarización Figure 4.3 An NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a resistance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS V t and thus i D is proportional to (v GS V t ) v DS. Note that the depletion region is not shown (for simplicity). Fifth Edition 23

24 Polarización Figure 4.5 Operation of the enhancement NMOS transistor as v DS is increased. The induced channel acquires a tapered shape, and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t. Fifth Edition 24

25 Regiones de operación Figure 4.6 The drain current i D versus the drain-to-source voltage v DS for an enhancement-type NMOS transistor operated with v GS > V t. Fifth Edition 25

26 Cálculo de la curva característica I-V Figure 4.8 Derivation of the i D v DS characteristic of the NMOS transistor. Fifth Edition 26

27 Curva característica I-V Figure 4.11 (a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D v DS characteristics for a device with k n (W/L) = 1.0 ma/v 2. Fifth Edition 27

28 Zona de saturación Figure 4.15 Increasing v DS beyond v DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). Fifth Edition 28

29 El inversor CMOS Figure 4.53 The CMOS inverter. Fifth Edition 29

30 El inversor CMOS Figure 4.54 Operation of the CMOS inverter when v I is high: (a) circuit with v I = V DD (logic-1 level, or V OH ); (b) graphical construction to determine the operating point; (c) equivalent circuit. Fifth Edition 30

31 El inversor CMOS Figure 4.55 Operation of the CMOS inverter when v I is low: (a) circuit with v I = 0 V (logic-0 level, or V OL ); (b) graphical construction to determine the operating point; (c) equivalent circuit. Fifth Edition 31

32 El inversor CMOS Figure 4.56 The voltage transfer characteristic of the CMOS inverter. Fifth Edition 32

33 Retardos de propagación Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through Q N ; (d) equivalent circuit during the capacitor discharge. Fifth Edition 33

34 Puerta de transmisión CMOS 34

35 Puertas NAND y NOR CMOS V DD V DD V A V out V B V B V out V A Figura 7. Puertas NAND (a) y NOR (b) con tecnología CMOS. 35