Tapped Inductor Bandpass Filter Design. High Speed Signal Path Applications 7/21/2009 v1.6
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1 Tapped Inductor Bandpass Filter Design High Speed Signal Path Applications 7/1/009 v1.6
2 Tapped Inductor BP Filter 1 st order (6 db/oct) LOW frequency roll-off Shunt LT 4 th order (4 db/oct) HIGH frequency roll-off Series L1, L Shunt C1, CT Called Tapped Inductor because filter uses a series-l T-match impedance transform
3 Tapped Inductor BP Filter Tank provides 1 st order Bandpass profile Impedance transform matches R L to R S at center frequency and increases high frequency roll-off to 4 th order 3
4 Pros / Cons Why is this architecture good? Avoids capacitors in series branches which are very susceptible to shunt parasitics Provides best harmonic tone rejection with lowest possible filter complexity Good noise rejection despite shallow roll-off at low frequencies Relatively easy to design filters up to 300 MHz with 3dB Q~5 (Q = Fo/BW) Design procedure provides flexible matching of R L to R S Drawbacks? Shallow low frequency roll-off may limit noise performance For large R S, R L, and large Q s C1 becomes prohibitively small Wider passband requires shallower stopband (tradeoff) 4
5 Theory Filter can be broken into parts for analysis Bandpass Tank T-match split into Up/Down impedance transforms Each section characterized by Wo and Q Design procedure works from load up to source 5
6 Theory: Filter Loss and Impedance Matching Impedance Matching Power transfer maximized and reflections minimized when R S = R in R in is equivalent resistance looking into T-match RS Rin Filter Loss Related to R S, R L, and Q s used in design Certain configurations can cause voltage gain 6
7 Theory: Bandpass Tank LC Bandpass Tank Impedance should equal R L at center frequency due to parallel cancellation of L T and C T Sets the center frequency and influences the BW CT LT RL Design procedure Choose filter center frequency F 0 Choose suitable Q T Choose R S and R L based on source/driver requirements and passband loss Solve for C T using Q equation Solve for L T using F 0 equation Q f π T = f 0 0 = R L C 1 π LC T T T 7
8 Theory: Up Impedance Transform Up Impedance Transform When properly designed, impedance looking into network will be real and > R L at center frequency Q U must be high enough to isolate C 1 from the tank to preserve the tank center frequency Design procedure Choose desired Q U Solve for L using Q equation Solve for L Solve for C 1 using F 0 equation Rin C1 L L Q U =πf 0 RL Solve for R in 1 L f ' 0 = π 1+ Q QU 1 U = L ' L R = R + ' in L C ( Q ) 1 U RL 8
9 Theory: Down Impedance Transform Down Impedance Transform When properly designed, impedance looking into network will be real and Rin < Rin at center frequency Rin L1 C11 Rin Design procedure Choose desired Q D Solve for C 11 using Q equation and R in from Up Transform design procedure Solve for C 11 Solve for L 1 using F 0 equation Solve for R in Q C D ' 11 f R 0 in = π ' f 0 R inc 11 QD C 11 + Q 1 = π LC = 1 D 1 ' Q = ' Rin D 9
10 Theory: Effect of Q Effect of Q After load/source/frequency are set, Q s are the only design knobs Closely related to Bandwidth of filter Higher Q typically results in less loss and a narrower filter but makes filter more sensitive and harder to tune on the actual board Choosing Q T T Intuitive trend is Q T ~F o /BW but the results are not simple Choosing Q U Set > 3 to prevent ripples in passband Choosing Q D Use equation for impedance matching: 1+ Q = 1+ Q OR Set Q U <Q D <1 for relaxed component values and possible voltage gain increase R R L S U D 10
11 Theory: Tips For R L =4R S Q T =5, Q D =.34, Q U =5 Impedance matched, Gain ~ 0 db For R L =4R S Q T =6, Q D =3, Q U =10 Gain > 0 db For R L =R S Q T =6, Q D =3, Q U =3 Loss ~ 6dB Can t increase Q U much because R in becomes too small (Avoid) Setting low Q D or Q U for wide BW can cause deep ripples in passband due to poor impedance transform. Increased gain can occur when R L >R S. Set Q D >1.5Q U only under this condition. Very large R L can cause prohibitively small C 1 and large L1, L 11
12 Theory: Tips Large Q T allows for narrower and flatter bandpass but the quality is very sensitive to (C 11 +C 1 ). Variations cause significant misshaping. Difficult to tune frequency. Small Q T allows for easier tuning without misshaping by changing C T OR (C 11 +C 1 ). Easier to tune with C T because it is usually much bigger. True bandwidth depends on both the tank and T-network. Filter voltage gain at center frequency: V V out in f= f 0 ~0log R S Rin + R R + 10log R For gain > 0 db: R L /R S >1 and R S <<R in in R + 10log R An impedance matched filter (R in =R S ) has ~0 db gain for R L =4R S ' in S L ' in R in 1+ Q U = 1+ QD R L 1
13 Theory: Tips Voltage output Amplifier Filter impedance Xform modeled as Transformer with coil ratio of 1:n (therefore an impedance ration of 1:n ) V V out in f= f 0 = R L n RL + n R S n 1+ Q = 1+ Q U D If R L =4*R S, n=, then G V =1 Impedance is also matched because R S = R L /n For a R S,R L voltage divider, G V =0.8 (-db) S L The LC network achieves a voltage gain of db Current output Amplifier No series R loss, G V = n Amplifier requires large R S, R L for large amplifier gain Iin RS Vin Z{1:n } Vo RL If R L =R S, n=1, then G V =1 Impedance is matched, Q U = Q D If R L =R S, n=, then G V = Impedance not matched, risk more ripple in passband 13
14 Theory: Tips Reducing QD and QU proportionally while maintaining an impedance match widens bandwidth of filter and impedance match filter profile Input Impedance (5 ohm match) 14
15 Example F 0 =190MHz, 30MHz -1dB Bandpass Filter R S =50, R L =150 15
16 Example Center Frequency and 3dB Half Bandwidth 16
17 Example F 0 =50MHz, 40MHz -1dB Bandpass Filter R S =50, R L =50 17
18 Example Center Frequency and 3dB Half Bandwidth 18
19 Architecture Example Differential implementation Additional large series caps for AC coupling ADC sets input common mode through load resistors Tank caps separated into common mode and differential loads for better charge kickback suppression from ADC 19
20 Practical Issues Input impedance matching good in bandwidth, but has peaking at certain frequencies Insert a small cap (CL) after the series output R s of DVGA to reduce impedance resonance at high frequencies Solid filter profile Impedance resonances (swept CL, green: CL=0.1pF) Peaking due to bond wire inductance 0
21 Practical Issues Charge kickback from ADC resonates with bond wire inductance and LC tank (observed in simple model simulation) Lower tank Q decays faster but bigger initial spike Higher tank Q decays slower but smaller initial spike Differential and CM error depends on whether sampling instant lands on maximum or minimum of kickback ringing Can create seemingly illogical SFDR variations across signal frequency, amplitude, sampling rate, common-mode capacitance, etc. Sampling Instant for ADC16DV160 1
22 References T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 004, pp (Impedance matching)
23 3
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