Ultra-low-power Arm Cortex -M4 32-bit MCU+FPU, 100DMIPS, up to 512KB Flash, 160KB SRAM, analog, audio, ext. SMPS

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1 STM32L452xx Ultralowpower Arm Cortex M4 32bit MCU+FPU, 100DMIPS, up to 512KB Flash, 160KB SRAM, analog, audio, ext. SMPS Features Datasheet production data Ultralowpower with FlexPowerControl 1.71 V to 3.6 V power supply 40 C to 85/125 C temperature range 145 na in V BAT mode: supply for RTC and 32x32bit backup registers 22 na Shutdown mode (5 wakeup pins) 106 na Standby mode (5 wakeup pins) 375 na Standby mode with RTC 2.05 µa Stop 2 mode, 2.40 µa with RTC 84 µa/mhz run mode (LDO Mode) 36 μa/mhz run mode (@3.3 V SMPS Mode) Batch acquisition mode (BAM) 4 µs wakeup from Stop mode Brown out reset (BOR) Interconnect matrix Core: Arm 32bit Cortex M4 CPU with FPU, Adaptive realtime accelerator (ART Accelerator ) allowing 0waitstate execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions Performance benchmark 1.25 DMIPS/MHz (Drystone 2.1) CoreMark ( MHz) Energy benchmark 245 ULPBench score Clock Sources 4 to 48 MHz crystal oscillator 32 khz crystal oscillator for RTC (LSE) Internal 16 MHz factorytrimmed RC (±1%) Internal lowpower 32 khz RC (±5%) Internal multispeed 100 khz to 48 MHz oscillator, autotrimmed by LSE (better than ±0.25 % accuracy) Internal 48 MHz with clock recovery 2 PLLs for system clock, audio, ADC LQFP100 (14x14) UFBGA100 (7 7) WLCSP64 UFQFPN48 (7x7) LQFP64 (10x10) UFBGA64 (5x5) Up to 83 fast I/Os, most 5 Vtolerant RTC with HW calendar, alarms and calibration Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors 12x timers: 1x 16bit advanced motorcontrol, 1x 32bit and 3x 16bit general purpose, 2x 16 bit basic, 2x lowpower 16bit timers (available in Stop mode), 2x watchdogs, SysTick timer Memories Up to 512 KB single bank Flash, proprietary code readout protection 160 KB of SRAM including 32 KB with hardware parity check Quad SPI memory interface Rich analog peripherals (independent supply) 1x 12bit ADC 5 Msps, up to 16bit with hardware oversampling, 200 µa/msps 1x 12bit DAC output channels, lowpower sample and hold 1x operational amplifier with builtin PGA 2x ultralowpower comparators Accurate 2.5 V or V reference voltage buffered output 17x communication interfaces USB 2.0 fullspeed crystal less solution with LPM and BCD 1x SAI (serial audio interface) 4x I2C FM+(1 Mbit/s), SMBus/PMBus 3x USARTs (ISO 7816, LIN, IrDA, modem) 1x UART (LIN, IrDA, modem) 1x LPUART (Stop 2 wakeup) 3x SPIs (and 1x Quad SPI) CAN (2.0B Active) and SDMMC interface IRTIM (Infrared interface) May 2018 DS11912 Rev 4 1/212 This is information on a product in full production.

2 STM32L452xx 14channel DMA controller Development support: serial wire debug True random number generator (SWD), JTAG, Embedded Trace Macrocell CRC calculation unit, 96bit unique ID All packages are ECOPACK2 compliant Table 1. Device summary Reference Part numbers STM32L452xx STM32L452CC, STM32L452RC, STM32L452VC, STM32L452CE, STM32L452RE, STM32L452VE 2/212 DS11912 Rev 4

3 STM32L452xx Contents Contents 1 Introduction Description Functional overview Arm Cortex M4 core with FPU Adaptive realtime memory accelerator (ART Accelerator ) Memory protection unit Embedded Flash memory Embedded SRAM Firewall Boot modes Cyclic redundancy check calculation unit (CRC) Power supply management Power supply schemes Power supply supervisor Voltage regulator Lowpower modes Reset mode VBAT operation Interconnect matrix Clocks and startup Generalpurpose inputs/outputs (GPIOs) Direct memory access controller (DMA) Interrupts and events Nested vectored interrupt controller (NVIC) Extended interrupt/event controller (EXTI) Analog to digital converter (ADC) Temperature sensor Internal voltage reference (VREFINT) VBAT battery voltage monitoring Digital to analog converter (DAC) DS11912 Rev 4 3/212 6

4 Contents STM32L452xx 3.17 Voltage reference buffer (VREFBUF) Comparators (COMP) Operational amplifier (OPAMP) Touch sensing controller (TSC) Digital filter for SigmaDelta Modulators (DFSDM) Random number generator (RNG) Timers and watchdogs Advancedcontrol timer (TIM1) Generalpurpose timers (TIM2, TIM3, TIM15, TIM16) Basic timer (TIM6) Lowpower timer (LPTIM1 and LPTIM2) Infrared interface (IRTIM) Independent watchdog (IWDG) System window watchdog (WWDG) SysTick timer Realtime clock (RTC) and backup registers Interintegrated circuit interface (I 2 C) Universal synchronous/asynchronous receiver transmitter (USART) Lowpower universal asynchronous receiver transmitter (LPUART) Serial peripheral interface (SPI) Serial audio interfaces (SAI) Controller area network (CAN) Secure digital input/output and MultiMediaCards Interface (SDMMC) Universal serial bus (USB) Clock recovery system (CRS) Quad SPI memory interface (QUADSPI) Development support Serial wire JTAG debug port (SWJDP) Embedded Trace Macrocell Pinouts and pin description Memory mapping Electrical characteristics /212 DS11912 Rev 4

5 STM32L452xx Contents 6.1 Parameter conditions Minimum and maximum values Typical values Typical curves Loading capacitor Pin input voltage Power supply scheme Current consumption measurement Absolute maximum ratings Operating conditions General operating conditions Operating conditions at powerup / powerdown Embedded reset and power control block characteristics Embedded voltage reference Supply current characteristics Wakeup time from lowpower modes and voltage scaling transition times External clock source characteristics Internal clock source characteristics PLL characteristics Flash memory characteristics EMC characteristics Electrical sensitivity characteristics I/O current injection characteristics I/O port characteristics NRST pin characteristics Extended interrupt and event controller input (EXTI) characteristics Analog switches booster AnalogtoDigital converter characteristics DigitaltoAnalog converter characteristics Voltage reference buffer characteristics Comparator characteristics Operational amplifiers characteristics Temperature sensor characteristics V BAT monitoring characteristics Timer characteristics Communication interfaces characteristics DS11912 Rev 4 5/212 6

6 Contents STM32L452xx 7 Package information LQFP100 package information UFBGA100 package information LQFP64 package information UFBGA64 package information WLCSP64 package information UFQFPN48 package information Thermal characteristics Reference document Selecting the product temperature range Ordering information Revision history /212 DS11912 Rev 4

7 STM32L452xx List of tables List of tables Table 1. Device summary Table 2. STM32L452xx family device features and peripheral counts Table 3. Access status versus readout protection level and execution modes Table 4. STM32L452xx modes overview Table 5. Functionalities depending on the working mode Table 6. STM32L452xx peripherals interconnect matrix Table 7. DMA implementation Table 8. Temperature sensor calibration values Table 9. Internal voltage reference calibration values Table 10. DFSDM1 implementation Table 11. Timer feature comparison Table 12. I2C implementation Table 13. STM32L452xx USART/UART/LPUART features Table 14. SAI implementation Table 15. Legend/abbreviations used in the pinout table Table 16. STM32L452xx pin definitions Table 17. Alternate function AF0 to AF Table 18. Alternate function AF8 to AF Table 19. STM32L452xx memory map and peripheral register boundary addresses Table 20. Voltage characteristics Table 21. Current characteristics Table 22. Thermal characteristics Table 23. General operating conditions Table 24. Operating conditions at powerup / powerdown Table 25. Embedded reset and power control block characteristics Table 26. Embedded internal voltage reference Table 27. Current consumption in Run and Lowpower run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) Table 28. Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Table 29. Current consumption in Run and Lowpower run modes, code with data processing running from Flash, ART disable Table 30. Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Table 31. Current consumption in Run and Lowpower run modes, code with data processing running from SRAM Table 32. Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Table 33. Typical current consumption in Run and Lowpower run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Table 34. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Table 35. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.05 V) Table 36. Typical current consumption in Run and Lowpower run modes, with different codes DS11912 Rev 4 7/212 9

8 List of tables STM32L452xx running from Flash, ART disable Table 37. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Table 38. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) Table 39. Typical current consumption in Run and Lowpower run modes, with different codes running from SRAM Table 40. Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Table 41. Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) Table 42. Current consumption in Sleep and Lowpower sleep modes, Flash ON Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) Table 44. Current consumption in Lowpower sleep modes, Flash in powerdown Table 45. Current consumption in Stop 2 mode Table 46. Current consumption in Stop 1 mode Table 47. Current consumption in Stop Table 48. Current consumption in Standby mode Table 49. Current consumption in Shutdown mode Table 50. Current consumption in VBAT mode Table 51. Peripheral current consumption Table 52. Lowpower mode wakeup timings Table 53. Regulator modes transition times Table 54. Wakeup time using USART/LPUART Table 55. Highspeed external user clock characteristics Table 56. Lowspeed external user clock characteristics Table 57. HSE oscillator characteristics Table 58. LSE oscillator characteristics (f LSE = khz) Table 59. HSI16 oscillator characteristics Table 60. MSI oscillator characteristics Table 61. HSI48 oscillator characteristics Table 62. LSI oscillator characteristics Table 63. PLL, PLLSAI1 characteristics Table 64. Flash memory characteristics Table 65. Flash memory endurance and data retention Table 66. EMS characteristics Table 67. EMI characteristics Table 68. ESD absolute maximum ratings Table 69. Electrical sensitivities Table 70. I/O current injection susceptibility Table 71. I/O static characteristics Table 72. Output voltage characteristics Table 73. I/O AC characteristics Table 74. NRST pin characteristics Table 75. EXTI Input Characteristics Table 76. Analog switches booster characteristics Table 77. ADC characteristics Table 78. Maximum ADC RAIN Table 79. ADC accuracy limited test conditions Table 80. ADC accuracy limited test conditions Table 81. ADC accuracy limited test conditions /212 DS11912 Rev 4

9 STM32L452xx List of tables Table 82. ADC accuracy limited test conditions Table 83. DAC characteristics Table 84. DAC accuracy Table 85. VREFBUF characteristics Table 86. COMP characteristics Table 87. OPAMP characteristics Table 88. TS characteristics Table 89. V BAT monitoring characteristics Table 90. V BAT charging characteristics Table 91. TIMx characteristics Table 92. IWDG min/max timeout period at 32 khz (LSI) Table 93. WWDG min/max timeout value at 80 MHz (PCLK) Table 94. I2C analog filter characteristics Table 95. SPI characteristics Table 96. Quad SPI characteristics in SDR mode Table 97. QUADSPI characteristics in DDR mode Table 98. SAI characteristics Table 99. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V Table 100. emmc dynamic characteristics, VDD = 1.71 V to 1.9 V Table 101. USB electrical characteristics Table 102. LQPF pin, 14 x 14 mm lowprofile quad flat package mechanical data Table 103. UFBGA ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data Table 104. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Table 105. LQFP64 64pin, 10 x 10 mm lowprofile quad flat package mechanical data Table 106. UFBGA64 64ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data Table 107. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Table 108. WLCSP64 64ball, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale mechanical data Table 109. WLCSP64 recommended PCB design rules (0.4 mm pitch) Table 110. UFQFPN48 48lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data Table 111. Package thermal characteristics Table 112. STM32L452xx ordering information scheme Table 113. Document revision history DS11912 Rev 4 9/212 9

10 List of figures STM32L452xx List of figures Figure 1. STM32L452xx block diagram Figure 2. Power supply overview Figure 3. Powerup/down sequence Figure 4. Clock tree Figure 5. Voltage reference buffer Figure 6. STM32L452Vx LQFP100 pinout (1) Figure 7. STM32L452Vx UFBGA100 ballout (1) Figure 8. STM32L452Rx LQFP64 pinout (1) Figure 9. STM32L452Rx, external SMPS device, LQFP64 pinout (1) Figure 10. STM32L452Rx UFBGA64 ballout (1) Figure 11. STM32L452Rx WLCSP64 pinout (1) Figure 12. STM32L452Cx UFQFPN48 pinout (1) Figure 13. STM32L452xx memory map Figure 14. Pin loading conditions Figure 15. Pin input voltage Figure 16. Power supply scheme Figure 17. Current consumption measurement scheme with and without external SMPS power supply Figure 18. VREFINT versus temperature Figure 19. Highspeed external clock source AC timing diagram Figure 20. Lowspeed external clock source AC timing diagram Figure 21. Typical application with an 8 MHz crystal Figure 22. Typical application with a khz crystal Figure 23. HSI16 frequency versus temperature Figure 24. Typical current consumption versus MSI frequency Figure 25. HSI48 frequency versus temperature Figure 26. I/O input characteristics Figure 27. I/O AC characteristics definition (1) Figure 28. Recommended NRST pin protection Figure 29. ADC accuracy characteristics Figure 30. Typical connection diagram using the ADC Figure bit buffered / nonbuffered DAC Figure 32. SPI timing diagram slave mode and CPHA = Figure 33. SPI timing diagram slave mode and CPHA = Figure 34. SPI timing diagram master mode Figure 35. Quad SPI timing diagram SDR mode Figure 36. Quad SPI timing diagram DDR mode Figure 37. SAI master timing waveforms Figure 38. SAI slave timing waveforms Figure 39. SDIO highspeed mode Figure 40. SD default mode Figure 41. LQFP pin, 14 x 14 mm lowprofile quad flat package outline Figure 42. LQFP pin, 14 x 14 mm lowprofile quad flat recommended footprint Figure 43. LQFP100 marking (package top view) Figure 44. Figure 45. UFBGA ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline UFBGA ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid 10/212 DS11912 Rev 4

11 STM32L452xx List of figures array package recommended footprint Figure 46. UFBGA100 marking (package top view) Figure 47. LQFP64 64pin, 10 x 10 mm lowprofile quad flat package outline Figure 48. LQFP64 64pin, 10 x 10 mm lowprofile quad flat package recommended footprint Figure 49. LQFP64 marking (package top view) Figure 50. UFBGA64 64ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline Figure 51. UFBGA64 64ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint Figure 52. UFBGA64 marking (package top view) Figure 53. WLCSP64 64ball, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale package outline Figure 54. WLCSP64 64pin, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale recommended footprint Figure 55. WLCSP64 marking (package top view) Figure 56. UFQFPN48 48lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat Figure 57. package outline UFQFPN48 48lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint Figure 58. UFQFPN48 marking (package top view) Figure 59. LQFP64 P D max vs. T A DS11912 Rev 4 11/212 11

12 Introduction STM32L452xx 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L452xx microcontrollers. This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the STMicroelectronics website For information on the Arm (a) Cortex M4 core, please refer to the Cortex M4 Technical Reference Manual, available from the website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/212 DS11912 Rev 4

13 STM32L452xx Description 2 Description The STM32L452xx devices are the ultralowpower microcontrollers based on the highperformance Arm Cortex M4 32bit RISC core operating at a frequency of up to 80 MHz. The CortexM4 core features a Floating point unit (FPU) single precision which supports all Arm singleprecision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L452xx devices embed highspeed memories (Flash memory up to 512 Kbyte, 160 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32bit multiahb bus matrix. The STM32L452xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer a fast 12bit ADC (5 Msps), two comparators, one operational amplifier, one DAC channel, an internal voltage reference buffer, a lowpower RTC, one generalpurpose 32bit timer, one 16bit PWM timer dedicated to motor control, four generalpurpose 16bit timers, and two 16bit lowpower timers. In addition, up to 21 capacitive sensing channels are available. They also feature standard and advanced communication interfaces. Four I2Cs Three SPIs Three USARTs, one UART and one LowPower UART. One SAI (Serial Audio Interfaces) One SDMMC One CAN One USB fullspeed device crystal less The STM32L452xx operates in the 40 to +85 C (+105 C junction) and 40 to +125 C (+130 C junction) temperature ranges from a 1.71 to 3.6 V V DD power supply when using internal LDO regulator and a 1.05 to 1.32V V DD12 power supply when using external SMPS supply. A comprehensive set of powersaving modes allows the design of lowpower applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMP and comparators. A VBAT input allows to backup the RTC and backup registers. Dedicated V DD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. The STM32L452xx family offers six packages from 48 to 100pin packages. DS11912 Rev 4 13/212 56

14 Description STM32L452xx Table 2. STM32L452xx family device features and peripheral counts Peripheral STM32L452Vx STM32L452Rx STM32L452Cx Flash memory 256KB 512KB 256KB 512KB 256KB 512KB SRAM Quad SPI Timers Comm. interfaces RTC Advanced control General purpose Basic Low power 160KB Yes 1 (16bit) 2 (16bit) 1 (32bit) 2 (16bit) 2 (16bit) SysTick timer 1 Watchdog timers (independent, window) SPI 3 I 2 C 4 USART UART LPUART SAI 1 CAN 1 USB FS SDMMC Yes (1) No Tamper pins Random generator GPIOs (2) Wakeup pins Capacitive sensing Number of channels 12bit ADC Number of channels Yes Yes Yes (1) bit DAC channels 1 Internal voltage reference buffer Yes Analog comparator 2 Operational amplifiers 1 Max. CPU frequency (1) MHz No 14/212 DS11912 Rev 4

15 STM32L452xx Description Table 2. STM32L452xx family device features and peripheral counts (continued) Peripheral STM32L452Vx STM32L452Rx STM32L452Cx Operating voltage 1.71 to 3.6 V Operating temperature Ambient operating temperature: 40 to 85 C / 40 to 125 C Junction temperature: 40 to 105 C / 40 to 130 C Packages LQFP100 UFBGA100 WLCSP64 LQFP64 UFBGA64 UFQFPN48 1. WKUP5, ADC1_IN14 and SDMMC interface are not supported by 64pin packages with SMPS option. 2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2. DS11912 Rev 4 15/212 56

16 Description STM32L452xx Figure 1. STM32L452xx block diagram NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO TRACECLK TRACED[3:0] JTAG & SW ETM ARM CortexM4 80 MHz FPU MPU NVIC DBUS IBUS SBUS ART ACCEL/ CACHE Quad SPI memory interface Flash up to 512 KB RNG D0[3:0], D1[3:0], CLK0, CLK1 CS DMA2 AHB busmatrix SRAM2 32 KB SRAM1 128 KB AHB2 80 MHz VDD VDD12 Power management Voltage regulator 3.3 to 1.2 V VDD = 1.71 to 3.6 V VDD12 = 1.05 to 1.32 V (1) VSS DMA1 7 Groups of 4 channels max as AF PA[15:0] Touch sensing controller GPIO PORT VDD MSI RC HSI RC LSI PLL 1&2 reset VDD Supply supervision BOR PVD, PVM VDDUSB VDDA, VSSA VDD, VSS, NRST PB[15:0] PC[15:0] GPIO PORT B GPIO PORT C AHB1 80 MHz XTAL OSC 4 16MHz OSC_IN OSC_OUT PD[15:0] GPIO PORT D IWDG VBAT = 1.55 to 3.6 V PE[15:0] PH[1:0], PH[3] GPIO PORT E GPIO PORT H Reset & clock MAN control AGT FCLK HCLKx PCLKx Standby XTAL 32 khz RTC AWU Backup register OSC32_IN OSC32_OUT RTC_TS RTC_TAMPx VDD 16 external analog inputs USAR Temperature T 2MBps VDDA ADC1 ITF CRC FIFO TIM2 VDDUSB USB FS PHY 4 channels, ETR as AF DP DM NOE CRS CRS_SYNC VDDA VREF Buffer AHB/APB2 AHB/APB1 USART2 smcard IrDA RX, TX, CK, CTS, RTS as AF 83 AF EXT IT. WKUP USART3 smcard IrDA RX, TX, CK, CTS, RTS as AF D[7:0] CMD, CK as AF SDIO / MMC FIFO UART4 IrDA RX, TX, CTS, RTS as AF 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1 / PWM 16b SPI2 MOSI, MISO, SCK, NSS as AF SPI3 MOSI, MISO, SCK, NSS as AF 2 channels, 1 compl. channel, BKIN as AF 1 channel, 1 compl. channel, BKIN as AF RX, TX, CK,CTS, RTS as AF MOSI, MISO, SCK, NSS as AF MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SDCKIN[3:0], SDDATIN[3:0], SDCKOUT, SDTRIG as AF INP, INM, OUT INP, INM, OUT smcard VDDA TIM15 TIM16 USART1 SPI1 SAI1 DFSDM COMP1 COMP2 16b 16b APB2 80MHz APB2 60 M Hz WWDG VDDA DAC1 16b ITF APB1 80 MHz APB1 (max) 30MHz I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS I2C4/SMBUS OpAmp1 LPUART1 SWPMI1 LPTIM1 FIFO SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF TX, RX as AF VOUT, VINM, VINP RX, TX, CTS, RTS as AF IO RX, TX, SUSPEND as AF IN1, IN2, OUT, ETR as AF FIREWALL LPTIM2 IN1, OUT, ETR as AF 1. Only available when using external SMPS supply mode. OUT1 MSv40938V2 Note: AF: alternate function on I/O pins. 16/212 DS11912 Rev 4

17 STM32L452xx Functional overview 3 Functional overview 3.1 Arm Cortex M4 core with FPU The Arm Cortex M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a lowcost platform that meets the needs of MCU implementation, with a reduced pin count and lowpower consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm Cortex M4 with FPU 32bit RISC processor features exceptional codeefficiency, delivering the highperformance expected from an Arm core in the memory size usually associated with 8 and 16bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm core, the STM32L452xx family is compatible with all Arm tools and software. Figure 1 shows the general block diagram of the STM32L452xx family devices. 3.2 Adaptive realtime memory accelerator (ART Accelerator ) The ART Accelerator is a memory accelerator which is optimized for STM32 industrystandard Arm Cortex M4 processors. It balances the inherent performance advantage of the Arm Cortex M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS11912 Rev 4 17/212 56

18 Functional overview STM32L452xx 3.4 Embedded Flash memory STM32L452xx devices feature up to 512 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 256 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: Readout protection (RDP) to protect the whole memory. Three levels are available: Level 0: no readout protection Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected Level 2: chip readout protection: debug features (CortexM4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Protection level User execution Debug, boot from RAM or boot from system memory (loader) Read Write Erase Read Write Erase Main memory System memory Option bytes Backup registers SRAM2 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A 1 Yes Yes N/A (1) No No N/A (1) 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes (1) No No No (1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 2Kbyte granularity. Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is executeonly: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP area granularity is 64bit wide. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. 18/212 DS11912 Rev 4

19 STM32L452xx Functional overview The whole nonvolatile memory embeds the error correction code (ECC) feature supporting: single error detection and correction double error detection. The address of the ECC fail can be read in the ECC register 3.5 Embedded SRAM STM32L452xx devices feature 160 Kbyte of embedded SRAM. This SRAM is split into two blocks: 128 Kbyte mapped at address 0x (SRAM1) 32 Kbyte located at address 0x with hardware parity check (SRAM2). This memory is also mapped at address 0x , offering a contiguous address space with the SRAM1 (32 Kbyte aliased by bit band) This block is accessed through the ICode/DCode buses for maximum performance. These 32 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be writeprotected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: Three segments can be protected and defined thanks to the Firewall registers: Code segment (located in Flash or SRAM1 if defined as executable protected area) Nonvolatile data segment (located in Flash) Volatile data segment (located in SRAM1) The start address and the length of each segments are configurable: Code segment: up to 1024 Kbyte with granularity of 256 bytes Nonvolatile data segment: up to 1024 Kbyte with granularity of 256 bytes Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) Volatile data segment can be shared or not with the nonprotected code Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. DS11912 Rev 4 19/212 56

20 Functional overview STM32L452xx 3.7 Boot modes At startup, BOOT0 pin or nswboot0 option bit, and BOOT1 option bit are used to select one of three boot options: Boot from user Flash Boot from system memory Boot from embedded SRAM BOOT0 value may come from the PH3BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB FS in Device mode through DFU (device firmware upgrade). 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRCbased techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management Power supply schemes Note: V DD = 1.71 to 3.6 V: external power supply for I/Os (V DDIO1 ), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. V DD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load. V DDA = 1.62 V (ADC/COMPs) / 1.8 (DAC/OPAMP) / 2.4 V (VREFBUF) to 3.6 V: external analog power supply for ADC, DAC, OPAMP, Comparators and Voltage reference buffer. The V DDA voltage level is independent from the V DD voltage. V DDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The V DDUSB voltage level is independent from the V DD voltage. V BAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 khz oscillator and backup registers (through power switch) when V DD is not present. When the functions supplied by V DDA are not used, this supply should preferably be shorted to V DD. 20/212 DS11912 Rev 4

21 STM32L452xx Functional overview Note: Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant. V DDIOx is the I/Os general purpose digital functions supply. V DDIOx represents V DDIO1, with V DDIO1 = V DD. Figure 2. Power supply overview VDDA domain V DDA V SSA A/D converters Comparators D/A converters Operational amplifiers Voltage reference buffer V DDUSB V SS USB transceivers VDD domain V DD VDDIO1 I/O ring Reset block Temp. sensor PLL, HSI, MSI, HSI48 V SS Standby circuitry (Wakeup logic, IWDG) Voltage regulator VCORE VCORE domain Core Memories Digital peripherals V DD12 Low voltage detector Backup domain V BAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv45727V1 During powerup and powerdown phases, the following power sequence requirements must be respected: When V DD is below 1 V, other power supplies (V DDA ) must remain below V DD mv. When V DD is above 1 V, all power supplies are independent. During the powerdown phase, V DD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mj; this allows external decoupling capacitors to be discharged with different time constants during the power down transient phase. DS11912 Rev 4 21/212 56

22 Functional overview STM32L452xx Figure 3. Powerup/down sequence V 3.6 V DDX (1) V DD V BOR Poweron Operating mode Powerdown time Invalid supply area V DDX < V DD mv V DDX independent from V DD MSv47490V1 1. V DDX refers to V DDA Power supply supervisor The device has an integrated ultralowpower brownout reset (BOR) active in all modes except Shutdown and ensuring proper operation after poweron and during power down. The device remains in reset mode when the monitored supply voltage V DD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.the device features an embedded programmable voltage detector (PVD) that monitors the V DD power supply and compares it to the VPVD threshold. An interrupt can be generated when V DD drops below the VPVD threshold and/or when V DD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage V DDA with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 22/212 DS11912 Rev 4

23 STM32L452xx Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the lowpower regulator (LPR). The MR is used in the Run and Sleep modes and in the Stop 0 mode. The LPR is used in LowPower Run, LowPower Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention. Both regulators are in powerdown in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralowpower STM32L452xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (V CORE ) can be adjusted according to the system s maximum operating frequency. There are two power consumption ranges: Range 1 with the CPU running at up to 80 MHz. Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The V CORE can be supplied by the lowpower regulator, the main regulator being switched off. The system is then in Lowpower run mode. Lowpower run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. When the MR is in use, the STM32L452xx with the external SMPS option allows to force an external V CORE supply on the VDD12 supply pins. When V DD12 is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter Lowpower modes The ultralowpower STM32L452xx supports seven lowpower modes to achieve the best compromise between lowpower consumption, short startup time, available peripherals and available wakeup sources. DS11912 Rev 4 23/212 56

24 24/212 DS11912 Rev 4 Table 4. STM32L452xx modes overview Mode Regulator (1) CPU Flash SRAM Clocks DMA & Peripherals (2) Wakeup source Consumption (3) Wakeup time Run MR range 1 94 µa/mhz All SMPS range 2 High Yes ON (6) 34 µa/mhz (4) ON Any N/A MR range2 85 µa/mhz All except USB_FS, RNG SMPS range 2 Low 37 µa/mhz (5) Any LPRun LPR Yes ON (6) ON except All except USB_FS, RNG N/A 95 µa/mhz PLL Sleep MR range 1 27 µa/mhz All SMPS range 2 High No ON (6) ON (7) Any interrupt or 10 µa/mhz (4) Any MR range2 event 27 µa/mhz All except USB_FS, RNG SMPS range 2 Low 11 µa/mhz (5) LPSleep LPR No ON (6) ON (7) except Any PLL Stop 0 MR Range 1 (8) No OFF ON LSE LSI All except USB_FS, RNG BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3) (9) UART4 (9) LPUART1 (9) I2Cx (x=1...4) (10) LPTIMx (x=1,2) *** All other peripherals are frozen. Any interrupt or event Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3) (9) UART4 (9) LPUART1 (9) I2Cx (x=1...4) (10) LPTIMx (x=1,2) USB_FS (11) N/A to Range 1: 4 µs to Range 2: 64 µs 6 cycles 38 µa/mhz 6 cycles 125 µa MR Range 2 (8) 125 µa 2.47 µs in SRAM 4.1 µs in Flash Functional overview STM32L452xx