PT7M7803/ / μp Supervisor Circuits

Transcription

1 Features Precision supply-voltage monitor -.6V (PT7M78xxL) -.8V (PT7M78xxM) -.08V (PT7M78xxT) -.9V (PT7M78xxS) -.6V (PT7M78xxR) -.V (PT7M78xxZ) -.0V (PT7M78xxY) -.00V (PT7M78xxJ) -.5V (PT7M78xxK) -.80V (PT7M78xxG) 00ms reset pulse width Debounced CMOS-compatible manual-reset input (78, 78, 78, 785) Reset Output Signal for Watchdog and Power Abnormal, Manual Reset Reset Push-Pull output (PT7M7809,78,78, 78,785) Reset Open-Drain output (PT7M780) Voltage monitor for power-fail or low battery warning Guaranteed / valid at =.0V Description The PT7M78xx family microprocessor ( P) supervisory circuits are targeted to improve reliability and accuracy of power-supply circuitry in P systems. These devices reduce the complexity and number of components required to monitor power-supply and battery functions. The main functions are:. Asserting reset output during power-up, powerdown and brownout conditions for P system.. Detecting power failure or low-battery conditions with a.5v threshold detector.. Watchdog functions. Manual reset. Applications Power-supply circuitry in P systems Networking Security System Server/Storage Embedded System Function Comparison Table output (push-pull) Manual Reset Input Power Fail Detector (.5V) Watchdog Input Part No. output Push-Pull Open-Drain PT7M PT7M PT7M PT7M PT7M PT7M PT7M PT7M

2 Pin Configuration SOT-/SC70- PT7M780 PT7M7809 PT7M780 SOT- PT7M78 PT7M78 VCC VCC SOT-5 PT7M78 PT7M NC NC PT7M78 PT7M78 PT7M VCC 5 WDI WDI

3 Pin Description Pin Type Description VCC I Power Manual-Reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration of the Reset Timeout Period after transitions from low to high. Leave unconnected or connected to VCC if not used. Supply Voltage. Reset is asserted when drops below the Reset Threshold Voltage (V RST ). Reset remains asserted until rises above V RST and keep asserted for the duration of the Reset Timeout Period (t RS ) once rises above V RST. - Ground Reference for all signals. PFI I Power-Fail Voltage Monitor Input. When PFI <V PFT, PFO goes low. Connect PFI to or Vcc when not used. PFO O Power-Fail Output: it gets low and sinks current when PFI is less than.5v; otherwise PFO stays high. WDI I O Watchdog Input (CMOS). If WDI remains high or low for the duration of the watchdog timeout period (t WD ), the internal watchdog timer trigger a reset output. Floating WDI or connecting WDI to a highimpedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted or WDI occurs a rising or falling edge. Active-Low Reset Output (Push-Pull or Open-Drain). It goes low when Vcc is below the reset threshold. It remains low for about 00ms after one of the following occurs: Vcc rises above the reset threshold (VRST), the watchdog triggers a reset, or goes from low to high. O The inverse of, active high. Whenever is high, is low. NC - No connection. Block Diagram PT7M78//5 Block Diagram WDI Watchdog Transition Detector Vcc Watchdog Timer Timebase for Reset & Watchdog Vcc Reset Generator () V RST PFI PFO.5V

4 PT7M78/ Block Diagram Maximum Ratings Storage Temperature o C to +50 o C Ambient Temperature with Power Applied o C to +85 o C Supply Voltage to Ground Potential (Vcc to )...-0.V to +7.0V DC Input Voltage (All inputs except Vcc and )...-0.V to +0.V DC Output Current (All outputs)...0ma Power Dissipation... 0mW (Depend on package) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Conditions Sym Description Test Conditions Min Typ Max Unit Supply Voltage for 78xxL/M/J V Supply Voltage for 78xxT/S V Supply Voltage for 78xxR/Z/Y/K/G V V IH Input High Voltage V V IL Input Low Voltage V T A Operating Temperature

5 DC Electrical Characteristics ( = V RN + 5% to 5.5V, T A = -0~85ºC, unless otherwise noted.)(note ) Symbol Description Test Conditions Min Typ Max Unit Operating Voltage Range V I CC Supply Current Vcc = 5V, No 780/09/0// µa load 78//5-6 V IH Input High Voltage Pin:, WDI V V IL Input Low Voltage Pin:, WDI V V RST V RTH V OH V OL I LKG I WDI I source Threshold Voltage(Fallingedge)(Note ) Reset Threshold Hysteresis (Note ) Output High Voltage(Except 78//5) Output High Voltage(78//5) Output Low Voltage Open-Drain Output Leakage Current Average WDI Input Current (Note ) Output Short- Circuit Current (only for PT7M78//5) T A = 5ºC V RN -.5% V RN V RN +.5% T A = -0 ~ 85ºC 78xx V RN -.5% V RN V RN +.5% Vcc varies between V RN ± 5% 78//5L/M //5 T/S/R/K/Z/Y - - Others Vcc.5V Isource=800µA Vcc Vcc.7V Isource=500µA 0.8 Vcc - - Vcc.8V Isource=50µA 0.8 Vcc - - Vcc.0V Isource=µA 0.8 Vcc //5L/M, Vcc=V RST Isource=0µA Vcc V 78//5T/S/R/K, Vcc=V RST Isource=0µA 0.8 Vcc - - V Vcc.5V Isink=.mA Vcc.7V Isink=.mA Vcc.0V Isink=00µA > V TH(MAX) for µa WDI connected to : 5.5V WDI connected to PT7M78xL/M, =0V, Vcc=5.5V PT7M78xT/S/R/K/Z/Y, =0V, Vcc=.6V PT7M78/ pull-up resistor r k (internal) PT7M78/78/ Note:. Parameters of room temperature guaranteed by production test and parameters of full-temperature guaranteed by design.. Valid for both and. V RST (V RTH -) is the Reset threshold voltage when from high to low level, and V RTH + is the Reset threshold voltage when from low to high level. V RN is nominal reset threshold voltage.. WDI is internally serviced within the watchdog period if WDI is left unconnected. V mv V V µa µa 5

6 AC Electrical Characteristics Symbol Description Test Conditions Min Typ Max Unit t RS Reset Pulse Width from low to High, T A = ms t WD Watchdog Timeout Period WDI, tied to Vcc, Vcc>V RN +5%, T A = s t Pulse Width ns t MD to Delay Vcc=5V ns t WP WDI Pulse Width ns Watchdog Timing Diagram VCC V RST V RST t RS t WD t RS t RS t WP t MD WDI t 6

7 Functional Description Reset Output A microprocessor ( P) reset input starts the P in a known state. Whenever the P is in an unknown state, it should be held in reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout conditions. On power-up, once Vcc reaches about.0v, is a guaranteed logic low of 0.V or less. As Vcc rises, stays low. When Vcc rises above the reset threshold, an internal timer releases after about 00ms. pulses low whenever Vcc drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 00ms. On power-down, once Vcc falls below the reset threshold, stays low and is guaranteed to be 0.V or less until Vcc drops below.0v. Watchdog Timing Diagram shows the timing relationship. The active-high output is simply the inverse of the output, and is guaranteed to be valid with Vcc down to.0v. Watchdog Timer The PT7M78xx watchdog circuit monitors the P activity. If the P does not toggle the watch-dog input (WDI) within.6s, reset asserts. As long as reset is asserted or the WDI input is toggled, the watchdog timer will stay clear and will not count. As soon as reset is released, the timer will start counting. WDI input pulses as short as 50ns can be detected. Disable the watchdog function by leaving WDI unconnected or by three-stating driver connected to WDI. Manual Reset The manual-reset input () allows reset to be triggered by a push button switch. has an internal pullup resistor, so it can be left open when not used. Power-Fail Comparator The power-fail comparator can be used for various purposes because its output and noninverting input are not internally connected. The inverting input is internally connected to a.5v reference. Typical Application Circuit IN DC Linear Regulator P Vcc Vcc P Supervisory PFI Circuit WDI I/O Line PFO Interrupt 7

8 Mechanical Information TE (SOT-) Note: ) Ref: JEDEC TO-6H; ) Coplanarity deviation should not exceed 0.mm PKG. DIMENSIONS(MM) Symbol Min Max A A A b c D E.0.0 E.5.55 e 0.95TYP e L θ 0 8 8

9 CE (SC70-) 9

10 TAE (SOT-5) Note: ) Controlling dimensions in millimeters. ) Ref: JEDEC MO-78C/AA PKG. DIMENSIONS(MM) SYMBOL MIN MAX A.05.5 A A.05.5 b c D.8.0 E E e 0.95BSC e L θ 0 8 0

11 TBE (Lead free and Green SOT) X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Note: ) Controlling dimensions in millimeters. ) Ref: JEDEC TO-5D

12 Ordering Information Part Number Package Code Package PT7M780XTEX T Lead free and Green SOT-, Tape & Reel PT7M7809XTEX T Lead free and Green SOT-, Tape & Reel PT7M780XTEX T Lead free and Green SOT-, Tape & Reel PT7M780XCEX C Lead free and Green SC70-, Tape & Reel PT7M7809XCEX C Lead free and Green SC70-, Tape & Reel PT7M780XCEX C Lead free and Green SC70-, Tape & Reel PT7M78XTAEX TA Lead free and Green SOT-5, Tape & Reel PT7M78XTAEX TA Lead free and Green SOT-5, Tape & Reel PT7M78XTAEX TA Lead free and Green SOT-5, Tape & Reel PT7M78XTAEX TA Lead free and Green SOT-5, Tape & Reel PT7M785XTAEX TA Lead free and Green SOT-5, Tape & Reel PT7M78XTBEX TB Lead free and Green SOT, Tape & Reel PT7M78XTBEX TB Lead free and Green SOT, Tape & Reel PT7M7809XUWF UWF Wafer form Note: X refers to voltage range, see below table. E = Pb-free and Green packaging X = Suffix for Tape/Reel packaging Contact Pericom for availability. Suffix: X Monitored Voltage X L M T S R Z Y J K G Reset Threshold (V)

13 Marking Information Code Description Part Number Year Work Week Only for PT7M7809M Part Number Code Code Part No Code Part No Code Part No Code Part No AA PT7M7809L AO PT7M78L BC PT7M780L BQ PT7M78L AB PT7M7809M AP PT7M78M BD PT7M780M BR PT7M78M AC PT7M7809T AQ PT7M78T BE PT7M780T BS PT7M78T AD PT7M7809S AR PT7M78S BF PT7M780S BT PT7M78S AE PT7M7809R AS PT7M78R BG PT7M780R BU PT7M78R AF PT7M7809Z AT PT7M78Z BH PT7M780Z BV PT7M78Z AG PT7M7809Y AU PT7M78Y BI PT7M780Y BW PT7M78Y jm PT7M7809J sf PT7M78J sc PT7M780J si PT7M78J pe PT7M7809G mq PT7M78K AH PT7M780L AV PT7M78L BJ PT7M78L BX PT7M785L AI PT7M780M AW PT7M78M BK PT7M78M BY PT7M785M AJ PT7M780T AX PT7M78T BL PT7M78T BZ PT7M785T AK PT7M780S AY PT7M78S BM PT7M78S CA PT7M785S AL PT7M780R AZ PT7M78R BN PT7M78R CB PT7M785R AM PT7M780Z BA PT7M78Z BO PT7M78Z CC PT7M785Z AN PT7M780Y BB PT7M78Y BP PT7M78Y CD PT7M785Y se PT7M780J sg PT7M78J sh PT7M78J sj PT7M785J mp PT7M78K Pericom Semiconductor Corporation Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.