Timing Constraint-driven Technology Mapping for FPGAs Considering False Paths and Multi-Clock Domains

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1 Timing Constrint-driven Technology Mpping for FPGAs Considering Flse Pths nd Multi-Clock Domins Lei Cheng, Deming Chen, Mrtin D.F. Wong Univ. of Illinois t UC, Chmpign, IL USA {lcheng1,dchen,mdfwong}@uiuc.edu Abstrct Modern FPGA chips contin multiple dedicted clocking networks, becuse nerly ll rel designs contin multiple clock domins. In this pper, we present n FPGA technology mpping lgorithm trgeting designs with multi-clock domins such s those contining multi-clocks, multi-cycle pths, nd flse pths. We use timing constrints to hndle these unique clocking issues. We work on timing constrint grphs nd process multiple rrivl/required times for ech node in the gte-level netlist. We lso recognize nd process constrint conflicts efficiently. Our lgorithm produces mpped circuit with the optiml mpping depth under timing constrints. To the best of our knowledge, this is the first FPGA mpping lgorithm working with multi-clock domins. Experiments show tht our lgorithm is ble to improve circuit performnce by 16.8% on verge fter plcement nd routing for set of benchmrks with multi-cycle pths, compring to previously published depth-optiml lgorithm tht does not consider multi-cycle pths. 1. Introduction Modern designs t to hve mny different timing constrints, rising from multiple relted (nd not relted) clock domins. They lso hve exceptions (cn lso be considered s constrints) such s multi-cycle, mximum pth dely, nd flse-pth exceptions [1]. A flse pth in circuit is pth which cnnot be ctivted by ny input vector. Fig. 1 shows flse pth exmple. In prctice, designers cn specify don t cre conditions, such tht some ctivted pths will become flse pths under don t cre conditions. A multi-cycle pth in circuit is pth tht does not hve to propgte signls in single clock cycle. A flse pth cn be treted s pth under clock domin with multicycle timing constrint of. A multi-cycle pth nd single-cycle regulr pth cn be seen to function with relted clocks under two clock domins [1]. Logic synthesis with multiple clock domins brings up new chllenges for optimiztion while trying to fulfill these complicted timing constrints. Reserchers hve proposed lgorithms to identify flse pths using vrious pth sensitiztion methods [2, 3, 4, 5, 6, 7]. There re lso some lgorithms to identify multi-cycle pths in circuit. In [8], the uthors presented method to detect multi-cycle pths bsed on the nlysis of the stte trnsition grph of the controller of microprocessor. In [9], the uthors provided multi-cycle pth detection lgorithm bsedonsymbolicsttetrversloffinite stte mchines. The multi-cycle pths cn lso be detected using SATbsed method [10]. Timing constrints due to multi-clock domins re hevily used in sttic timing nlysis (STA). Most litertures to dte focus on nlysis with flse pth constrints [11, 12, 13]. In [14], the uthors proposed unified frmework for STA considering both flse pth nd multi-cycle pth timing constrints. However, ll of these STA lgorithms my suffer n exponentil runtime for node involved in multiple timing constrints. In [1], the uthorsproposednefficient STA method using the edge msk dt structure, in which ech edge hs two ssocited This work is prtilly sponsored by Alter Corportion through reserch grnt. We used mchines donted by Intel. Mike Hutton, Json Govig Alter Corp., Sn Jose, CA USA {mhutton,jgovig}@lter.com b c d 1 e Figure 1: Exmple of flse pth. In this exmple, the pth defg is flse pth. For this pth to be ctive, b is required to be 1 t the gte 1,ndb is lso required to be 0tthegteo 1, which is not possible. vectors representing timing informtion from the source nd destintion direction respectively. In this pper, we use method similr to [1] for timing informtion propgtion. In this work, we design technology mpping lgorithm with multi-clock domin considertion for FPGAs becuse modern FPGA chips contin multiple dedicted clocking networks. For exmple Alter Strtix II devices [15], contin 16 dedicted full-chip globl clocks nd 32 regionl clock lines. These clocks cn be controlled either by pins or internl signls, or generted by on-chip PLLs from other clock signls. FPGA technology mpping converts given Boolen network into functionlly equivlent network comprised only of LUTs. It is criticl synthesis step in the FPGA design flow. Through communiction with FPGA vors, we re wre tht synthesis with multi-clock domins nd the corresponding timing constrints re very importnt to FPGA customers. Timing constrints cn lso be specified in commercil FPGA tools, such s Alter Qurtus II [16] nd Xilinx ISE [17]. However, we re not wre of ny work on FPGA technology mpping with multi-clock domins. Previous depth-optiml FPGA technology mpping lgorithms re ll working with single clock domin [18, 19, 20, 21]. In this work, we propose n lgorithm trgeting FPGA designs under multi-clock domins. We significntly ext the cut-enumertion-bsed mpping frmework to crry out the multi-clock-domin mpping process. We work on timing constrint grphs nd process multiple rrivl/required times for ech node in the gte-level netlist. We lso recognize nd process constrint conflicts efficiently. Our lgorithm produces mpped circuit with the optiml mpping depth under multi-clock timing constrints. In ddition, due to the lck of rel benchmrks with multi-clock domins, we develop circuit model to incorporte multi-cycle pths nd designed twenty such benchmrk circuits using the twenty lrgest MCNC benchmrks s the bse. These benchmrks just serve s the evlution instrument, nd our lgorithm is generl enough to hndle other multi-clock-domin criteri, such s mximum pth dely nd flse pths. Experiments show tht our lgorithm is ble to improve circuit performnce by 16.8% on verge, compring to previously published depth-optiml lgorithm tht does not consider multi-cycle pths. The rest of this pper is orgnized s follows. We provide the problem formultion nd some relted definitions in Section 2. In Section 3, we present the detils of our FPGA technology mpping lgorithm. The results re shown in Section 4, nd we conclude this pper in Section 5. f o 1 g /07/$ IEEE 370

2 1 G G MUX1 1 Dt ff_in D Q Multi-Cycle Opertion MC out 0 MUX2 1 ff_out D in D Q Q out Figure 2: Grph G represents circuit. Grph G α is timing constrint grph for timing constrint α. B(G α)= {3, 4}, E(G α)={7}. The pth 3 5isprefix pthof G α. The pth 5 7issuffix pthofg α. The pth is complete pth of G α. The complete pth ofG is pth with timing constrint α, becuse it covers complete pth 3 5 7ofG α,while thecompletepth ofG is regulr pth. 2. Problem Formultion nd Definitions A Boolen network cn be represented by DAG where ech node represents logic gte, nd directed edge (i, j) exists if the output of gte i is n input of gte j. APInode hs no incoming edges nd PO node hs no outgoing edges. We tret the flip-flop outputs s specil PIs nd the flip-flop inputs s specil POs, nd mke no distinction in terms of nottion. We use input(v) to denote the set of nodes which re fnins of gte v. Given Boolen network N, weuseo v to denote cone rooted on node v in N. O v is subnetwork of N consisting of v nd some of its predecessors, such tht for ny node w O v, there is pth from w to v tht lies entirely in O v. The cone O v is K-fesible if the size of input(o v)isnotlrgerthnk, whereinput(o v)denotes the set of distinct nodes outside O v which supply inputs to the gtes in O v.acut C is prtitioning (X, X 0 )ofcone O v such tht X 0 is cone of v. Nodev is the cut root. The cut-set of the cut, denoted V (X, X 0 )orv (C), consists of the inputs of cone X 0,orinput(X 0 ). A cut C is K-fesible if V (C) K, whichmensx 0 cn be implemented by K-LUT. A Boolen network is l-bounded if input(v) l for ech node v. In this work, ll initil networks re 2- bounded. If network is not 2-bounded, we cn trnsfer it into 2-bounded network using gte decomposition. We ssume tht the timing model of circuit is directed cyclic grph G = {V, E}, wherev is set of vertices nd E is set of edges (see Fig. 2 [14] for n exmple of timing constrint grph nd relted definitions). The edges of the grph re ssocited with delys. The begin set B(G) is set of vertices in G which hve no incoming edges. The set E(G) is set of vertices in G which hve no outgoing edges. A prefix pthof G is pth strting from vertex in B(G), nd suffix pthof G is pth tht s t vertex in E(G). A complete pth of G is both prefix pth nd suffix pthofg. A timing constrint α is specified by constrint type nd timing constrint grph G α,where G α is subgrph of G. A complete pth of G is pth of timing constrint α if nd only if it covers complete pth of G α. The constrint type of timing constrint specifies whether the timing constrint is flse-pth constrint or multi-cycle constrint with exct number of cycles. Our lgorithm ssumes timing constrint grphs re given. We use widely ccepted unit dely model [18], where ech LUT on pth contributes one unit dely. If we tret regulr pths s specil cse of multi-cycle pths with one clock cycle requirement, nd flse pths s specil cse of multi-cycle pths with infinity clock cycle requirement, the optimum mpping depth of 2-bounded circuit N under timing constrints is the minimum number d o such tht there is mpped circuit of N, in which the depth of every constrint pth is limited by d o cycles, wherecycles is theclockcyclerequirementofthetimingconstrintofthe pth. The mpping problem for depth-optiml FPGA with multi-clock domins is to cover given 2-bounded Boolen network with K-fesible cones, or equivlently, K-LUTs in such wy tht the optiml mpping depth is gurnteed under timing constrints due to multi-clock domins. 8 4 clock reset Dt PRS D Q CLR D Q PRS PRS D ff_q3 Q D ff_q4 Q ff_q5 CLR CLR Single-Cycle Opertion D Figure 3: Exmple of multi-cycle timing constrint. 3. FPGA Technology Mpping with Timing Constrints 3.1 Overll Algorithm In previous cut-enumertion-bsed dely optimum FPGA technology mpping lgorithms [18, 19, 20, 21], minimum mpping depth is computed t the of the cut enumertion process. This minimum mpping depth is ssigned to be the required time for ech PO, nd required times re propgted from POs to PIs in the cut selection phse. In our lgorithm considering timing constrints, there re multiple rrrivl/required times on node. Our lgorithm tkes circuit nd timing constrints in SDC (Synopsys Design Constrints) formt s inputs. We convert every timing constrint into timing constrint grph, nd generte timing constrint cores for ll constrints (see Section 3.6 for definition of timing constrint cores). Then different rrivl times corresponding to different timing constrints re propgted from PIs to POs in the topologicl order. At the of cut enumertion, we compute the optimum normlized mpping depth (see Section 3.5 for definition). Then, we set different required times on the POs ccording to the vrious timing constrints pplied on them. When we propgte required times from POs bck to PIs in the reverse topologicl order, we choose the cut for ech node tht fulfills ll the timing requirements nd hs smll cost. The detils will be provided in the rest of this section. In Section 3.2, we present multi-cycle circuit model tht is used to generte testing circuits in our experiments; in Section 3.3, we introduce our dt structure; in Section 3.4, we present the bsic procedure of propgting constrint delys during cut enumertion; in Section 3.5, we present how to crry out cut selection nd generte mpping solution for node considering vrious constrint delys; in Section 3.6, we introduce the concept of constrint cores tht cn help to resolve constrint conflicts; nd we provide nlysis of our lgorithm in Section A Multi-Cycle Circuit Fig.3showscircuitmodelwithmulti-cyclepths[9] to serve the purpose of evluting our lgorithm. We generte our testing circuits using this model, becuse we cnnot ccess ny rel circuit with timing constrints. Even though this circuit model only shows multi-cycle timing constrints, our lgorithm is generl enough nd will work for ny type of circuits with multi-clock domins. The circuit model cn lso help to understnd why there re multiple rrivl/required times on one node when vrious timing constrints re considered. The upper prt of the figure shows the dt pth, nd the middle prt is the control flip-flops. The initil stte of the control flip-flops fter the reset signl is (ff q3,ff q4,ff q5 )=(1, 0, 0), nd these flip-flops chnge s (0, 1, 0), (0, 0, 1), (1, 0, 0), (0, 1, 0), (0, 0, 1),... synchronizedwiththeclocksignl. ThegteMUX1 selects input from pin Dt only when ff q3 = 1, nd the gte MUX2 selects input from pin MC out only when ff q5 =1. It is esy to know tht the combintoril pth from ff in to ff out is two-cycle pth. Fig. 4 shows decomposition of Q 371

3 D in D in w v 1 C C e 1 u Q out MC out ff_q5 Q out ff_q5 MC out C 2 v 2 e 2 Figure 4: Decomposition of gte MUX2 in Fig. 3. In this exmple, both AND gte 2 nd the OR gte cross two different timing constrints, one is for regulr pths, nd the other is for multi-cycle pths. The AND gte 1 hs only one rrivl/required time. The AND gte 2 nd the OR gte both hve two rrivl/required times. MUX2inFig.3. InFig.4,theANDnode 2 hs two rrivl times, one from ff q5 which comes from regulr pth, nd the other from MC out which comes from two-cycle pth. TheORgteinFig.4lsohstworrivltimes,butthe AND gte 1 only hs one rrivl time for regulr pths. Similrly, both the AND gte 2 nd the OR gte hve two required times, nd the AND gte 1 hs only one required time. 3.3 Dt Structure When we consider mny timing constrints in the technology mpping lgorithm, different nodes from the sme cut set my hve different sets of timing constrints. In Fig. 5(), for exmple, both nodes v 1 nd v 2 belong to the cut set of the cut C 1. Node v 1 is not covered by ny timing constrint grph, but node v 2 is contined by timing constrint grph G α. However, the fct tht cut node is covered by constrint grph does not imply tht there lwys exists constrint pth going through this cut node nd the cut root. In Fig. 5(), node v 3 is covered by the constrint grph G α, but the cut root u 2 is not covered by ny constrint grph, so ny pth through nodes v 3 nd u 2 is regulr pth. With bove observtions, we design the following dt structure in our lgorithm. Given cut C rooted on node u, for ech node v V (C) (note tht V (C) isthecutset of C), there is timing set D(C, v),ndechitem,nmed dely item, in timing set S D(C, v) providestheinformtion of constrint pth going through both v nd u. More specificlly, S is triple S =< α,f,d >,where α identifies which timing constrint the pth goes through (α = 0 for regulr pths); f is flg indicting whether the pth contins complete constrint pth (f = f c), or prefixconstrint pth (f = f p)sofr;ndd is the rrivl time in the corresponding timing constrint. Given timingsetd(c, v), let f S(α, C, v) denotethedelyitem u 1 C 1 v 1 v 2 () : nodes of the begin set : nodes of the set : timing constrint v 3 u 2 C 2 v 4 u 2 C 2 v 3 u 1 C 1 v 1 v 2 (b) From Regulr pths Figure 5: Exmples for dt structure illustrtion. Figure 6: Cut C is generted by combining C 1 nd C 2. corresponding to α, ndf (α, C, v), f f (α, C, v), f d(α, C, v) denote the timing constrint identity field, flg field, nd rrivl time field of f S(α, C, v), respectively. If D(C, v) do not hve n item corresponding to timing constrint α, then f S(α, C, v), f (α, C, v), f f (α, C, v) donotexist,nd f d(α, C, v) isinfinity. Note tht the triple form of dely item, < α,f,d >, is used to construct dely item, while f S(α, C, v) is used to select dely item from D(C, v). In Fig. 5(b), for cut C 1 rooted t node u 1, {v 1,v 2} V (C 1), we hve D(C 1,v 1)={< α,f p,x 1 >} nd D(C 1,v 2)={< 0,,x 2 >}(for regulr pths, we do not cre bout the flg field), where x 1 nd x 2 re some dely vlues. For cut C 2 rooted t node u 2, v 3 V (C 2), we hve D(C 2,v 3)={< α, f c,x 3 >, < 0,,x 4 >} since there re both complete pths of timing constrint α nd regulr pths going through v 3 to u 2. Given D(C 2,v 3)={< α,f c,x 3 >, < 0,,x 4 >}, wehve f S(α, C 2,v 3) =< α,f c,x 3 >, f S(0,C 2,v 3) =< 0,,x 4 >, f d(α, C 2,v 3)=x 3,ndf d(0,c 2,v 3)=x Arrivl Time Genertion Timing sets re computed long cut enumertion. For PI node u, it only hs one trivil cut C, ndv (C) ={u}. If the PI node u belongstoboththebeginsetndthe set of timing constrint α, then<α,f c, 0 > D(C, u); if u only belongs to the begin set of timing constrint α, then <α,f p, 0 > D(C, u); if u does not belong to the begin set of ny timing constrint, then D(C, v) ={< 0,,0 >}. For n internl node u with two fnins v 1 nd v 2,cutC rooted t u is generted by combining one cut C 1 rooted t v 1 nd nother cut C 2 rooted t v 2.Weonlyprocessthecse when C is K-fesible. Let e 1 denote the edge from v 1 to u, nd e 2 denote the edge from v 2 to u (see Fig. 6). Since we use the topologicl order trversl, the timing sets of V (C 1)nd V (C 2) re known when we combine cuts C 1 nd C 2 to from cut C. The timing sets of V (C) re either computed from those of V (C 1)ndV (C 2), or generted by the cut itself when u belongs to the begin set of some timing constrints, s shown by Algorithm 1. For ny node w V (C 1), it is lso true tht w V (C). Initilly, timing set D(C, w) is empty. Algorithm 2 exmines every dely item S =< α, f, d > D(C 1,w). For ech dely item S =< α,f,d>, if α = 0 (corresponding to regulr pths), we dd dely item <α,f,d>to D(C, w). If f = f c,thereexistspth from PI to v 1 through w which covers complete pth of timing constrint α, nd we lso dd <α,f c,d>to D(C, w). If f = f p nd e 1 does not belong to timing constrint α, there is no pth from PI to u through w tht covers complete pth of α, so we dd < 0,,d > to D(C, w). If f = f p,nde 1 is n edge of the timing constrint α, wedd <α,f p,d > to D(C, w). Furthermore, if u belongs to the set of the timing constrint α, we chnge flg f p to f c. After we process ll the nodes in V (C 1), we process nodes in V (C 2) in similr wy in Algorithm 1. At the of Algorithm 1, we check whether u belongs to the begin set of timing constrint. If u belongs to the begin set of timing constrint β, wewilldd<β,f p,d> to D(C, w) for ll w V (C), where d is the mximum of ll dely vlues in D(C, w), nd we lso remove the dely item corresponding to the regulr pths from D(C, w) (note tht the regulr pth timing informtion my be regenerted lter if there is prefix pth going out of the timing constrint grph 372

4 Algorithm 1: Generte timing sets for cut Input: C, C 1,C 2 :threecuts,c is formed by combining C 1 nd C 2 Output: timingsets begin u root of C; for w V (C) do D(C, w) ø; /*timing sets propgtion*/ for w V (C 1) do propogte timing set(w, e 1,C,C 1); for w V (C 2) do propogte timing set(w, e 2,C,C 2); /*timing sets genertion by the cut itself*/ for timing constrints β stisfying u B(G β) do for w V (C) do d 0; for <β,f,d 0 > D(C, w) do if d 0 >dthen d = d 0 ; f = f p; if u E(G β) then f = f c; D(C, w) {< β,f,d>} D(C, w); Remove dely item f S(0,C,w)fromD(C, w); without going through set nodes of timing constrint β). When u belongs to the begin set of timing constrint, we lso check whether u belongs to the set of the timing constrint. If u belongstoboththebeginsetndthe set of timing constrint, we chnge the flg from f p to f c in the bove process. After we compute the timing sets relted to ll the cuts of node u, we will compute the rrivl times of different timing constrints on u. We ssign timing set D n(u) to node u, which is very similr to the timing set we defined before. Let C(u) denotellthek-fesible cuts rooted t u. For every timing constrint α tht covers u, wedd < α, f, d α > to D n(u), where d α = MIN{MAX{f d(α, C, w) w V (C)} C C(u)} nd f is equl to ny f f(α, C, w) if f S(α, C, w) exists(wecnprovethtf f (α, C, w) islwys the sme for ny C C(u) ndw V (C) iff S(α, C, w) exists). In cut-enumertion-bsed lgorithm, there is trivil cut C 0 for ech node u, ndv (C 0 )={u}. We hve described how to generte timing set for the trivil cut of PI node. For n internl node u, D(C 0,u)={<α,f,d+1 > <α,f,d> D n(u)}, becuse trivil cut lwys strts new level in cut-enumertion-bsed lgorithms. It is possible tht one pth belongs to multiple timing constrints, which introduces timing constrint conflicts. We will tlk bout how to hndle this issue in our lgorithm in Section Mpping Solution At the of the cut enumertion, we know ll the timing informtion for every timing constrint. For PO node u, wecheckeverydelyitems =< α,f,d>from its timing set D n(u). If α = 0, there is t lest one regulr pth from PInodetou; if α 6= 0 nd f = f c, then there is t lest one pth from PI node to u contining one complete pth of the timing constrint α. Wedefine normlized depth for ech dely item. If α =0(orα 6= 0ndf = f p), the normlized depth is d. If α 6= 0ndf = f c,the normlized depth is dd/cyclese, wherecycles is the number of cycles llowed in the multi-cycle pth constrint α, nd cycles is infinity for flse-pth constrint. The optimum normlized mpping depth is the mximum of ll normlized Algorithm 2: propogtetiming set(w, e, C, C 0 ) begin u root of C; for <α,f,d> D(C 0,w) do if α =0or f = f c then dd dely item(< α,f,d>, D(C, w)); else /*f = f p*/ if e 6 E(G α) then dd dely item(< 0,,d>, D(C, w)); else if u E(G α) then f f c; dd dely item(<α,f,d>, D(C, w)); Algorithm 3: dd dely item(<α,f,d>,d(c, w)) begin if f S(α, C, w) exists then if f d(α, C, w) >dthen d f d(α, C, w); Remove f S(α, C, w) fromd(c, w); D(C, w) D(C, w) {<α,f,d>}; depths. For illustrtion purpose, we cn think of optimum normlized mpping depth s the minimum clock period of the mpped circuit under unit dely model. For regulr pth with depth d, the clock period should be equl to or lrger thn d to stisfy the pth timing. For multi-cycle pth with depth d, the clock period should be equl to or lrger thn dd/cyclese to stisfy the pth timing. Sme with the previous cut enumertion bsed technology mpping lgorithm [18], we crry out cut selection procedure in the reverse topologicl order from POs to PIs. However, we set different required times on the POs ccording to the vrious timing constrints pplied on them. Let d o denote the optimum normlized mpping depth. The POs with regulr pths will hve required time with vlue of d o for regulr pths. The POs with timing constrint α will hve required time with vlue of d o cycles for the timing constrint α. The required times will be propgted from POs to PIs in the cut selection stge. To pick which cut to mp node is the key for high mpping qulity. Different required times due to different timing constrints offer opportunities to sve mpping cost under the timing constrints. In our lgorithm, when we mp node u, we will exmine ll the cuts on u nd try to find the best one tht fulfills ll the timing requirements nd lso reduces the mpping cost. The mpping cost of cut is computed in similr wy s tht in [18]. To mke sure the timing constrints re met, ech input on the exmined cut needs to be checked ginst ll of its required times ssocited with its timing constrints. After the best cut is picked, required times on u will be propgted to the inputs of the cut ccording to the timing constrints on the inputs respectively. 3.6 Timing Constrint Cores There is constrint conflict if there is pth tht belongs to more thn one timing constrints. However, different timing constrints should hve different priorities. If pth belongs to multiple timing constrints, we should only consider the timing constrint with the highest priority. However, we cnnot exmine pths one by one to determine whether pth belongs to multiple timing constrints due to exponentil number of pths. It is lso very hrd to determine whether multiple rrivl times t PO come from the sme pth or different pths. Thus, it is very importnt 373

5 to design n effective method to hndle this problem. In this subsection, we introduce concept clled timing constrint core to resolve constrint conflicts. Definition 1. Given timing constrint α, the timing constrint core of α, K(α), is the set of nodes tht cnnot be reched without going through B(G α) nd E(G α) from outside of G α. With this definition, we immeditely hve the following theorem: Theorem 1. Given timing constrint α, every complete pth going through one node of K(α) ispthofthe timing constrint α. For node u, wedefinethecoretimingconstrintofu s follows: Definition 2. Given node u, its core timing constrint, K n(u), is the timing constrint α with the highest priority stisfying u K(α). Ifu does not belong to ny timing constrint core, K n(u) does not exist. During the cut enumertion process, when we process node u, wefilter out ll the timing informtion relted to timing constrints with lower priorities thn K n(u), if K n(u) exists. By filtering out low priority timing constrints, we utomticlly resolve constrint conflicts mong low priority timing constrints nd K n(u). It is possible tht there is high priority timing constrint grph G β covering u. Inthis cse, it is true tht u 6 K(β), otherwise K n(u) 6= α. There must exist complete pth going through u tht does not cover complete pth of β, but covers complete pth of α. So, we need to propgte timing informtion for both α nd β when we process u. 3.7 Complexity nd Optimlity Regrding to the runtime of our lgorithm, we hve the following theorem: Theorem 2. The runtime of processing cut is liner to the number of totl timing constrints. With this theorem, we know tht the runtime of our lgorithm is incresed by t most n t times, where n t is the totl number of timing constrints, compred to the previous lgorithm [18] without considering timing constrints. Furthermore, we cn show tht our lgorithm is ble to produce optimum normlized mpping depth s defined in Section Theorem 3. Our FPGA technology mpping lgorithm is ble to produce mpped circuit with the optimum mpping depth when timing constrints re considered. 4. Experimentl Results Our experiments re crried out on desktop PC with 2.4 GHz Intel(R) Xeon(TM) CPU. The OS is Red Ht Linux 8.0, nd we use gcc to compile our progrm. Becuse we cnnot get ccess to ny rel circuit with timing constrints, we designed new set of benchmrk circuits from the 20 lrgest MCNC benchmrk circuits. We use the templte in Fig. 3 to derive our benchmrk circuits. We rndomly pick two circuits from the 20 lrgest benchmrk circuits, nd plce the circuit with lrger mpping depth into the multi-cycle prt of Fig. 3, nd plce the other circuit into the singlecycle prt. In this wy, we generte 20 new benchmrk circuits, run both our lgorithm nd DAOmp on these circuits, nd report the results. Note tht we compre with DAOmp becuse DAOmp is recent depth-optiml mpping lgorithm without resynthesis (i.e., without chnging the originl circuit structure during mpping). We believe our lgorithm cn be exted to work on other mpping frmeworks, such s the ABC mpper [21], where resynthesis choices re crried out. This will be considered in our future work. Timing Constrints (SDC) Benchmrk circuit Our Mpper TimeQuest Mpped circuit (BLIF) BLIF to VQM Converter VQM file Qurtus_mp Qurtus_fit Synthesized circuit Timing report DAOMp TRUE_WYSIWYG_ FLOW = ON Figure 7: Experimentl results. USE_TIMEQUEST_TIMING_ ANALYZER = ON We use K = 5 for ll circuits in the experiment. The mpped circuits re in Berkeley Logic Interchnge Formt (BLIF).Fig.7showsourexperimentlflow. In order to use the commercil timing nlysis engine, TimeQuest Timing Anlyzer (vilble from Alter s Qurtus II softwre), we write converter from BLIF formt to Verilog Qurtus Mpping (VQM) formt. We build project for ech VQM file. We set TRUE WYSIWYG FLOW to ON so tht Qurtus II will not optimize nd remp our circuits, nd we set USE TIMEQUEST TIMING ANALYZER to ON so tht Qurtus II will consider timing constrints during plcement nd routing stge. We use Synopsys Design Constrints Formt (SDC) to specify timing constrints, nd the multi-cycle prt in Fig. 3 is set to hve multi-cycle timing constrint of two clock cycles. We use the sme Strtix II device for both DAOmp nd our lgorithm. We run Qurtus II commnds qurtus mp 1,ndqurtusfit to synthesize, plce nd route the circuits. Then, we use the TimeQuest Timing Anlyzer to report timing informtion for ll circuits. In order to find the minimum clock period of mpped circuit,weruntheexperimentlflow for multiple itertions, nd we set different clock period vlue in ech itertion (using the SDC commnd crete clock). For ech itertion, the TimeQuest Timing Anlyzer reports whether the clock period is chievble or not. If the specified clock period is not chievble under the multi-cycle timing constrints, we increse the clock period vlue in step of 0.5ns, nd repet the flow gin. If the specified clock period is chievble, we decrese the clock period vlue lso in step of 0.5ns, nd run the flow. The initil clock period is 6ns. After few itertions, we will know the minimum clock period of the mpped circuit chievble fter plcement nd routing. Tble 1 shows our experimentl results. The first column shows two circuits of the 20 lrgest MCNC benchmrks we used to generte circuit with timing constrints. The first circuit corresponds to the single cycle prt, nd the second circuit corresponds to the multi-cycle prt of the new circuit. The column PIs (POs) shows the numbers of primry inputs (outputs) in our new circuits. The column LUT s DAO (LUT s our) shows the numbers of LUTs of the mpped circuits produced by DAOmp (our mpper). The column DAO ( our) shows the minimum clock periods chievble for the mpped circuits by DAOmp (our mpper). The column Impr perf shows the performnce improvements of our lgorithm over DAOmp. Since the circuit performnce is mesured by the clock frequency, the reciprocl of the clock period, the performnce improvement is computed by 1 The commnd qurtus mpisusedtoprepretheinput files for lter process. It does not optimize or remp our circuitssincewesettruewysiwyg FLOW to ON. 374

6 Tble 1: Experimentl Dt. Circuit PIs POs LUT s our LUT s DAO our(ns) DAO(ns) Impr perf (%) lu4+clm lu4+diffeq lu4+tseng pex2+s pex2+tseng pex4+elliptic pex4+frisc des+clm ex1010+tseng ex5p+diffeq ex5p+elliptic misex3+diffeq misex3+tseng pdc+tseng seq+diffeq seq+tseng spl+clm spl+diffeq spl+s spl+tseng Averge the formul 1/our 1/ DAO 1/ DAO. From the tble, we know tht our lgorithm is ble to improve circuit performnce by 16.8% on verge. The reson tht our lgorithm is ble to chieve better circuit performnce is very intuitive. Our mpping lgorithm is ble to mp the multi-cycle prts of circuit with lrger depths, nd mp the norml prts with shorter depths, while previous lgorithms do not hve such cpbility. In previous cut-enumertion-bsed lgorithms, timing constrint pths nd regulr pths hve no difference when they re used to compute the optimum mpping depth, so the optimum mpping depth computed by previous lgorithms is generlly lrger thn tht computed by our lgorithm. Since this optimum mpping depth is set s the required time of the circuit, previous lgorithms t to mp regulr pth with lrger depth thn our lgorithm. As result, they re likely to produce mpped circuit with lrger clock period fter plcement nd routing. 5. Conclusions In this pper, we presented n FPGA technology mpping lgorithm considering multi-clock domins. We developed method tht could propgte timing informtion for vrious timing constrints through the network. We worked on timing constrint grphs nd processed multiple rrivl/required times for ech node in the network. We lso introduced concept clled timing constrint core, which couldbeusedtoresolveconstrintconflicts. Our lgorithm could produce mpped circuit with the optiml mpping depth under multi-clock timing constrints. Compred to previous FPGA technology mpping lgorithm tht did not consider timing constrints, our lgorithm is ble to improve circuit performnce by 16.8% on verge fter plcement nd routing. 6. References [1] M. Hutton et l. Efficient sttic timing nlysis nd pplictions using edge msks. In FPGA, pges , [2] J.Benkoskietl.Timingverifiction using stticlly sensitizble pths. TCAD, 9(10): , [3] D.H.C. Du, S.H.C. Yen, nd S. Ghnt. On the Generl Flse Pth Problem in Timing Anlysis. In DAC, pges , [4] S. Perremns, L. Clesen, nd H. De Mn. Sttic timing nlysis of dynmiclly sensitizble pths. In DAC, pges , [5] P.C. McGeer nd R.K. Bryton. Efficient lgorithms for computing the longest vible pth in combintionl network. In DAC, pges , [6] D. Brnd nd V.S. Iyengr. Timing nlysis using functionl nlysis.techniclreport,bmthomsj.wtsonres.center, [7] H.-C. Chen nd D.H.C. Du. Pth sensitiztion in criticl pth problem. TCAD, 12(2): , [8] A.P. Gupt nd D.P. Siewiorek. Automted Multi-Cycle Symbolic Timing Verifiction of Microprocessor-bsed Designs. In DAC, pges , [9] K. Nkmur et l. Witing flse pth nlysis of sequentil logic circuits for performnce optimiztion. In ICCAD, pges , [10] K. Nkmur et l. Multi-clock pth nlysis using propositionl stisfibility. In ASPDAC, pges 81 86, [11] K.P. Belkhle nd A.J. Suess. Timing nlysis with known flse sub grphs. In ICCAD, pges , [12] E. Goldberg nd A. Sldnh. Timing nlysis with implicitly specified flse pths. In VLSI Design, pges , [13] D. Bluw, R. Pnd, nd A. Ds. Removing user-specified flse pths from timing grphs. In DAC, pges , [14] S. Zhou et l. Efficient sttic timing nlysis using unified frmework for flse pths nd multi-cycle pths. In ASP- DAC, pges 24 27, [15] Alter StrtixII Device. [online] com/products/devices/strtix2/st2-index.jsp [16] Alter Qurtus II Softwre. [online] com/products/softwre/products/qurtus2/qts-index.html [17] Xilinx ISE Softwre. [online] ise/logic design prod/foundtion.htm [18] D. Chen nd J. Cong. DAOmp: A Depth-optiml Are Optimiztion Mpping Algorithm for FPGA Designs. In IC- CAD, Nov [19] J. Lmoureux nd S. J. E. Wilton. On the Interction between Power-Awre CAD Algorithms for FPGAs. In IC- CAD, [20] V. Mnohrrjh, S.D. Brown, nd Z.G. Vrnesic. Heuristics for Are Minimiztion in LUT-Bsed FPGA Technology Mpping. TCAD, 25(11): , [21] A. Mishchenko, S. Chtterjee, nd R.K. Bryton. Improvements to Technology Mpping for LUT-Bsed FPGAs. TCAD, 26(2): , [22] P. Ashr, S. Dey, nd S. Mlik. Exploiting multicycle flse pths in the performnce optimiztion of sequentil logic circuits. TCAD, 14(9): ,

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