Analog Front-End Design for 2x Blind ADC-based Receivers. Tina Tahmoureszadeh

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1 Analog Front-End Design for 2x Blind ADC-based Receivers by Tina Tahmoureszadeh A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto c Copyright by Tina Tahmoureszadeh 21

2 Analog Front-End Design for 2x Blind ADC-Based Receivers Tina Tahmoureszadeh Master of Applied Science, 21 Graduate Department of Electrical and Computer Engineering University of Toronto Abstract This thesis presents the design, implementation, and fabrication of an analog frontend (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-1 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies μm 2 and consumes 2.4 mw at 1 Gb/s. Measured frequency responses at data-rates of 1, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 db of high-frequency boost at 1 Gb/s. ii

3 Acknowledgments I would like to thank my supervisor, Professor Ali Sheikholeslami, for his support and guidance throughout this research work. Thanks for making this journey worth taking. I would like to thank my colleagues at Fujitsu, notably Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune, and Bill Walker for their technical help and support over the course of this project. Special thanks to my defense committee: Professor Tony Chan Carusone, Professor Roman Genov, and Professor Teng Joon Lim for their time and valuable feedback. I would like to thank my parents, Farahnaz and Darioush, and my sisters, Tila and Taraneh, for their endless love and support. Even if I could give you not only the whole world, but the whole universe, with all its planets and stars, it will be nothing compared to the sacrifices you have made for me. I am forever grateful to the help and support I constantly received from my research group members, Shayan Shahramian, Siamak Sarvari, Oleksiy Tyshchenko, David Halupka, and Behrooz Abiri. Thanks for always having the time to offer your help. To my girl buddies, Ruslana, Farzaneh, and Azadeh, I wouldn t have made it without you. I owe this to the long supporting, encouraging, and inspiring chats with you. I owe this to the endless tea breaks and our adventurous long walks around the campus. Thanks to Hamed, Karim, Mike, Dustin, and Kentaro for the rest of the unforgettable memories. Last but not the least, my dearest koochooloo warmed up my heart, day and night, so I can be here, writing to close this chapter of my life. iii

4 Contents Acknowledgments List of Figures List of Tables List of Acronyms iii vi viii ix 1 Introduction Motivation Thesis Objectives Thesis Outline Background Wire-line Communication System Transceiver Communication Channel Binary versus ADC-based Receivers ADC-based Receivers Phase Tracking versus Blind Sampling x versus 2x Sampling Rate x blind ADC-based Receiver Aliasing Necessity for an Anti-Aliasing Filter Previous Work Equalization Feed-Forward Equalization (FFE) Previous Work Summary Anti-Aliasing Filter (AAF) Design Anti-Aliasing Filters Active RC Filters G m -C Filters Integration and Dump (I&D) Filters Proposed I&D Scheme iv

5 3.3 I&D Design Methodology and Modeling Design Methodology Behavioural Modeling Behavioural Simulation Results Implementation Circuit Design Circuit Simulation Results Summary Analog Front-End Design (AFE) AFE Architecture AFE Design Methodology and Modeling Design Methodology Behavioural Modeling Behavioural Simulation Results AFE Implementation Cascode-Switching Architecture Reset Cell Architecture Clock Generation Design Circuit Simulation Results Clock Generation Analog Front-End (AFE) Summary Experimental Results Circuit Layout and Equipment Setup Channel Measurements AFE Performance Frequency Response of AFE FFE Performance AAF Performance Summary Conclusions and Future Directions Thesis Contributions Future Work References 72 v

6 List of Figures 2.1 An example of a two connector backplane from Tyco Electronics [12] The effect of the limited channel bandwidth on the ideal NRZ signal ADC-based receiver architectures Extraction of the instantaneous phase (φ inst ) Data decision scheme An example where the sampling theorem is satisfied An example where the sampling theorem is violated (Aliasing) Zero-crossing estimations based on the linear interpolation Equalization in frequency domain Feed-forward and feedback equalization A generic implementation of CTLE FIR implementation of FFE Active RC filter presented in [15] Gm-C filter presented in [17] Comparison between output samples of a rectangular filter and an I&D filter LTI Model of an I&D filter I&D Response Previous I&D worksinthefront-end Proposed AFE for a 2x blind ADC-based receiver including AAF Bandwidth scalability of the I&D scheme φ error plot for phase extraction with/without I&D Input data used for simulations with various T ini T ini = T ini = 12.5% UI = 12.5ps T ini = 25% UI = 25ps Frequency response of the I&D filter from Simulink simulations AAF system block diagram Pulses that drive the 4-way time-interleaved I&D system Architectures considered for the I&D filter design Frequency response of I&D filter generated from circuit simulations A 2x blind ADC-based receiver with the proposed AFE AAF/FFE system block diagram vi

7 4.3 AFE behavioural modeling Zero-pole map of the proposed AFE Cascode-switching implementation Reset cell implementation Clock generation block diagram CMOS logic implementation Half-rate CMOS clock generator implementation CML divider implementation A 2x blind ADC-based receiver with the proposed AFE Timing diagram Simulated nodes in clock generation circuitry Simulated clock generation waveforms at 1 Gb/s Simulated clock generation waveforms at 5 Gb/s Simulated clock generation waveforms at 2 Gb/s Simulated time-domain waveforms of the AFE Simulated frequency response at 1 Gb/s Simulated frequency response at 5 Gb/s Simulated frequency response at 2 Gb/s AFE micrograph Measurement setup S 21 plots Measured vs simulated frequency response (1 Gb/s) Measured vs simulated frequency response (5 Gb/s) Measured vs simulated frequency response (2 Gb/s) Data-rate = 1 Gb/s - Channel loss = GHz Data-rate = 5 Gb/s - Channel loss = GHz Data-rate = 2 Gb/s - Channel loss = GHz Verification of the anti-aliasing filter Jitter tolerance comparison with AAF on/off vii

8 List of Tables 3.1 Simulated 3-dB bandwidths of I&D filter Simulated results of the clock generation circuitry Simulated results of AFE Description of the pin-list Description of the test channels Performance summary viii

9 List of Acronyms AAF anti-aliasing filter AFE analog front-end BER bit error rate BERT bit error rate tester CDR clock and data recovery CML current mode logic CMOS complimentary MOS CTLE continuous time linear equalizer DAC digital-to-analog converter DCD duty-cycle distortion DeMUX demultiplexer DFE decision feedback equalizer DSP digital-signal processor FFE feed-forward equalizer FIR finite impulse response Gb/s gigabits per second HDMI high-definition multi-media interface IC integrated circuit I&D integration and dump ISI intersymbol interference LSB least-significant bit ix

10 LTI linear-time invariant MOSFET metal oxide semiconductor field effect transistor MSB most-significant bit NMOS negative-channel metal oxide semiconductor NRZ non-return-to-zero PCB printed circuit board PCIe Peripheral Component Interconnect Express PD phase detector PI phase interpolater PMOS positive-channel metal oxide semiconductor PLL phase-locked loop PVT process-voltage-temperature PRBS pseudo-random binary sequence S&H sample-and-hold SATA Serial Advanced Technology Attachment SerDes serializer/deserializer SNR signal-to-noise ratio SONET synchronous optical network UI unit interval USB Universal Serial Bus VCO voltage-controlled oscillator VNA vector network analyzer x

11 1 Introduction High definition television, voice over Internet, and even gaming systems are creating a large demand for faster data transmission which could range from chip-to-chip to over continental distances. Established industry standards such as high-definition multi-media interface (HDMI), Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA) have driven this market for years. New circuit innovations are sought everyday to carve out a path for multi-gigabits per second (Gb/s) data transmission. 1.1 Motivation In a typical high-speed transceiver, serial data streams are sent from a transmitter to a receiver via a communication channel. The existing low-cost channel materials demonstrate low-pass behaviour at 1 Gb/s and above. This causes the transmitted pulse to spread to over one unit interval (UI) and interfere with its neighbouring symbols. Known as intersymbol interference (ISI), this phenomenon complicates the task of the data recovery on the receiver side. The most common practice to counteract the deteriorating channel effects is to use equalization. Equalizers can be implemented in the analog or digital domain. Binary receivers [1, 2, 3], use only 1 bit (i.e. the sign) of the received data to recover the data and the embedded clock. ADC-based receivers [4, 5, 6, 7, 8, 9], on the other hand, have access to more than 1 bit (i.e. the sign and the magnitude) of the received signal. In these receivers, a front-end ADC digitizes the input signal and enables more complex equalization circuitry in the digital domain. Blind ADC-based receivers are a sub-category of the ADC-based receivers. They utilize a feed-forward architecture and enable the design of a fully digital receiver. Digital implementation is advantageous since it has low noise sensitivity compared to the analog circuits, facilitates power/area scaling, and improves the flexibility of the design. The focus of this thesis is to explore ways to improve the performance of the 1

12 2 1 Introduction blind ADC-based receivers. The industry standards, mentioned previously, demand supporting a wide range of data-rates and various channel characteristics. Usually, they are required to be fully compatible with prior generations. For example, PCIe 3. that aims for 8 GHz is required to be backward compatible with PCIe 2. and 1. which support 5 GHz and 2.5 GHz, respectively [1]. This shows the significance of designing receivers that cover a large range of data-rates. Current blind ADC-based receivers [4, 5] are limited in their operating data-rate. The main problem is that they rely on the communication channel to perform the necessary anti-aliasing. For a system that covers a wide range of data-rates, the channel bandwidth is not sufficient to filter the transmitted signal at the lower speed. To overcome this disadvantage, our work proposes an analog front-end (AFE) whose bandwidth automatically adjusts with the data-rate. The proposed AFE consists of a combined anti-aliasing filter (AAF) and an equalizer which extends the operating data-rate from 2 to 1 Gb/s. The equalizer turns on when the channel imposes severe attenuation which occurs at the higher speeds. The AAF, as explained above, turns on for low data-rates where the channel does not have enough bandwidth to prevent aliasing. 1.2 Thesis Objectives This thesis presents the design of an AFE for 2x blind ADC-based receivers. The main objectives of this thesis are as follows: Exploring AAF solutions with adjustable bandwidth to expand the applications of 2x blind ADC-based receivers to support multiple data-rates. Investigating the incorporation of an equalizer in conjunction with the bandwidth scalable AAF. Design, fabrication, and measurement of the proposed AFE to prove functionality.

13 1.3 Thesis Outline Thesis Outline The remaining chapters of this thesis are organized as follows. Chapter 2 provides a background on wire-line communication system, ADC-based receivers, and the significance of equalization. It serves as a foundation for the discussions of its following chapters. Chapter 3 presents the design methodology, modeling, and simulation results of the AAF. The design of the complete AFE including both the AAF and the equalizer is presented in Chapter 4 followed by the simulation results. Chapter 5 discusses the measurements of the test-chip. Chapter 6 concludes this thesis and outlines the future directions for this work.

14 2 Background The rapid increase of speed in high-capacity networks and computer systems has created a large demand for high-speed data transmission. Gigabit Ethernet, long-haul optical channels, memory, and chip-to-chip interconnect are applications that directly benefit from the multi-gb/s serial link technology. This chapter presents the main challenges in high-speed signaling along with their commonly used solutions. This material serves as a background to frame the discussions in the following chapters. Section 2.1 introduces a typical wire-line communication system consisting of a transmitter and a receiver block communicating through a wired backplane. Channel impairments that distort the transmitted signal, therefore complicating the task of the receiver, are also discussed in this section. Binary and ADC-based receivers are introduced towards the end of this section as the two well-known receiver architectures. Section 2.2 discusses the ADC-based receivers in more detail to provide the necessary context for the upcoming sections. Sections 2.3 and 2.4 present the necessity for an anti-aliasing filter (AAF) and equalization as a part of the currently employed ADC-based receivers. Section 2.5 concludes this chapter. 2.1 Wire-line Communication System High-speed signaling refers to the exchange of information from a transmitting device to a receiving device at data-rates in excess of 1 Gb/s. The data is transmitted via a physical medium based on which the communication system can be classified as wire-line, wireless, optical, and etc. In the remainder of this section we discuss the building blocks of a wire-line communication Transceiver A generic high-speed transceiver consists of a transmitter on one chip and a receiver on another. The task of the transceiver is to transfer the data from the transmitter to the receiver through a communication channel. This communication channel, which 4

15 2.1 Wire-line Communication System 5 could range from hundreds of feet of cable in network interfaces to less than one foot of a PCB trace in chip-to-chip signaling interfaces, suffers from non-idealities which distort the transmitted signal. The role of the transceiver is to compensate for the losses introduced by the physical channel and recover the data with an acceptable bit error rate (BER). The evolving integrated circuit (IC) technology has enabled the design of the highspeed transceivers. The wire-line backplane, on the other hand, does not advance with the same pace and continues to be the bottleneck. Although a transceiver incorporates other blocks such as drivers, serializers, deserializers, and samplers [11], its main design challenge is attributed to compensating for deteriorating channel effects. In the next section, we study the channel impairments Communication Channel In a wire-line communication system, which is the focus of this thesis, the communication channel carries electrical signals from the source to the destination. This channel could be a twisted pair, coaxial cable, an Ethernet cable, or a USB cable. Although these wire-line channels are of various natures, they impose similar challenges to the designers. A typical channel in serial high-speed signaling consists of connectors, a PCB trace, and cables. A backplane trace, provided by Tyco Electronics [12], is shown in Fig. 2.1(a). It comprises of two line-cards of length 1 connected through a PCB trace of length 2. The material used in both the line-cards and the trace is Nelco 4-13SI. This channel can be modeled as a linear-time invariant (LTI) system with a frequency response plotted in Fig. 2.1(b). The limited bandwidth of this channel, which is an example of a generic wire-line link, attenuates the higher frequency content of the transmitted signal. In the timedomain, this translates to the spreading of the data bit, which consequently interferes with its adjacent bits. This phenomenon, known as intersymbol interference (ISI), is more clearly explained in the following example. If an ideal non-return-to-zero (NRZ) signal is applied to a channel with infinite bandwidth, an undistorted NRZ output is obtained, as shown in Fig. 2.2(a). The corresponding histogram of the samples, shown on the right side, includes an impulse at the zero level and another at the one level, indicating only two possible sample values. Fig 2.2(b), in contrast, presents a similar case except with a practical channel

16 6 2 Background 1" 2" (a) Physical dimensions of the channel S 21 (db) Frequency (GHz) (b) The channel transfer function. Figure 2.1: An example of a two connector backplane from Tyco Electronics [12]. that has a limited bandwidth. The samples, in this scenario, not only depend on the current bit value but also on the bits before and after it. Now, the histogram on the right, consists of more than two impulses, indicating a range around the one and zero levels, as possible sampled values. The samples affected by ISI vary with time and can be misinterpreted by the receiver. The narrower the channel bandwidth is, the longer the UI extends in the timedomain, and the more severely ISI affects the transmitted waveform. The waveform will also fail to reach the full levels of zero and one due to the destructive interference from the neighbouring bits. These effects, if not compensated for, result in erroneous data detection and increased BER of the receiver. The most common practice to compensate for ISI is to utilize equalization to flatten the combined frequency response of the channel and the equalizer. We will see this in more detail in Section 2.4.

17 2.1 Wire-line Communication System 7 Voltage (V) Time (ns) (a) Output of a channel with infinite bandwidth. Voltage (V) Time (ns) (b) Output of a channel with finite bandwidth. Figure 2.2: The effect of the limited channel bandwidth on the ideal NRZ signal Binary versus ADC-based Receivers The task of a receiver is to correctly detect the transmitted signal. Ideally, the highspeed serial data stream would be transmitted across the channel in parallel with the corresponding clock signal. Non-idealities of the communication channels, however, distort the data and the clock differently to the extent that they will no longer be phase-aligned. Furthermore, the increased link cost for carrying the clock signal makes this receiver topology undesirable. Consequently, in today s high-speed transceivers, the clock is not transmitted along with the data and the task of the clock recovery is solely left to the receiver. Generally, receivers are categorized to a binary or an ADC-based receiver according to their front-end sampler. The more traditional receivers are of the type binary as they use a flip-flop at the front-end to sample the incoming signal. The binary sample carries the sign information of the data while discarding the magnitude in-

18 8 2 Background formation. This requires the necessary compensation to be performed before the sampling. Usually, an analog equalizer that precedes the binary sampler takes care of this compensation. ADC-based receivers, however, sample the received signal with an ADC. Each sample is now represented with a set of more than one bit, preserving both the sign and the magnitude information. The extra information about the received signal enables the ADC-based receivers to employ more complex equalization in the digital domain in addition to the analog equalization. As the advancement in wire-line channels lags the rapid increase in the data-rate, the need for intensive compensation of the channel impairments grows. Accordingly, ADC-based receivers which allow for a higher degree of equalization are a promising solution for wire-line multi-gb/s transceivers above 2 Gb/s [13]. 2.2 ADC-based Receivers As discussed in the previous section, ADC-based receivers offer extensive channel loss compensation in digital domain as they use more than one bit to represent each sample. ADC-based receivers can be categorized based on their sampling topology and sampling rate. By sampling topology, as will be discussed in Section 2.2.1, the receivers can be grouped to phase-tracking and blind. Based on the sampling rate, as will be discussed in Section 2.2.3, the receivers can be classified as the baud rate sampling (i.e. 1x) or twice the baud rate sampling (i.e. 2x) Phase Tracking versus Blind Sampling The more well-known ADC-based receivers, known as the phase-tracking receivers, align the sampling clock of the front-end to the phase of the incoming signal via internal feedback [7, 8, 9, 6]. These receivers, shown in 2.3(a), recover the embedded clock in the incoming signal by a phase recovery unit that drives a DAC to generate a control signal for the clock generator unit. The clock generator unit that is either a voltage-controlled oscillator (VCO) or a phase interpolater (PI) is an analog block that produces a sampling clock in phase with the input signal. The design of such analog blocks in multi-gb/s signaling is the main disadvantage of the phase-tracking architectures since they are sensitive to noise, prevent fast production-level testing, and they do not easily port to new technologies.

19 2.2 ADC-based Receivers 9 Decision Recovered Data Input Data ADC Phase Recovery Unit DAC Sampling Clock Clock Generator Control Signal (a) Phase-tracking ADC-based receiver architecture. Ф inst Decision Recovered Data Input Data ADC Phase Detector Filter Ф ave Blind Sampling Clock (b) Feed-forward (blind) ADC-based receiver architecture. Figure 2.3: ADC-based receiver architectures. In an attempt to design an all-digital receiver, blind ADC-based architectures have been introduced [4, 5]. In these architectures, shown in 2.3(b), a blind sampling clock (i.e. a clock signal with no phase relation with respect to the data) samples the incoming data. The newly introduced digital blocks, a phase detector and a digital filter, replace the undesirable analog VCO/PI blocks in the phase-tracking receiver. As the input is sampled blindly, there is no need for a feedback loop to recover the clock. This is why these architectures are also known as feed-forward ADC-based receivers x versus 2x Sampling Rate ADC-based receivers are also classified based on the number of the samples per unit interval (UI) taken from the received signal. The most common sampling rates are twice per UI (i.e. 2x) or once per UI (i.e. 1x). Either of the phase-tracking or blind ADC-based receiver can utilize a baud-rate sampling or twice a baud-rate sampling rate, resulting in total of four possible architectures: 1x phase-tracking, 2x phase-

20 1 2 Background tracking, 1x blind, and 2x blind. As explained in the previous section, phase-tracking receivers depend on a feedback loop to align the sampling clock to the received signal. This feedback loop often demands considerable design and verification resources. One solution to simplify the design is to remove the feedback phase recovery loop and investigate the blind architectures. The motivation to go from the 2x to the 1x sampling rate is to relax the ADC conversion rate, allowing for increased baud rate. The 1x blind ADC-based receivers, however, are not feasible since in the worst case, the samples can fall on the zero-crossings of the input and make the task of the data recovery impossible. In the next section, 2x blind ADC-based receivers are discussed in more detail x blind ADC-based Receiver A block diagram of a blind-sampling ADC-based receiver [4, 5] is presented in 2.3(b). A blind clock samples the received signal twice per UI. The phase detector uses these samples to approximate the instantaneous zero-crossings, φ inst, of each data transition. The value of φ inst is further filtered to generate the average instantaneous phase, φ ave. Both phase values along with the digital samples are sent to the decision block for data recovery. In this section, we explain the functionality of the phase detector and the decision block to provide the context for the remaining chapters. Fig. 2.4 illustrates the task of the phase detector which relies on the linear interpolation between the two consecutive samples of opposite signs. If X and Y are the two samples, the instantaneous phase of X (i.e. φ inst ) can be derived by the similar triangles theorem as shown in equation 2.1. X amp and Y amp are the absolute values of the amplitudes of X and Y respectively. ( ).5Xamp φ inst = UI (2.1) X amp + Y amp The filter that follows the phase detector, subtracts the current value of the φ ave from the φ inst to generate a phase error (φ er ) for every UI. Similar to the phasetracking receiver, φ er is low-pass filtered to recover the φ ave. The decision block, uses φ inst, φ ave, and the value of the 3 consecutive samples to extract the data. First, the average eye-center phase, known as the data-picking phase, φ pick,iscalculatedby adding.5ui to the φ ave. Second, the value of the φ inst and φ pick are compared and the sample closest to the φ pick or furthest to the φ inst is chosen as the decided data

21 2.3 Aliasing 11 value. Fig. 2.5 illustrates this data decision scheme. Y Ф inst Y amp t X amp X.5UI Figure 2.4: Extraction of the instantaneous phase (φ inst ). A B C Picked Data=A Ф pick Ф inst A B C Picked Data=B Ф inst Ф pick Figure 2.5: Data decision scheme. The next section discusses the limitations of the phase recovery scheme used in 2x blind ADC-based receivers. This serves as a necessary background to motivate our proposed design in this work. 2.3 Aliasing A typical signal processing system samples and digitizes the incoming analog signal, performs the necessary digital signal processing, and converts the final output back to the continuous domain to interface with the analog world. The sampling theorem [14] states that a continuous signal, g(t), strictly band-limited to B Hz, can be

22 12 2 Background reconstructed from its samples only if the sampling frequency is more than 2B Hz. Otherwise, the sampling process will not be reversible. G(f) -B B f G s (f)... -2B -B B 2B... f H(f) -B B f Figure 2.6: An example where the sampling theorem is satisfied. Suppose that g(t) with a frequency spectrum, G(f), is sampled at 2B Hz. The frequency spectrum of the sampled signal, G s (f), would be the sum of the replications of the G(f) around the integer multiples of 2B Hz, as shown in Fig The low-pass filter, H(f), with cutoff frequency of B can be used to recover the original signal, g(t). The sampling theorem relies on the assumption that g(t) is strictly band-limited. No practical signal, however, is strictly band-limited, with the result that undersampling always occurs to some degree. This phenomenon, known as aliasing, refers to the overlap of the frequency content as highlighted in Fig Once the signal is aliased, it is impossible to differentiate between the frequencies in band and out of band. To combat the effects of aliasing, low-pass anti-aliasing filters are placed prior to the sampler to attenuate the higher frequency content of the signal. Although ADCbased receivers recover one bit per UI and not the actual transmitted pulse waveform, being a sampled system, they need to deal with aliasing. The next section discusses the aliasing issues specific to the design of the 2x blind ADC-based receivers.

23 2.3 Aliasing 13 G(f) -B B f G s (f)... -2B -B B 2B... f Figure 2.7: An example where the sampling theorem is violated (Aliasing) Necessity for an Anti-Aliasing Filter The phase recovery scheme employed in 2x blind ADC-based receivers [4, 5] was described in Section The scheme relies on the linear interpolation between the two consecutive samples of opposite sign. This interpolation leads to erroneous estimation of the zero crossings and reduced jitter tolerance if the received signal contains sharp transitions. Fig. 2.8 compares the results of the interpolation on an ideal signal against a filtered one. Linear interpolation gives a far better estimation of the zero-crossings when the signal is filtered as opposed to when it is not. The 2x blind ADC-based receivers reported so far [4, 5] leave the task of antialiasing to the communication channel. Therefore, they can not be applied to the standards where the backplane trace is as short as a few centimeters as in PCIe. To expand the applications of the 2x blind ADC-based receivers, it is important to incorporate an anti-aliasing filter at the front-end to reduce aliasing and improve the jitter tolerance of the receiver Previous Work To date, no anti-aliasing filter has been incorporated in the design of the 2x blind ADC-based receivers. Anti-aliasing filters, however, are used in almost every electronic circuit. In audio systems, they are used for preamplification, equalization, and tone control. Communication systems use them for tuning to specific frequencies. In digital signal processing, the filters avoid the aliasing of the out-of-band noise and interference. These systems primarily utilize low-pass filters prior to the ADC to

24 14 2 Background Voltage (V) Time (ns) (a) Ideal signal. Voltage (V) Time (ns) (b) Filtered signal. Figure 2.8: Zero-crossing estimations based on the linear interpolation. eliminate the undesired aliased information in the signal path. Op-amp RC filters [15, 16] are attractive anti-aliasing solutions as they offer low noise and high dynamic range. While feedback is mainly responsible for these desired features, it limits the bandwidth of the filters. G m -C (transconductance-c) filters [17, 18] are more suited for high-frequency performance as they eliminate the feedback. Section 3.1 discusses the different types of anti-aliasing filters in more detail. 2.4 Equalization As explained in Section 2.1, the signal that travels from the transmitter to the receiver is distorted by the non-idealities of the channel. Limited channel bandwidth disperses the current UI in the time-domain such that it interferes with its neighbouring UIs. The most common way to cancel ISI is to use equalization to make the cascade of the channel and the equalizer have a flat frequency response, as shown in Fig. 2.9.

25 2.4 Equalization 15 f f f Channel x Equalizer = Channel & Equalizer Figure 2.9: Equalization in frequency domain. Equalization can be performed on the transmitter side [19, 2, 21], the receiver side [5, 22, 23], or both [9, 24, 25]. In the remainder of this section we focus on the receiver-side implementations of the equalization Feed-Forward Equalization (FFE) Equalization [26] at the receiver can be performed in a linear or a non-linear manner. The former has a feed-forward architecture while the latter uses a feedback, as shown in 2.1. Feed-forward equalizers (FFE) do not have a feedback path and can be implemented either as a continuous time linear equalizer (CTLE) or a finite impulse response (FIR) filter. A common way to implement CTLE is a differential pair with source degeneration consisting of a capacitor in parallel with a resistor [27]. The capacitor becomes a short at high frequencies which increases the gain and compensates for the channel losses. Fig shows a generic schematic of this approach along with the corresponding frequency response. This approach is limited by the gain-bandwidth product of the source-coupled differential pair and if designed well can provide 4-6 db gain/stage at 1 Gb/s in 9-nm CMOS technology [28]. FIR Input Data FFE - + Recovered Data Feed-forwad Feedback Figure 2.1: Feed-forward and feedback equalization.

26 16 2 Background H(f) V i At HF f Figure 2.11: A generic implementation of CTLE. A 2-tap FIR implementation of the FFE is shown in Fig In this realization, equalization is achieved by subtracting a fraction of the previously sampled data from the current sample. This fraction (α 2 /α 1 ) can be adjusted to obtain the required high-frequency boost to counteract the channel attenuation. For severe cases of ISI, FIR filter can be generalized to have more taps to account for the disturbance of more neighbouring bits. Analog FIR filters are often not a suitable choice since the analog delay cells exhibit sensitivity to noise and process-voltage-temperature (PVT) variations. ADC-based receivers, on the other hand, facilitate the use of digital FIR filters as FFE. In digital FIR filters, equalization is performed on the digital presentations of the incoming data. Input Data α 1 Σ - Equalized Data Delay α 2 2-tap Delay α α n n-tap Figure 2.12: FIR implementation of FFE.

27 2.5 Summary 17 As mentioned above, linear equalization amplifies the high-frequency content of the data; this also amplifies the high-frequency noise which reduces the signal-to-noise ratio (SNR) and increases the BER. Noise enhancement problem can be avoided by employing non-linear equalization such as the decision feedback equalizer (DFE) presented in Fig In this technique, the decided bit drives the equalization eliminating the noise from the received signal. In an ADC-based receiver, on the other hand, DFE enhances the quantization noise introduced by the ADC. Therefore, it is a good idea to employ both an analog FFE and a digital FFE or DFE in ADCbased receivers to minimize BER degradations due to both the high-frequency and quantization noise Previous Work ADC-based receivers are potential solutions for data-rates above 2 Gb/s [13] since they enable complex equalization to cancel the deteriorating channel effects. The 2x blind ADC-based receiver presented in [5] employs a linear analog equalizer prior to the ADC plus a digital FFE following the ADC. The analog equalizer provides a nominal gain of 6 db at 2.5 GHz by using an RC-degenerated differential pair designed in 65-nm CMOS. The digital FFE, implemented as a half-a-ui-spaced 2- tap FIR filter, further equalizes the digital signal. The combined analog and digital equalization is capable of compensating 15 db of signal loss caused by the cable. Future chapters explain our proposed architecture to achieve almost the same boosting effect except with an all-analog implementation. This is useful when the ADC quantization noise becomes a limiting factor in the design; this occurs when the ADC resolution is chosen to be low for power-saving purposes. 2.5 Summary This chapter provided an introduction on wire-line communication systems explaining the roles of a receiver, a transmitter, and an equalizer. The signal degradations due to the communication channel were studied and the methods to counteract these effects were presented. The ADC-based receiver architecture was introduced as a potential solution for data-rates of 2 Gb/s and above. It was explained that the current ADCbased receivers lack anti-aliasing filters at the front-end. In the following chapters,

28 18 2 Background we present our solution to this problem expanding the applications of the ADC-based receivers to standards that support multi data-rates and a variety of channels.

29 3 Anti-Aliasing Filter (AAF) Design Anti-aliasing filters are widely used in today s data acquisition systems. These types of systems consist of a front-end sampler, an ADC, and digital-signal processor (DSP) circuitry. The anti-aliasing filter, which is placed prior to the sampler, ensures that the input signal does not contain frequencies higher than half the sampling rate. This guarantees the reconstruction of the input signal. In 2x blind ADC-based receivers, aliasing prevents the accurate phase recovery of the input. As a result, it is important to investigate solutions to prevent aliasing in these receivers and expand their operating input frequency range. This chapter presents the design of the anti-aliasing filter (AAF) portion of the proposed analog front-end (AFE). Section 3.1 studies various ways to implement the desired AAF. Section 3.2 selects the integration and dump (I&D) scheme as the desired solution and presents the proposed architecture. Section 3.3 discusses the design methodology for the I&D filter along with the behavioural modeling and simulation results. Section 3.4 describes the circuit implementation of the I&D filter followed by the simulation results. Section 3.5 concludes this chapter. 3.1 Anti-Aliasing Filters As discussed in Section 2.3, in order for 2x blind ADC-based receivers to accommodate data-rates ranging from 2-1 Gb/s, it is crucial that the AFE design includes an AAF whose bandwidth adjusts with the data-rate. This section investigates the use of active RC filters, G m -C filters, and I&D filters as possible candidates for the desired AAF. I&D is selected since it offers easy bandwidth programmability controlled by the data-rate Active RC Filters Active RC filters have largely been used to implement an AAF in data-acquisition systems. Operational amplifiers, resistors, and capacitors constitute the building 19

30 2 3 Anti-Aliasing Filter (AAF) Design blocks of such filters [29, 3]. While operational amplifiers provide voltage gain and high dynamic range, they are bandwidth limited and therefore not suitable for highspeed (Gb/s) systems. To combat this disadvantage, research continues to explore more circuit techniques to design op-amps with large bandwidth. A CMOS AAF with RC feedback is presented in [15] that achieves a maximum pole frequency of 5 MHz. The op-amp utilized in this design (shown in Fig 3.1) consists of three main stages with three local common-mode feedbacks and two feed-forward stages for compensation. Although operating at a comparatively fast speed amongst active RC filters, the design suffers from a low phase margin of 2. The tunability of the bandwidth of an active RC filter can be achieved by digitally selecting a number of parallel resistors or capacitors. There is no well-known approach to adjust the bandwidth according to the data-rate. For this reason and due to the low frequency operation of the op-amps, active RC filters are not suitable for the AFE targeting high-speed ADC-based receivers. Out- Out+ In + In - Figure 3.1: Active RC filter presented in [15] G m -C Filters G m -C filters (transconductance-c filters) offer higher bandwidth than their active RC counterparts [29, 3]. In G m -C filters a differential input voltage is converted to current by the transconductance cell and integrated on a capacitor. Therefore, the key to designing fast filters of this type is to use fast transconductors.

31 3.1 Anti-Aliasing Filters 21 A transconductor circuit with a 3-dB bandwidth of 9 MHz for the design of G m - C filters is presented in [17]. The circuit consists of a fixed transconductor cascaded with a variable gain cell (shown in Fig. 3.2). This topology takes advantage of the current-mode signal processing to increase the operational bandwidth. Tunability of the bandwidth is achieved by the variable gain stage. Although G m -C filters offer higher bandwidth compared to the active RC filters, they are still unsuitable choices for ADC-based receivers covering 2-1 Gb/s. Moreover, as was the case with active RC filters, G m -C filters are also unable to provide bandwidth scalability with the data-rate. V i G m Variable Gain Cell i o V o Figure 3.2: Gm-C filter presented in [17] Integration and Dump (I&D) Filters I&D is a well-known scheme for optimum detection in digital communication [14]. The input waveform is integrated for one full period, sampled, and reset before the integration of the next bit commences. While I&D improves performance by averaging the noise and therefore lowering the bit error rate (BER), it introduces the following problems to high-speed systems. One is that the integration must be exactly phasealigned to the input data so that the entire unit interval (UI) is integrated. Another issue is that the integration result is required to be reset immediately before the next integration starts. This, however, can be relaxed by using time-interleaved architectures [31]. For an linear-time invariant (LTI) system with an impulse response of h(t), the input-output relationship can be expressed as: y(t) = x(τ)h(t τ)dτ (3.1) Assuming that h(t) is a rectangular filter of pulse-width equal to UI seconds, we

32 22 3 Anti-Aliasing Filter (AAF) Design can write: y(t) = t t UI x(τ)dτ (3.2) y(t) is sampled at the maximum eye-opening, which happens at the end of each UI integration. The resulting samples can be formulated by the relationship 3.3: y(nui) = n(ui) UI(n 1) x(τ)dτ, n =1, 2,... (3.3) For a specific input x(t), shown in Fig. 3.3(a), the outputs of the rectangular filter and the I&D are presented in Fig. 3.3(b) and Fig. 3.3(c), respectively. Although the two output waveforms are different, their corresponding output samples are the same. This result shows that the I&D is a practical implementation of a rectangular filter [26]. The above analyses show that an I&D scheme can be modeled as an LTI system with a rectangular impulse response of width equal to the duration of the integration. This model, shown in Fig. 3.4, is followed by its corresponding impulse/frequency response in Fig In the frequency domain, I&D filter is a sinc function with nulls at integer multiples of the data-rate (f b = 1/UI) and a 3-dB bandwidth equal to.443f b [26].

33 3.1 Anti-Aliasing Filters 23 1 Voltage (V) UI 2UI 3UI 4UI 5UI 6UI 7UI 8UI Time (ps) (a) Input (x(t)) to both systems (rectangular filter and I&D). 1 Voltage (V) UI 2UI 3UI 4UI 5UI 6UI 7UI 8UI Time (ps) (b) Output of the rectangular filter. 1 Voltage (V) UI 2UI 3UI 4UI 5UI 6UI 7UI 8UI Time (ps) (c) Output of the I&D. Figure 3.3: Comparison between output samples of a rectangular filter and an I&D filter.

34 24 3 Anti-Aliasing Filter (AAF) Design V i (t) h(t) T s = (n)ui V o (n) n = 1, 2,... Figure 3.4: LTI Model of an I&D filter. 1 UI h(t) H(f) UI 2UI 3UI 4UI Time (s) 5UI f b 2f b 3f b 4f b Frequency (Hz) 5f b (a) I&D impulse response. (b) I&D frequency response. Figure 3.5: I&D Response. 3.2 Proposed I&D Scheme Fig. 3.6 presents two examples of the previous works where I&D was utilized as the front-end sampler for serializer/deserializer (SerDes) applications. Both of these architectures take advantage of the I&D to filter the high-frequency noise and improve the signal-to-noise ratio (SNR). However, integrating the entire bit period in these two architectures necessitates a clock recovery unit to accurately align the phase of the input to the integrating clock. In [32], the clock signal and data are sent from the transmitter to the receiver. Although feasible at data-rates as low as 7 Mb/s, this method is not applicable to today s multi-gb/s signaling. The reason is that the skew introduced due to the losses of the channel is large enough to disturb the phase relation between the input and the clock. To resolve this, [33] eliminates the clock wire and recovers the clock from the received signal by a clock recovery unit. The recovered clock drives the I&D which is phase-aligned to the input signal. I&D scheme has also been employed in the design of a decision feedback equalizer (DFE) as presented in [34]. This receiver enjoys the power-saving offered by this scheme as opposed to standard DFE summing amplifiers. The I&D, which is phasealigned to the input, integrates the signal for an entire UI. The anti-aliasing feature

35 3.2 Proposed I&D Scheme 25 of the I&D is an undesired feature in this design since it closes the output eye. In a future design [35], similar authors employed a sample-and-hold (S&H) to avoid the loss introduced by the I&D. As discussed in Chapter 2, our goal is to explore the anti-aliasing feature of the I&D and not hinder it. TX RX clk DLL/PLL clk I&D data I&D TX (a) Receiver using I&D in the front-end [32]. RX FF clk recovery unit clk data I&D I&D (b) Receiver using I&D in the front-end [33]. Figure 3.6: Previous I&D works in the front-end.

36 26 3 Anti-Aliasing Filter (AAF) Design Since we target 2x blind ADC-based receivers, the I&D clock no longer requires to be phase-aligned to the input data. Therefore, the feedback loop from the clock recovery unit to the AFE is eliminated. Furthermore, we take advantage of the bandwidth programmability of the I&D to cover data-rates in the range of 2-1 Gb/s. Fig. 3.7 presents the proposed AFE architecture for 2x blind ADC-based receivers. This filter blindly integrates the incoming signal for.5ui. A 4-way time-interleaved architecture is employed to relax the speed requirements of the reset switches. Each interleaved branch is followed by a 4-b half-rate ADC that quantizes the AAF output samples. These digital samples are further DeMUXed and sent to the 2x blind ADCbased CDR [5]. The ADC clock has a certain phase relationship with respect to the AAF/FFE clock which is discussed in Section f b = 2-1 Gb/s AAF 4-bit f b /2 GS/s ADC 16 for f b <= 5 Gb/s 2x Blind ADC-Based 32 for f b > 5 Gb/s CDR D OUT AAF Ck Gen ADC Ck Gen This Work AFE Figure 3.7: Proposed AFE for a 2x blind ADC-based receiver including AAF. The impulse/frequency responses of an I&D are plotted in Fig This figure shows that the I&D bandwidth linearly scales with the integration duration (T i ). As described in Section 2.2.3, the phase (zero-crossing) of the incoming signal in 2x ADC-based receivers is derived by a linear interpolation between the two consecutive opposite samples. In order to see the effectiveness of the I&D as an AAF, Fig. 3.9 plots the phase error (φ error ) versus the initial integration time (T ini ). φ error is defined as the difference between the interpolated phase and the actual input phase. Fig. 3.9 shows that the I&D scheme reduces this error by about 21 %.

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