RRN7745PL. Datasheet. Automotive Radar. Four Channel 77 GHz Receiver. Revision 1.0,

Transcription

1 Four Channel 77 GHz Receiver Datasheet Revision 1.0, Automotive Radar

2 Edition Published by Infineon Technologies AG Munich, Germany 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Revision History Page or Item Subjects (major changes since previous revision) Revision 1.0, Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, DI-POL, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EconoPACK, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OptiMOS, ORIGA, POWERCODE ; PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS, SmartLEWIS, SOLID FLASH, TEMPFET, thinq!, TRENCHSTOP, TriCore. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update Datasheet 3 Revision 1.0,

4 Table of Contents Table of Contents Table of Contents Overview Block Diagram RRN7745PL Ball Diagram Ball Definitions and Functions General Product Characteristics Absolute Maximum Ratings Functional Range Power Supply Mixer Description Mixer Typical Performance Characteristics DC Offset Compensation Description DC Offset Compensation Typical Performance Characteristics IQ Modulator in LO branch Description IQ Modulator Typical Performance Characteristics Test Signal Generation Description of Test Signal Generation Serial Configuration Interface Timing Logic Levels Address Modes Programming Word Write-Verify Mode Read Mode Read Chip-ID Mode Chip-ID Read Sequence No Operation (NOP) Command RRN7745PL Configuration Register Details bit Registers RRN7745PL Power Detector Description Power Detector Temperature Sensor Description Temperature Sensor Calculation of Temperature Sensor Multiplexer Description Sensor Multiplexer Package Outlines Dimensions Package Datasheet 4 Revision 1.0,

5 Four Channel 77 GHz Receiver RRN7745PL Overview Features 200 GHz SiGe technology Four single ended RF inputs Differential LO input LO modulator DC offset compensation at IF outputs Test signal generator Chip temperature sensor Single supply voltage of 3.3 V Description RRN7745PL is a fully integrated state of the art receiver, intended for the use in automotive radar applications, with an operating frequency range from 76 GHz to 77 GHz manufactured in Infineon's 200 GHz SiGe HBT process. For the compensation of an IF DC-offset a compensation circuit is integrated. The built-in test signal generator can be used for calibration and monitoring purposes. In-circuit monitoring of the chip-performance is facilitated through integrated power sensors and a chip temperature sensor. The LO modulator allows a static adjustment of the amplitude and phase or a modulation of the LO signal. Product Name Product Type Ordering Code Package RRN7745PL 77 GHz Receiver SP PG-WFWLB Datasheet 5 Revision 1.0,

6 Block Diagram RRN7745PL 1 Block Diagram RRN7745PL RF2 IF2N IF2 RX-Module 2 RX-Module 3 RF3 IF3N IF3 RF1 IF1N IF1 TST1 TST4 RX-Module 1 ILO1 ILO4 RX-Module 4 RF4 IF4N IF4 VCC VEE TST1 TST2 TST3 TST4 Power Splitter ILO1 ILO2 ILO3 ILO4 Power Splitter DIGTST Temp. Sensor Digital Modulator LO Modulator ENA SI SO CLK Serial Configuration Interface LON LO ILO2 TST2 TST3 ILO3 TEMP TSTI TSTIN TSTQ TSTQN TST ILO MODI MODIN MODQ MODQN PLO PTST TEMP Multiplexer MUXA MUXB Figure 1 Block Diagram of RRN7745PL Datasheet 6 Revision 1.0,

7 Block Diagram RRN7745PL RFx DC-Offset Compensation IFx IFxN TSTx ILOx Figure 2 Block Diagram of the RX Module LON LO PTST TST PLO ILO TSTI TSTIN TSTQ TSTQN ±45 ±45 MODI MODIN MODQ MODQN Figure 3 Block Diagram of the LO Modulator Datasheet 7 Revision 1.0,

8 Ball Diagram 2 Ball Diagram DIGTST NC NC NC VEE VEE VEE IF4 IF4 IF4N A A VEE DIGTST NC NC VEE VEE VEE IF4 IF4N IF3 B B NC VEE DIGTST NC VEE RF4 VEE RF3 VEE IF4N IF3 IF3N C C NC NC VEE VEE VEE VEE VEE IF3 IF3N VCC D D NC NC VEE IF3N VCC MODQ E E LON VEE VEE VEE VCC VCC MODQ MODQN F F LO VEE VEE VEE VCC VCC MODI MODIN G G NC ENA VEE IF2N VCC MODI H H ENA CLK SI VEE VEE VEE VEE IF2 IF2N VCC J J CLK SI SO MUXB VEE RF1 VEE RF2 VEE IF1N IF2 IF2N K K SI SO MUXB MUXA VEE VEE VEE IF1 IF1N IF2 L L SO MUXB MUXA MUXA VEE VEE VEE IF1 IF1 IF1N M M Figure 4 Ball Diagram ewlb (Top View) Datasheet 8 Revision 1.0,

9 Ball Diagram 2.1 Ball Definitions and Functions Table 1 RF Interfaces 1) Ball No. Name Pin Type Buffer Type Function C6 RF4 AI 50 Ohm RF Input RF4 C8 RF3 AI 50 Ohm RF Input RF3 K8 RF2 AI 50 Ohm RF Input RF2 K6 RF1 AI 50 Ohm RF Input RF1 G3 LO AI 100 Ohm Diff. Non Inverting Differential RF Input LO F3 LON AI 100 Ohm Inverting Differential RF Input LON Diff. 1) The DC potential of inputs RF1 - RF4 and LO/LON have to be floating or connected to VEE. Any other potential might cause a damage of the chip. Table 2 IF Interfaces Ball No. Name Pin Buffer Function Type Type A10, A11, IF4 AO Non Inverting IF Output 4 B10 A12, B11, IF4N AO Inverting IF Output 4 C10 B12, C11, IF3 AO Non Inverting IF Output 3 D10 C12, D11, IF3N AO Inverting IF Output 3 E10 J10, K11, IF2 AO Non Inverting IF Output 2 L12 H10, J11, IF2N AO Inverting IF Output 2 K12 L10, M10, IF1 AO Non Inverting IF Output 1 M11 K10, L11, M12 IF1N AO Inverting IF Output 1 Table 3 Serial Configuration Interface Ball No. Name Pin Type Buffer Type H2, J1 ENA I TTL\ CMOS J2, K1 CLK I TTL\ CMOS Function Serial Configuration Interface Enable Input Serial Configuration Interface Clock Input Datasheet 9 Revision 1.0,

10 Ball Diagram Table 3 Serial Configuration Interface Ball No. Name Pin Type Buffer Type J3, K2, L1 SI I TTL\ CMOS K3, L2, M1 SO O TTL\ CMOS Function Serial Configuration Interface Data Input Serial Configuration Interface Data Output Table 4 Control and Sense Functions Ball No. Name Pin Buffer Function Type Type G11, H12 MODI AI Non Inverting LO IQ-Modulator Input I 1) G12 MODIN AI Inverting LO IQ-Modulator Input I 1) E12, F11 MODQ AI Non Inverting LO IQ-Modulator Input Q 1) F12 MODQN AI Inverting LO IQ-Modulator Input Q 1) L4, M3, M4 MUXA AO Multiplexer Output A 2) Power or temperature sensor output K4, L3, M2 MUXB AO Multiplexer Output B 2) Power sensor reference or temperature sensor output A1, B2, C3 DIGTST I Digital Test Input 3) 1) If the IQ-modulator inputs are not used in the application, the input pins have to be not connected. Connecting the input pins to VEE might cause a damage of the chip. 2) If the multiplexer output is not used in the application the output pins have to be left not connected. 3) If the digital test signal generator is not used in the application, it is recommended to connect the DIGTST pin to VEE. Table 5 Power Supply Ball No. Name Pin Type D12, E11, F9, F10, G9, G10, H11, J12 Buffer Type Function VCC PWR Positive Supply Voltage Datasheet 10 Revision 1.0,

11 Ball Diagram Table 6 Ground Balls Ball No. Name Pin Type A5, A7, A9, B1, B5, B7, B9, C2, C5, C7, C9, D3, E3, H3, K5, K7, K9, L5, L7, L9, M5, M7, M9 D4, D5, D7, D9, F4, F5 1), F8, G4, G5 1), G8, J4, J5, J7, J9 Buffer Type Function VEE PWR Negative Supply Voltage Signal ground VEE PWR Negative Supply Voltage 2) Signal ground 1) Thermo ball; floating; strongly recommended to connect to VEE 2) For heat dissipation; balls have to be connected to a cooling plane connected to VEE to ensure adequate heat dissipation Table 7 Not Connected Ball No. Name Pin Type A2, A3, A4, NC B3, B4, C1, C4, D1, D2, E1, E2, H1 Buffer Type Function Not used Recommended to connect to VEE, other potentials than VEE or floating might cause a damage of the chip If more than one ball is assigned to a dedicated signal, the balls are electrically redundant. The connection of the balls placed on the outer edge of the package plus the connection of the RF-balls enable the fundamental electrical operation of the chip. It is highly recommended to connect all balls assigned to one signal to ensure electrical functionality of the chip and to increase device reliability. All thermo-balls marked with footnote 2) have to be contacted on board in any case to optimize the thermal connectivity of the device to the board. Datasheet 11 Revision 1.0,

12 Ball Diagram Table 8 ESD Protection Ball No. Name ESD protection circuit D12, E11, F9, F10, G9, G10, H11, J12 VCC VCC VEE L10, M10, M11 K10, L11, M12 J10, K11, L12 H10, J11, K12 B12, C11, D10 C12, D11, E10 A10, A11, B10 A12, B11, C10 G11, H11 G12 E12, F11 F12 L4, M3, M4 K4, L3, M2 A1, B2, C3 H2, J1 J2, K1 J3, K2, L1 K3, L2, M1 IF1 IF1N IF2 IF2N IF3 IF3N IF4 IF4N MODI MODIN MODQ MODQN MUXA MUXB DIGTST ENA CLK SI SO VCC I/O VEE to internal circuit power clamp K6 K8 C8 C6 G3 F3 RF1 RF2 RF3 RF4 LO LON VCC RFx / LOx transmission line to internal circuit power clamp VEE Datasheet 12 Revision 1.0,

13 Ball Diagram Table 9 I/O Internal Circuit Pad Name I/O internal circuit L10, M10, M11 K10, L11, M12 J10, K11, L12 H10, J11, K12 B12, C11, D10 C12, D11, E10 A10, A11, B10 A12, B11, C10 IF1 IF1N IF2 IF2N IF3 IF3N IF4 IF4N 200f 450 R 50R to DC -offset compensation VCC IFx/IFxN 100 R VEE L4, M3, M4 K4, L3, M2 MUXA MUXB VCC 170 R 15R MUXA MUXB 80R VEE Datasheet 13 Revision 1.0,

14 Ball Diagram Table 9 I/O Internal Circuit Pad Name I/O internal circuit G11, H11 G12 E12, F11 F12 MODI MODIN MODQ MODQN MODI MODIN MODQ MODQN 50R VEE H2, J1 J2, K1 J3, K2, L1 ENA CLK SI VCC 94k 50k ENA CLK SI 4k 400R VEE Datasheet 14 Revision 1.0,

15 Ball Diagram Table 9 I/O Internal Circuit Pad Name I/O internal circuit K3, L2, M1 SO VCC 15R 80R SO 80R 15R VEE A1, B2, C3 DIGTST VCC 80k 10.6k DIGTST 10k 30k 500R VEE Datasheet 15 Revision 1.0,

16 General Product Characteristics 3 General Product Characteristics 3.1 Absolute Maximum Ratings Table 10 Absolute Maximum Ratings, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply voltage V CC,MR V Digital input voltage V IN -0.3 V CC +0.3 V Analog input I IQ 0 10 ma current IQ modulator Junction T j C temperature Storage T stg C temperature ESD Resistivity V ESD,HBM -1 1 kv HBM 1) V ESD,CDM V CDM 1), all balls V ESD,CDM V CDM 1), corner balls 1) ESD susceptibility, HBM according to AEC Q / JESD 22-A114, CDM according AEC Q Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Attention: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation. Datasheet 16 Revision 1.0,

17 General Product Characteristics 3.2 Functional Range Table 11 Functional Range Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply voltage V cc V Silicon bulk temperature range Blocking level at RF input Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. 3.3 Power Supply C ambient temperature not below -40 C, max. max. limit P Blocker -20 dbm Table 12 Power Supply, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified), typical values are determined at V CC = 3.3 V and = 25 C. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply current I CC ma all mixers on, DC offset compensation max., test-iqmodulator off, multiplexer off Power supply rejection ratio PSRR 16 db DC-offset compensation in reset state Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization Datasheet 17 Revision 1.0,

18 General Product Characteristics The following diagrams show values that are verified by characterization of the RRN7745PL Supply Current V = V CC V = V CC V = V CC I CC (ma) T ( C) Si Figure 5 Supply current versus temperature, Table 12/ Supply Current T = -20 C Si T = 25 C Si T = 125 C Si 290 I CC (ma) V (V) CC Figure 6 Supply current versus supply voltage, Table 12/ Datasheet 18 Revision 1.0,

19 General Product Characteristics 24 PSRR, = 25 C 22 PSRR (db) V CC = V V CC = V V CC = V P (dbm) Blocker Figure 7 Power supply rejection ratio versus blocking level at RF input, = 25 C, Table 12/ PSRR, V CC = 3.3 V PSRR (db) = -10 C = 25 C = 125 C P (dbm) Blocker Figure 8 Power supply rejection ratio versus blocking level at RF input, V CC = 3.3 V, Table 12/ Datasheet 19 Revision 1.0,

20 Mixer 4 Mixer 4.1 Description Mixer The mixer unit of RRN7745PL consists of four independent mixers for receiving RF signals. The LO signal distribution is done by splitting the differential input signal into four signals. Each of these signals is amplified and distributed to a mixer. Each mixer can be enabled or disabled by programming the serial configuration interface (see Chapter 8). The mixer core is based on Gilbert cell mixers. The double-balanced active mixer structure is used for down-conversion of the RF input signal. No external biasing of the RF interfaces is needed, all ports are DC-coupled to ground. Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95, typical values are determined at V CC = 3.3 V and = 25 C (unless otherwise specified). Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition RF frequency range f RF GHz LO frequency range f LO GHz IF frequency range f IF 0 1 MHz LO input power P LO 0 dbm Conversion gain G C db voltage gain; T a =-40 C, load impedance 10 kohm differential Conversion gain variation over frequency Conversion gain variation over temperature Conversion gain balance over frequency and temperature db voltage =25 C, =125 C, load impedance 10 kohm differential G CV,f 1.5 const. chip temperature & const. supply voltage G CV,T 3.5 const. frequency & const. supply voltage G B 2 db between any two const. supply voltage Datasheet 20 Revision 1.0,

21 Mixer Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95, typical values are determined at V CC = 3.3 V and = 25 C (unless otherwise specified). Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Input match RF port S11 RF -15 db provided by MMIC using reference matching structure Input match LO port S11 LO -15 db differential, provided by MMIC using reference matching structure LO input Z LO 100 Ohm differential impedance IF coupling DC IF output Z IF 600 Ohm single ended 1) impedance IF output common V CM V mode voltage LO/RF leakage P RF/LOon -17 dbm with LO input power for reliable RX operation Input 1 db compression point P RF/LOoff -30 dbm with reduced LO input power (RTN7735PL maximally reduced power) P1dB dbm Datasheet 21 Revision 1.0,

22 Mixer Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95, typical values are determined at V CC = 3.3 V and = 25 C (unless otherwise specified). Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Noise floor N 10kHz nv/ Hz Phase drift of mixer & mixer test signal nv/ Hz N 100kHz nv/ Hz nv/ Hz Attention: Test means that the parameter is not subject to production test. It was verified by 10 khz offset, T a =-40 C, DC offset compensation in reset mode, without 10 khz offset, =25 C, =125 C, DC offset, compensation in reset mode, without 100 khz offset T a =-40 C, DC offset compensation in reset 100 khz offset =25 C, =125 C, DC offset compensation in reset mode ΔΦ -4 4 Deg. between any two channels ) IF output operating condition: minimum differential IF output load impedance is 10 kohm, minimum common mode IF output load impedance is 100 kohm Datasheet 22 Revision 1.0,

23 Mixer 4.2 Typical Performance Characteristics 18 Conversion Gain, V CC = V, f = 76.5 GHz G C (db) = -20 C = 25 C = 125 C P (dbm) LO Figure 9 Conversion gain versus LO power, V CC =3.135V, Table 13/ Conversion Gain, V CC = 3.3 V, f = 76.5 GHz G C (db) = -20 C = 25 C = 125 C P (dbm) LO Figure 10 Conversion gain versus LO power, V CC =3.3V, Table 13/ Datasheet 23 Revision 1.0,

24 Mixer 19 Conversion Gain, V CC = V, f = 76.5 GHz G C (db) = -20 C = 25 C = 125 C P (dbm) LO Figure 11 Conversion gain versus LO power, V CC =3.465V, Table 13/ Conversion Gain = -20 C = 25 C = 125 C 17 G C (db) f (MHz) IF Figure 12 Conversion gain versus IF frequency, V CC = V, Table 13/ Datasheet 24 Revision 1.0,

25 Mixer Conversion Gain = -20 C = 25 C = 125 C 17 G C (db) f (MHz) IF Figure 13 Conversion gain versus IF frequency, V CC =3.3V, Table 13/ Conversion Gain = -20 C = 25 C = 125 C 17 G C (db) f (MHz) IF Figure 14 Conversion gain versus IF frequency, V CC = V, Table 13/ Datasheet 25 Revision 1.0,

26 Mixer Conversion Gain Balance Ch. 1 & 2 Ch. 1 & 3 Ch. 1 & 4 Ch. 2 & 3 Ch. 2 & 4 Ch. 3 & 4 G B (db) V (V) CC Figure 15 Conversion gain balance versus supply voltage, =25 C, Table 13/ Conversion Gain Balance Ch. 1 & 2 Ch. 1 & 3 Ch. 1 & 4 Ch. 2 & 3 Ch. 2 & 4 Ch. 3 & 4 G B (db) T ( C) Si Figure 16 Conversion gain balance versus temperature, V CC =3.3V, Table 13/ Datasheet 26 Revision 1.0,

27 Mixer -5 Reflection Coefficient S 11 (db) = -20 C = 25 C = 125 C Frequency (GHz) Figure 17 Input match RF port, V CC =3.3V, Table 13/ Reflection Coefficient S 11 (db) = -20 C = 25 C = 125 C Frequency (GHz) Figure 18 Input match LO port, V CC =3.3V, Table 13/ Datasheet 27 Revision 1.0,

28 Mixer Common Mode Voltage V = CC V = CC V = CC V CM (V) T ( C) Si Figure 19 IF output common mode voltage versus temperature, Table 13/ LO/RF Leakage -35 P LO/RF (dbm) = -20 C = 25 C = 125 C P (dbm) LO Figure 20 LO/RF leakage, V CC =3.3V, Table 13/ Datasheet 28 Revision 1.0,

29 Mixer db Compression Point T = -20 C Si T = 25 C Si T = 125 C Si P1dB (dbm) V (V) CC Figure 21 Input 1 db compression point versus supply voltage, Table 13/ Noise IF, V = 3.3 V CC T = -20 C Si T = 25 C Si T = 125 C Si N 10kHz (nv/ Hz) P (dbm) LO Figure 22 Noise 10 khz versus LO power, Table 13/ Datasheet 29 Revision 1.0,

30 Mixer Noise IF, V = 3.3 V CC T = -20 C Si T = 25 C Si T = 125 C Si N 100kHz (nv/ Hz) P (dbm) LO Figure 23 Noise 100 khz versus LO power, Table 13/ Noise Floor, V CC = 3.3 V N 100kHz (nv/ Hz) = -20 C = 25 C = 125 C P (dbm) Blocker Figure 24 Noise 100 khz versus blocker level, V CC =3.3 V, Table 13/ Datasheet 30 Revision 1.0,

31 DC Offset Compensation 5 DC Offset Compensation 5.1 Description DC Offset Compensation For compensating the DC offset at the IF output a compensation circuit is integrated. It is based on current sources parallel to the IF output, which can be controlled using the serial configuration interface (see Chapter 8.8). Using these current sources an additional offset voltage can be supplied to the IF outputs in typical steps of 333 mv. By adding a DC-voltage with the contrary sign the intrinsic DC offset can be minimized for each channel individually. Table 14 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, unless otherwise noted typical values are determined at V CC = 3.3 V, = 25 C. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Resolution RES Comp 2+1 Bit 2 bit + 1 bit for sign Compensable DC Offset Voltage V Comp V 1 V for nominal collector resistor Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. 5.2 Typical Performance Characteristics DC Offset Compensation V Comp (V) = -20 C = 25 C = 125 C DC Offset Comp. Setting Figure 25 DC offset compensation, V CC =3.3V, Table 14 Datasheet 31 Revision 1.0,

32 IQ Modulator in LO branch 6 IQ Modulator in LO branch 6.1 Description IQ Modulator The LO signal can be modulated using the integrated IQ modulator in the LO branch (see block diagram Chapter 1). The modulation can be controlled by programming the bits DAC_LO_I and DAC_LO_Q using the serial configuration interface (see Chapter 8.8) or by applying an external modulation signal current at the inputs MODI, MODIN, MODQ and MODQN (see Chapter 2). The signals at the inputs MODI / MODIN and MODQ / MODQN must be supplied differentially. For modulation over the external inputs the DAC used for the digital modulation has to be deactivated (bit DAC_LO). In this mode the common-mode current providing the bias point for the IQ modulator has to be supplied externally according to specification (see Table 15). Table 15 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition I and Q resolution RES LOIQ 6 Bit Modulation signal frequency f LOIQ khz LO modulation I LOIQ 7 10 ma pk differential 1)2) signal current LO modulation I LOCM ma DAC off 2) common mode current IQ modulator LO suppression IQ modulator image rejection ratio LOSUP 15 3) f IF -f MOD 1) each branch typ ma to 3.5 ma. 2) Attention: Absolute maximum ratings must not be exceeded (see Chapter 3.1). 3) By applying an appropriate external signal at MODI, MODIN, MODQ and MODQN an optimization of 10 db will be possible. Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. db amplitude at f IF +f MOD divided by amplitude at f IF IRR 15 3) db amplitude at f IF +f MOD divided by amplitude at Datasheet 32 Revision 1.0,

33 IQ Modulator in LO branch Ext. current source switching quad I IQ I 1 I 1 I I IQ-modulator DAC Figure 26 Circuit diagram of an IQ-modulator analog input One of the four input branches of the IQ modulator interface can be seen in Figure 26. The IQ modulator input current I is optionally the external supplied signal current I IQ or the current I 1 provided by the DAC. The external supplied signal current I IQ is the sum of the LO modulation common mode current I LOCM as specified in (see Table 15) and the LO modulation signal current I LOIQ specified in (see Table 15). To achieve an optimization of the IQ modulator LO suppression (6.1.6 in Table 15) as well as the image rejection ratio (6.1.7 in Table 15), the amplitude and the phase of the differential modulation signal current I LOIQ of either input MODI/MODIN or MODQ/MODQN has to be adjusted. The required quantization step for setting the amplitude is 1 db related to the effective amplitude of the differential modulation signal I LOIQ and for phase adjustment 6. Programming of the DAC is done via the serial configuration interface (see Chapter 8.8). The used number format is offset binary. The reset state of the DAC corresponds to inverted maximum in-phase LO signal. 6.2 Typical Performance Characteristics Modulator LO suppression = -20 C = 25 C = 125 C LOSUP (db) f (GHz) LO Figure 27 IQ modulator LO suppression versus LO frequency, V CC =3.3V, Table 15/ Datasheet 33 Revision 1.0,

34 IQ Modulator in LO branch Modulator IRR = -20 C = 25 C = 125 C IRR (db) f (GHz) LO Figure 28 IQ modulator image rejection ratio versus LO frequency, V CC =3.3V, Table 15/ Datasheet 34 Revision 1.0,

35 Test Signal Generation 7 Test Signal Generation 7.1 Description of Test Signal Generation For testing the functionality of the mixers a test signal generator is integrated. The test signal is coupled to the RF branch of the mixer (see Chapter 1). The power of the test signal can be adjusted in seven steps. The test signal generator is activated by enabling the bit DAC_TST in register ENA_MIX and by applying a clock signal to the input DIGTST which is compatible to 3.3 V CMOS logic. A single sideband signal resulting in a 4-point constellation diagram is generated. Table 16 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, typical values are determined at V CC = 3.3 V and = 25 C (unless otherwise specified),. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Fundamental tone test signal level Phase drift of mixer test signal V SSB mv rms at mixer IF output 1) ; setting bits TST_SIG for typical value: 100 B ΔΦ TST -1 1 Deg. between any two channels 2), guaranteed by design Modulator divider DIV M ratio Constellation points Sideband offset f TST 0 1 MHz frequency 1) Seven levels programmable via Serial Configuration Interface (see Table 17). 2) Phase of each test signal at insertion point is constant in a range of E1 over temperature, supply voltage and temperature. Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization The digital input signal on DIGTST is divided by four in a two stage Johnson counter, thus creating two 90 phase shifted signals with 50% duty cycle (see Figure 29). Counter advance occurs on the rising edge of DIGTST. By means of the control bits TST_SIG, the amplitude of the test signal generated by the DAC can be controlled as listed in Table 17. The power up default value of TST_SIG is 000 B, i.e. the modulation feature is deactivated. The bits DAC_Test_I and DAC_Test_Q are used to generate an offset of the I or Q channel respectively to suppress the carrier. Datasheet 35 Revision 1.0,

36 Test Signal Generation DIGTST D CLK Q D CLK Q D CLK Q DAC_Test_I <5:0> TST_SIG <2:0> DAC_Test_Q <5:0> TST_SIG <2:0> A <5:0> B <4:2> add / sub A <5:0> B <4:2> add / sub +/- +/- Q <5:0> Q <5:0> DAC DAC IQ modulator I-channel IQ modulator Q-channel Figure 29 /2 divider /2 Johnson counter Block diagram of the test signal generator add / subtract circuit DACs Table 17 Programmable power levels (see register MUX in Chapter 8) TST_SIG:2 TST_SIG:1 TST_SIG:0 power reduction off db db db db db db db 14 Test signal level V SSB (mv RMS ) f IF (MHz) Figure 30 Example: IF spectrum using the test signal generation, f TST =100kHz, Table 16/ Datasheet 36 Revision 1.0,

37 Serial Configuration Interface 8 Serial Configuration Interface The serial configuration interface is implemented with a 16-bit shift register and 8-bit data registers (Figure 31). The interface is programmed by a 16-bit sequence consisting of a command/address byte and a data byte. All the registers, as well as the chip-id, set by 48 fuses, can be read back by applying a Write-Verify, a Read or a Read Chip-ID command. A reset of the serial configuration interface is enforced at power-on. If the serial configuration interface is not used the default settings remain valid. When writing to the serial configuration interface unused (reserved) bits have to be set to their default value to avoid a possible malfunction of the chip. If the inputs SI, CLK and ENA are left open, the inputs are forced to logical high by an internal pull-up resistor. Register N 8.. Register 1 8 Register 0 8 Address Decoder 8 SI CLK ENA 16 Bit Shift Register 8 SO 16 3 x 16 Chip ID Fuses Figure 31 Serial configuration interface block diagram Datasheet 37 Revision 1.0,

38 Serial Configuration Interface 8.1 Timing The signal ENA acts as chip select or enable and is low-active. The transmission of the serial data provided to the serial data input SI is started by a negative edge on the enable input ENA. Data at the serial input SI is then read at the falling edge of the clock input CLK. The most significant bit (MSB) is read first (Figure 32). The serial output SO is high impedance while ENA remains inactive (logic high). Output data is clocked out at the rising edge of the clock input CLK with the MSB first (Figure 33). The timing parameters specified in Table 18 have to be considered. SI CLK ENA SO Figure 32 Serial configuration interface transmission scheme t ENA(lead) t DATA(su) t DATA(h) t ENA(lag) ENA SI MSB LSB CLK SO t SO(en) t SO(v) t CLK(H) t CLK(L) t SO(dis) Figure 33 Serial configuration interface timing diagram Datasheet 38 Revision 1.0,

39 Serial Configuration Interface Table 18 Timing Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Serial clock high t CLK(H) 10 ns time Serial clock low t CLK(L) 10 ns time Chip select lead t ENA(lead) 20 ns time Chip select lag time t ENA(lag) 20 ns Data setup time t DATA(su) 10 ns Data hold time t DATA(h) 10 ns CLK to SO valid time ENA to SO active time ENA to SO high-z time t SO(v) 20 ns load capacitance 20 pf Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization t SO(en) 100 ns t SO(dis) 100 ns Datasheet 39 Revision 1.0,

40 Serial Configuration Interface 8.2 Logic Levels The digital inputs and the digital output are designed to be compatible with standard CMOS / TTL levels (Table 19). Table 19 Logic levels, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition LOW level input V IN(L) V 1) HIGH level input V IN(H) 2.0 VCC V 1) Input current I IN μa 2) Input hysteresis V H 50 mv guaranteed by design 1) LOW level output V OUT(L) V 3) HIGH level output V OUT(H) VCC-0.66 VCC V 3) Output current I OUT(L) 1.5 ma 3) LOW Output current I OUT(H) -1.5 ma 3) HIGH 1) Valid for ENA, SI, CLK 2) V IN = 0 V to VCC 3) Valid for SO Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. Datasheet 40 Revision 1.0,

41 Serial Configuration Interface 8.3 Address Modes The serial configuration interface is programmed using a 16-bit word consisting of eight command/address bits and eight data bits. The address space of the RRN7745PL and the RTN7735PL is not overlapping allowing the parallel operation of the chip using only one programming interface. For that purpose either the output signals SO needs to be connected separately for each chip or an individual ENA for each chip is used. The latter concept can also be used to operate more than one chip of the same type in parallel Programming Word Description Programming Word CMD w ADDR w DATA rw Field Bits Type Description CMD 15:14 w Command 11 B write-verify 10 B read 01 B NOP 00 B read-out of chip_id ADDR 13:8 w Offset Address DATA 7:0 rw Data Datasheet 41 Revision 1.0,

42 Serial Configuration Interface 8.4 Write-Verify Mode Figure 34 shows the write-verify command. The two most significant bits have to be set to logic 1 to select the write-verify mode, followed by six address bits A0-A5. The programming sequence is completed by eight data bits D0-D7. While the 16-bit sequence consisting of command, address and data is clocked into the interface, 16 bits are shifted out at the serial output SO, depending on the previous command. In the subsequent command cycle the command bits and the address bits A0-A5 of the write command and the data bits D0-D7, which are read back from the addressed register, are shifted out. The command, address and data bits at the input SI following bit D0 may contain any value as well as a further Write-Verify command, Read Chip-ID command, Read command or NOP command. 1 1 A5 A3 A1 D7 D5 D3 D1 A4 A2 A0 D6 D4 D2 D0 X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx A5 A3 A1 D7 D5 D3 D1 1 1 A4 A2 A0 D6 D4 D2 D0 SO Figure 34 Write-Verify Mode 8.5 Read Mode In Figure 35 a read sequence is depicted. The most significant bit has to be set to logic 1 to select the read mode, followed by a logic 0 and six address bits A0-A5. The programming sequence is completed by eight data bits containing any arbitrary value. During a second part of the read sequence the command bits and the address bits of the read command and the 8 data bits of the selected register are provided at the serial output SO. During the second part of the read sequence, the command, address and data bits at the input SI may contain any value as well as a further Read command, Read Chip-ID command, Write-Verify command or NOP command. A5 A3 A1 1 0 A4 A2 A0 X X X X X X X X X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx 1 A5 A3 A1 D7 D5 D3 D1 0 A4 A2 A0 D6 D4 D2 D0 SO Figure 35 Read Mode Datasheet 42 Revision 1.0,

43 Serial Configuration Interface 8.6 Read Chip-ID Mode The chip-id consists of 48 bits, where 45 bits contain information for Infineon-internal use. Three bits are used for a consecutive numbering of different versions of the chip Chip-ID Read Sequence In Figure 36 a chip-id read sequence is depicted. The chip-id is read in three times 16-bit sections. The section to be read is selected by the two address bits A1 and A0. Valid addresses are 20 H to 22 H. If the address 23 H is selected 16-bit at logical 1 are shifted out at the output SO. The read chip-id sequence consists of two parts. First a read chip-id command is sent to the interface. The two most significant bits are logic 0, followed by six address bits and eight databits which may contain any arbitrary value. The most significant bit of the six address bits is logic 1 to select the RRN7745PL. The two least significant bits of the address are the bits A1 and A0, which are used to select the 16-bit sections of the Chip-ID. During a second part of the read sequence the selected 16-bit section of the chip-id is provided at the serial output SO. During the second part of the read chip-id sequence, the command, address and data bits at the input SI may contain any value as well as a further Read Chip-ID command, Read command, Write-Verify command or NOP command. A5 A3 A1 0 0 A4 A2 A0 X X X X X X X X X X X X X X X X X X X X X X X X SI CLK ENA SO Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx D15 D13 D11 D9 D7 D5 D3 D1 D14 D12 D10 D8 D6 D4 D2 D0 Figure 36 Read Chip-ID mode The register addresses and the data content of the three 16-bit sections of the chip-id are shown in the subsequent register description. Chip-ID: Most significant word (bits 47:32) Chip_ID_3 Offset Reset Value Most significant word 22 H XXXX H 15 0 Infineon_internal r Field Bits Type Description Infineon_internal 15:0 r Internal used Datasheet 43 Revision 1.0,

44 Serial Configuration Interface Chip-ID: Second significant word (bits 31:16) Chip_ID_2 Offset Reset Value Second significant word 21 H XXXX H Infineon_internal V1 E V0 Infineon_internal r r r r r Field Bits Type Description Infineon_internal 15:8 r Internal used V1 7 r Version bit 1 Consecutive numbering of different variants from mono-mask. E 6 r Engineering bit V0 5 r Version bit 0 Consecutive numbering of different variants from mono-mask. Infineon_internal 4:0 r Internal used Mapping of mono mask samples to Chip-ID Table 20 Designation of mono mask mono mask V1 E V0 RRN7745PL Chip-ID: Least significant word (bits 15:0) Chip_ID_1 Offset Reset Value Least significant word 20 H XXXX H 15 0 Infineon_internal r Field Bits Type Description Infineon_internal 15:0 r Internal used Datasheet 44 Revision 1.0,

45 Serial Configuration Interface 8.7 No Operation (NOP) Command In Figure 37 a NOP command is depicted. In the subsequent command cycle to a NOP instruction the 16 bits used within the NOP command are shifted out unmodified at the output SO. The address space is chosen so that it is not overlapping between RTN7735PL and RRN7745PL. If an address of the contrary chip is addressed, the chip shifts out the current command sequence at the output SO in the subsequent programming cycle, just as using a NOP command. This allows the operation of the chip set in daisy chain mode. 0 1 A5 A3 A1 D7 D5 D3 D1 A4 A2 A0 D6 D4 D2 D0 X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx A5 A3 A1 D7 D5 D3 D1 0 1 A4 A2 A0 D6 D4 D2 D0 SO Figure 37 NOP Command Datasheet 45 Revision 1.0,

46 Serial Configuration Interface 8.8 RRN7745PL Configuration Register Details The RRN7745PL is configured by ten 8-bit registers with register addresses 20 H to 2B H. The data bits control the DACs of the IQ modulators in both the LO and the test signal path, the selection of the power and temperature sensor outputs, the enabling of the mixers and finally the DC offset compensation of the four IF-channels. Table 21 Registers Overview Register Short Name Register Long Name Offset Address Page Number TST_I DAC IQ-Modulator Test Signal I-Channel 20 H 47 TST_Q DAC IQ-Modulator Test Signal Q-Channel 21 H 47 LO_I DAC IQ-Modulator LO-Signal I-Channel 22 H 48 LO_Q DAC IQ-Modulator LO-Signal Q-Channel 23 H 48 ENA_MIX Enable Mixers and DACs 24 H 49 MUX Multiplexer and Test Signal 25 H 50 Not Implemented 26 H Not Implemented 27 H DC1 DC Offset Compensation Channel 1 28 H 51 DC2 DC Offset Compensation Channel 2 29 H 51 DC3 DC Offset Compensation Channel 3 2A H 52 DC4 DC Offset Compensation Channel 4 2B H 52 The registers with the offset addresses 26 H and 27 H are not implemented. If a write-verify or read command is applied to one of these addresses, the subsequent command cycle provides the corresponding command bits and address bits as well as 8 data bits at logic 1 at the output SO. A write-verify or read command applied to register addresses out of the specified range cause undefined data bits shifted out at the output SO. Datasheet 46 Revision 1.0,

47 Serial Configuration Interface bit Registers RRN7745PL DAC IQ-Modulator Test Signal I-Channel Bits DAC_Test_I control the digital-to-analog converter of the test signal IQ-modulator I-channel. The test signal DAC can be enabled by setting the bit DAC_TST in register ENA_MIX to 1 B. TST_I Offset Reset Value DAC IQ-Modulator Test Signal I-Channel 20 H B DAC_Test_I rw Not_used rw Field Bits Type Description DAC_Test_I 7:2 rw Test Signal DAC I-Channel Reset: B Not_used 1:0 rw Do not change Note: These bits must always be written as 0 B. Reset: 00 B DAC IQ-Modulator Test Signal Q-Channel Bits DAC_Test_Q control the digital-to-analog converter of the test signal IQ-modulator Q-channel. The test signal DAC can be enabled by setting the bit DAC_TST in register ENA_MIX to 1 B. TST_Q Offset Reset Value DAC IQ-Modulator Test Signal Q-Channel 21 H B DAC_Test_Q rw Not_used rw Field Bits Type Description DAC_Test_Q 7:2 rw Test Signal DAC Q-Channel Reset: B Not_used 1:0 rw Do not change Note: These bits must always be written as 0 B. Reset: 00 B Datasheet 47 Revision 1.0,

48 Serial Configuration Interface DAC IQ-Modulator LO-Signal I-Channel Bits DAC_LO_I control the digital-to-analog converter of the LO-signal IQ-modulator I-channel. The DAC can be disabled by setting the bit DAC_LO in register ENA_MIX to 0 B. LO_I Offset Reset Value DAC IQ-Modulator LO-Signal I-Channel 22 H B DAC_LO_I rw Not_used rw Field Bits Type Description DAC_LO_I 7:2 rw LO-Signal DAC I-Channel Reset: B Not_used 1:0 rw Do not change Note: These bits must always be written as 0 B. Reset: 00 B DAC IQ-Modulator LO-Signal Q-Channel Bits DAC_LO_Q control the digital-to-analog converter of the LO-signal IQ-modulator Q-channel. The DAC can be disabled by setting the bit DAC_LO in register ENA_MIX to 0 B. LO_Q Offset Reset Value DAC IQ-Modulator LO-Signal Q-Channel 23 H B DAC_LO_Q rw Not_used rw Field Bits Type Description DAC_LO_Q 7:2 rw LO-Signal DAC Q-Channel Reset: B Not_used 1:0 rw Do not change Note: These bits must always be written as 0 B. Reset: 00 B Datasheet 48 Revision 1.0,

49 Serial Configuration Interface Enable Mixers and DACs Bits RX1, RX2, RX3 and RX4 enable or disable the corresponding RF-channels. Bits DAC_LO and DAC_TST enable or disable the corresponding digital-to-analog converters. ENA_MIX Offset Reset Value Enable Mixers and DACs 24 H B Not_used RX_4 RX_3 RX_2 RX_1 DAC_LO DAC_TST rw rw rw rw rw rw rw Field Bits Type Description Not_used 7:6 rw Do not change Note: These bits must always be written as 1 B. Reset: 11 B RX_4 5 rw Mixer Enable RX4 Reset: 1 B RX_3 4 rw Mixer Enable RX3 Reset: 1 B RX_2 3 rw Mixer Enable RX2 Reset: 1 B RX_1 2 rw Mixer Enable RX1 Reset: 1 B DAC_LO 1 rw DAC Enable Mixer LO Reset: 1 B DAC_TST 0 rw DAC Enable Mixer Test Signal Reset: 0 B Datasheet 49 Revision 1.0,