RTN7735PL. Datasheet. Automotive Radar. 77 GHz Transmitter with Three Outputs and Integrated Down Converter. Rev. 1.0,

Transcription

1 77 GHz Transmitter with Three Outputs and Integrated Down Converter Datasheet Rev. 1.0, Automotive Radar

2 Edition Published by Infineon Technologies AG Munich, Germany 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Revision History Page or Item Subjects (major changes since previous revision) V 1.0, Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, DI-POL, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EconoPACK, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OptiMOS, ORIGA, POWERCODE ; PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS, SmartLEWIS, SOLID FLASH, TEMPFET, thinq!, TRENCHSTOP, TriCore. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of rius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update Datasheet 3 Rev. 1.0,

4 Table of Contents Table of Contents Table of Contents Overview Block Diagram Ball Diagram Ball Definitions and Functions General Product Characteristics Absolute Maximum Ratings Functional Range Power Consumption VCO Description VCO Electrical Characteristics VCO Typical Performance Characteristics Frequency Divider Block Diagram Divider Ratios Down Converter Description Down Converter Electrical Characteristics Down Converter Typical Performance Characteristics Serial Configuration Interface Timing Logic Levels Address Modes Programming Word Write-Verify Mode Read Mode Read Chip-ID Mode Chip-ID Read Sequence No Operation (NOP) Command Configuration Registers RTN7735PL RTN7735PL Configuration Register Details Power Detector Description Power Detector Calculation of Output Power Typical Performance Characteristics Temperature Sensor Description Temperature Sensor Calculation of Temperature Sensor Multiplexer Description Sensor Multiplexer Package Outlines Package Dimensions Datasheet 4 Rev. 1.0,

5 77 GHz Transmitter with Three Outputs and Integrated Down Converter RTN7735PL Overview Features 200 GHz Ge technology Programmable prescaler Three differential, AC-coupled RF outputs Output power reduction mode, digitally programmable Integrated down converter with prescaler Output level detectors Chip temperature sensor ngle supply voltage of 3.3V Description RTN7735PL is a fully integrated state of the art VCO usable in automotive radar applications. It provides three differential outputs for the frequency range from 76 GHz to 77 GHz manufactured in Infineon's 200 GHz Ge HBT process. Due to its integrated power amplifiers in each RF output, no additional active components are needed for building a RF transmission path of an automotive radar sensor in this frequency range. Each of the RF outputs can be used alternatively as LO source for one or two receiver-chips (e.g. RRN7745PL). The integrated prescaler and down converter enables an easy integration of RTN7735PL into frequency controlling circuits, like PLLs. Incircuit monitoring of the chip-performance is facilitated through integrated output level and chip temperature sensors. Product Name Product Type Ordering Code Package RTN7735PL 77 GHz Transmitter SP PG-WFWLB Datasheet 5 Rev. 1.0,

6 Block Diagram 1 Block Diagram PRF3 RF2 RF2N PRF2 PRF1 RF3N RF3 Power Splitter RF1 RF1N Temp. Sensor TEMP TEMP PRF1 PRF2 PRF3 VCC VEE TUNE1F TUNE2C 77 GHz Multiplexer MUXA MUXB ENA SI SO CLK Modulus Control Serial Configuration Interface Divider 1 Q2N Q2 Q1N Q1 TUNEDC 18 GHz Divider 2 Q3 Q3N QDC QDCN Figure 1 Block diagram of RTN7735PL Datasheet 6 Rev. 1.0,

7 Ball Diagram 2 Ball Diagram NC VCC Q1N Q1 VEE VEE MUXB MUXA VCC NC A A NC VCC Q1N Q1 VEE VEE MUXB MUXA VCC NC B B Q2 Q2 VCC NC VEE RF1N RF1 VEE MUXA VCC VCC VCC C C Q2N Q2N VEE VEE VEE VEE VEE VCC VCC VCC D D NC NC VEE VEE VEE VEE VEE VEE VEE VEE E E NC NC VEE RF2N F F Q3N Q3N VEE RF2 G G Q3 Q3 VEE VEE VEE VEE VEE VEE VEE VEE H H QDC QDC VEE VEE VEE VEE VEE ENA ENA ENA J J QDCN QDCN TUNEDC TUNE1F VEE RF3 RF3N VEE SI SI CLK CLK K K NC TUNEDC TUNE2C TUNE1F VEE VEE VCC SO SI NC L L NC TUNEDC TUNE2C TUNE1F VEE VEE VCC SO SI NC M M Figure 2 Ball Diagram ewlb (Top View) Datasheet 7 Rev. 1.0,

8 Ball Diagram 2.1 Ball Definitions and Functions Table 1 RF outputs Ball No. Name Pin Type Buffer Type C7 RF1 AO 100 Ohm Diff. C6 RF1N AO 100 Ohm Diff. G10 RF2 AO 100 Ohm Diff. F10 RF2N AO 100 Ohm Diff. K6 RF3 AO 100 Ohm Diff. K7 RF3N AO 100 Ohm Diff. Function Non Inverting Differential RF Output RF1 Inverting Differential RF Output RF1 Non Inverting Differential RF Output RF2 Inverting Differential RF Output RF2 Non Inverting Differential RF Output RF3 Inverting Differential RF Output RF3 Table 2 Serial Configuration Interface Ball No. Name Pin Type Buffer Type J10, J11, J12 ENA I TTL\ CMOS K11, K12 CLK I TTL\ CMOS K9, K10, L11, M11 SI I TTL\ CMOS L10, M10 SO O TTL\ CMOS Function Serial Configuration Interface Enable Input Serial Configuration Interface Clock Input Serial Configuration Interface Data Input Serial Configuration Interface Data Output Table 3 Control and Sense Functions Ball No. Name Pin Type Buffer Type A4, B4 Q1 AO 100 Ohm Diff. A3, B3 Q1N AO 100 Ohm Diff. Function Frequency Divider Output 1 1) Divider ratio RF signal: 4, 32/36, 64/68 or 128/132; Non inverting differential output Frequency Divider Output 1 1) Divider ratio RF signal: 4, 32/36, 64/68 or 128/132; Inverting differential output C1, C2 Q2 AO Frequency Divider Output 2 1) Divider ratio RF signal: 768, 816, 864, 1536, 1584, , , , , ; Divider ratio down converter: /356352; Non inverting differential output Datasheet 8 Rev. 1.0,

9 Ball Diagram Table 3 Control and Sense Functions (cont d) Ball No. Name Pin Buffer Function Type Type D1, D2 Q2N AO Frequency Divider Output 2 1) Divider ratio RF signal: 768, 816, 864, 1536, 1584, , , , , ; Divider ratio down converter: /356352; Inverting differential output H1, H2 Q3 AO Frequency Divider Output 3 1) Divider ratio down converter: 8 or 56/58; Non inverting differential output G1, G2 Q3N AO Frequency Divider Output 3 1) Divider ratio down converter: 8 or 56/58; Inverting differential output J1, J2 QDC AO Down Converter Output 1) Non inverting differential down converter mixer output K1, K2 QDCN AO Down Converter Output 1) Inverting differential down converter mixer output A10, B10, C9 MUXA AO Multiplexer Output 1) Power or temperature sensor output A9, B9 MUXB AO Multiplexer Output 1) Power sensor reference or temperature sensor output L2, M2, K3 TUNEDC AI Down Converter Tuning Input K4, L4, M4 TUNE1F AI Fine Tuning Input L3, M3 TUNE2C AI Coarse Tuning Input 1) If the output is not used in the application the output pins can be left not connected. Table 4 Power Supply Ball No. Name Pin Type A2, A11, B2, B11, C3, C10, C11, C12, D10, D11, D12, L9, M9 Buffer Type Function VCC PWR Positive Supply Voltage Datasheet 9 Rev. 1.0,

10 Ball Diagram Table 5 Ground Balls Ball No. Name Pin Type A5, A8, B5, B8, C5, C8, E10, E11, E12, H10, H11, H12, K5, K8, L5, L8, M5, M8 D3, D4, D5, D8, D9, E3, E4, E5 1), E8, E9, F3, G3, H3, H4, H5 1), H8, H9, J3, J4, J5 1), J8, J9 Buffer Type Function VEE PWR Negative Supply Voltage gnal ground VEE PWR Negative Supply Voltage 2) gnal ground 1) Thermo ball; floating; highly recommended to connect to VEE 2) For heat dissipation, all balls have to be connected to a cooling plane connected to VEE to ensure adequate heat dissipation Table 6 Not Connected Ball No. Name Pin Type A1, A12, B1, NC B12, C4, E1, E2, F1, F2, L1, L12, M1, M12 Buffer Type Function Not used For physical stability reasons only Do not connect If more than one ball is assigned to a dedicated signal, the balls are electrically redundant. The connection of the balls placed on the outer edge of the package plus the connection of the RF-balls enable the fundamental electrical operation of the chip. It is highly recommended to connect all balls assigned to one signal to ensure electrical functionality of the chip and to increase device reliability. All thermo-balls marked with footnote 2) have to be contacted on board in any case to optimize the thermal connectivity of the device to the board. Datasheet 10 Rev. 1.0,

11 Ball Diagram Table 7 ESD Protection Ball No. Name ESD protection circuit A2, A11, B2, B11,C3, C10, C11, C12, D10, D11, D12, L9, M9 VCC VCC VEE A10, B10, C9 A9, B9 C1, C2 D1, D2 J10, J11, J12 K11, K12 K9, K10, L11, M11 L10, M10 MUXA MUXB Q2 Q2N ENA CLK SI SO VCC I/O VEE to internal circuit power clamp A4, B4 A3, B3 H1, H2 G1, G2 J1, J2 K1, K2 Q1 Q1N Q3 Q3N QDC QDCN VCC Q1/Q1N Q3/Q3N QDC/QDCN to internal circuit power clamp VEE Datasheet 11 Rev. 1.0,

12 Ball Diagram Table 7 ESD Protection Ball No. Name ESD protection circuit K4, L4, M4 L3, M3 L2, M2, K3 TUNE1F TUNE2C TUNEDC VCC TUNE1F TUNE2C TUNEDC to internal circuit power clamp VEE C7 C6 G10 F10 K6 K7 RF1 RF1N RF2 RF2N RF3 RF3N power clamp to internal circuit transmission lines VCC RFx RFxN VEE Table 8 I/O Internal Circuits Ball No. Name I/O internal circuits K4, L4, M4 L3, M3 L2, M2, K3 TUNE1F TUNE2C TUNEDC VCC TUNE1F TUNE2C TUNEDC to internal circuit VEE A4, B4 A3, B3 H1, H2 G1, G2 Q1 Q1N Q3 Q3N 50R 50R VCC Q1, Q3 Q1N, Q3N VEE Datasheet 12 Rev. 1.0,

13 Ball Diagram Table 8 I/O Internal Circuits Ball No. Name I/O internal circuits C1, C2 D1, D2 Q2 Q2N VCC 190 R Q2/Q2N 80R VEE J1, J2 K1, K2 QDC QDCN VCC 50R 50R QDC QDCN VEE J10, J11, J12 K11, K12 K9, K10, L11, M11 ENA CLK SI VCC ENA CLK SI 4k 94k VEE Datasheet 13 Rev. 1.0,

14 Ball Diagram Table 8 I/O Internal Circuits Ball No. Name I/O internal circuits L10, M10 SO VCC 80R 30R SO 80R VEE A10, B10, C9 A9, B9 MUXA MUXB VCC 90R MUXA MUXB VEE Datasheet 14 Rev. 1.0,

15 General Product Characteristics 3 General Product Characteristics 3.1 Absolute Maximum Ratings Table 9 Absolute Maximum Ratings, =-40 C to 125 C; ambient temperature not below -40 C; all voltages with respect to ground (unless otherwise specified). Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply voltage V CC,MR V Digital input voltage V IN,D -0.3 V CC +0.3 V Tuning voltage V tc V coarse Tuning voltage fine V tf V Tuning voltage V t,dc V down converter Junction T j C temperature Storage T stg C temperature ESD Resistivity V ESD,HBM -1 1 kv HBM 1) V ESD,CDM V CDM 1), all balls V ESD,CDM V CDM 1), corner balls 1) ESD susceptibility, HBM according to AEC Q / JESD 22-A114, CDM according AEC Q Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Attention: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation. Datasheet 15 Rev. 1.0,

16 General Product Characteristics 3.2 Functional Range Table 10 Functional Range Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply voltage V CC V licon bulk temperature range Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. 3.3 Power Consumption C ambient temperature not below -40 C, max. max. limit Table 11 Power Consumption, V CC = 3.3 V, = -40 C to 125 C, ambient temperature not below -40 C, positive current flowing into pin (unless otherwise specified), typical values are determined at V CC = 3.3 V and =25 C. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Supply current I CC ma mode 1 see Table 12 I CC2 330 ma mode 2 see Table 12 I CC3 190 ma mode 3 see Table 12 I CC4 680 ma mode 4 see Table 12 I CC5 390 ma mode 5 see Table 12 I CC6 490 ma mode 6 see Table Datasheet 16 Rev. 1.0,

17 General Product Characteristics Table 12 Operational Mode Parameter Number of full Number of LO Q1 Q2 Q3 Down Comment TX outputs outputs 1) Converter Mode off off on on Q3: DIV 56 Mode 2 2) 0 0 on off on on Q1: DIV 32 Q3: DIV 56 Mode 3 3) 0 0 off off off off Mode 4 4) 3 0 on on on on Q1: DIV 32 Q2: DIV 768 Q3: DIV 56 Mode on off off off Q1: DIV 32 Mode off off on on Q3: DIV 56 1) 5 dbm output power 2) Reset Mode 3) Minimum power consumption mode 4) Maximum power consumption mode Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. The following diagrams show values that are verified by characterization of the RTN7735PL. 550 Supply current Mode1 500 I CC1 (ma) T = -10 C T = 25 C T = 65 C T = 125 C V (V) CC Figure 3 Supply current versus supply voltage, Mode 1, f =76.5GHz, Table 11/ Datasheet 17 Rev. 1.0,

18 General Product Characteristics 550 Supply current Mode I CC1 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 4 Supply current versus temperature, Mode 1, f =76.5GHz, Table 11/ Supply current Mode I CC2 (ma) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 5 Supply current versus supply voltage, Mode 2, f =76.5GHz, Table 11/ Datasheet 18 Rev. 1.0,

19 General Product Characteristics 425 Supply current Mode I CC2 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 6 Supply current versus temperature, Mode 2, f =76.5GHz, Table 11/ Supply current Mode I CC3 (ma) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 7 Supply current versus supply voltage, Mode 3, f =76.5GHz, Table 11/ Datasheet 19 Rev. 1.0,

20 General Product Characteristics 275 Supply current Mode I CC3 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 8 Supply current versus temperature, Mode 3, f =76.5GHz, Table 11/ Supply current Mode I CC4 (ma) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 9 Supply current versus supply voltage, Mode 4, f =76.5GHz, Table 11/ Datasheet 20 Rev. 1.0,

21 General Product Characteristics 775 Supply current Mode I CC4 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 10 Supply current versus temperature, Mode 4, f =76.5GHz, Table 11/ Supply current Mode I CC5 (ma) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 11 Supply current versus supply voltage, Mode 5, f =76.5GHz, Table 11/ Datasheet 21 Rev. 1.0,

22 General Product Characteristics 500 Supply current Mode I CC5 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 12 Supply current versus temperature, Mode 5, f =76.5GHz, Table 11/ Supply current Mode I CC6 (ma) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 13 Supply current versus supply voltage, Mode 6, f =76.5GHz, Table 11/ Datasheet 22 Rev. 1.0,

23 General Product Characteristics 600 Supply current Mode I CC6 (ma) V CC = V V CC = 3.3 V V CC = V T C Figure 14 Supply current versus temperature, Mode 6, f =76.5GHz, Table 11/ Datasheet 23 Rev. 1.0,

24 VCO 4 VCO 4.1 Description VCO The oscillator of RTN7735PL is a fully differential voltage controlled oscillator (VCO) with integrated resonator providing three differential outputs at RF1/RF1N, RF2/RF2N and RF3/RF3N. Turning on and off of the RF outputs RF1/RF1N, RF2/RF2N and RF3/RF3N and variation of the output power is possible by programming the serial configuration interface (see Chapter 7). The output power of each channel can be reduced by bits PSELx, influencing the power dissipation of the RTN7735PL only marginally or stepwise by using the bits PAx. In the latter case the power dissipation can also be reduced. If needed two channels can be used for LO distribution. In this case a power reduction of the LO channels is recommended. Setting the bits PAx_DRV to 0 B reduces the current in the power amplifier driver resulting in an additional reduction of power dissipation. To avoid out of band emissions during programming an output power reduction by input signal ENA is possible (see Chapter 7). This feature can be enabled for each RF power amplifier separately. Additionally it can be chosen between a mode with almost constant power dissipation and a mode where the power dissipation is reduced during power reduction by ENA. 4.2 Electrical Characteristics VCO Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified), parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Tunable frequency f GHz range Tuning voltage fine V tf V usable tuning voltage range V required tuning voltage range to achieve the tunable frequency range (4.2.1) Tuning sensitivity fine Tuning frequency range fine Tuning sensitivity ratio (fine tune) S tf MHz/V 1) f tf 1.5 GHz 1) SR tf 2.5:1 1) Datasheet 24 Rev. 1.0,

25 VCO Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified), parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Tuning voltage coarse V tc V usable tuning voltage range V required tuning voltage range to achieve the tunable frequency range (4.2.1) Tuning sensitivity coarse S tc MHz/V 1) Tuning input current I t μa Tuning input C tin 2.5 pf impedance Frequency pushing vs. V cc pu_v backside temperature Frequency pulling vs. output power configuration f pu_p 100 MHz 6 bit power setting of one channel (see Chapter 7.8), defined over onwafer measurements (including frequency variation vs. temperature) Frequency variation f v 50 MHz/ C vs. Temperature Output power P TX dbm differential, using reference matching structure and load with S11 < -10 db P TX_off -25 dbm differential, maximally reduced output power mode, see Chapter Datasheet 25 Rev. 1.0,

26 VCO Table 13 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified), parameters specified in the frequency range from 76 GHz to 77 GHz include a matching structure provided by Infineon using the high frequency laminate Taconic TLE-95. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Achievable output power attenuation range Power step size range 1 Power step size range 2 P Out_R2 16 db via 6 bit power setting, see Chapter 7.8 St Out_R1 1 db attenuation range1: 0-6dB St Out_R2 3 db attenuation range 2: 6-16 db Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization Phase noise N PN10kHz khz N PN100kHz khz N PN1MHz MHz Output power Q1 P DIVQ dbm differential Noise Floor Q1 N DIVQ1L -120 divider ratio Output impedance Z Q1 100 Ohm differential Q1 Common mode output voltage Q1 V CM,Q1 V CC V DC coupled Output voltage low V Q2,low V 2) Q2 Output voltage high Q2 V Q2,high 2.64 V CC V 2) Rise time Q2 t r,q2 150 C load < 30 pf 2) Output current Q2 I Q μa 2) Output voltage Q2 V Q2 200 mv Ohm load 3) 1) A coarse tuning voltage can be found to meet the fine tuning sensitivity and ratio requirements within the frequency range. This coarse tuning voltage exhibits coarse-tune sensitivity within the required limits. 2) CMOS compatible digital output, valid for divider ratios ) Valid for divider ratios 1584 Datasheet 26 Rev. 1.0,

27 VCO 4.3 Typical Performance Characteristics 82 RF Frequency, =25 C f (GHz) Parameter: V tf [0.4:0.4:4.6] (V) V (V) tc Figure 15 RF frequency versus coarse tune voltage, =25 C, Table 13/ RF Frequency, =25 C f (GHz) Parameter: V tc [0.4:0.4:4.6] (V) V (V) tf Figure 16 RF frequency versus fine tune voltage, =25 C, Table 13/ Datasheet 27 Rev. 1.0,

28 VCO Frequency pushing T = -10 C T = 25 C T = 125 C f pu_v (MHz/V) V (V) CC Figure 17 Frequency pushing versus supply voltage, f = 76.5 GHz, Table 13/ RF frequency vs. V cc = -10 C = 25 C = 125 C f (GHz) V (V) CC Figure 18 Frequency versus supply voltage Datasheet 28 Rev. 1.0,

29 VCO Frequency pulling, V CC = 3.3 V T = -10 C T = 25 C T = 65 C T = 125 C f pu_p (MHz) A 14 1E C PA setting (HEX) Figure 19 Frequency pulling vs. output power configuration, Table 13/ Frequency variation, V cc = 3.3 V, V tf =2V f v (MHz/ C) V tc = [0.4:0.4:4.6] (V) T ( C) Figure 20 Frequency variation versus temperature, V CC =3.3V, V tf =2V, Table 13/ Datasheet 29 Rev. 1.0,

30 VCO -15 Frequency variation, V cc = 3.3 V, V tc =2V f v (MHz/ C) V tf = [0.4:0.4:4.6] (V) T ( C) Figure 21 Frequency variation versus temperature, V CC =3.3V, V tc =2V, Table 13/ Output power P TX (dbm) = -10 C = 25 C = 65 C = 125 C V (V) CC Figure 22 Output power versus supply voltage, f = 76.5 GHz, Table 13/ Datasheet 30 Rev. 1.0,

31 VCO 15 Output power P TX (dbm) V CC = V V CC = 3.3 V V CC = V T ( C) Figure 23 Output power versus temperature, f = 76.5 GHz, Table 13/ Power reduction, V cc = V 12 6 Figure 24 P TX (dbm) = -10 C = 25 C = 65 C = 125 C A 14 1E C PA1 setting (HEX) 6 bit output power reduction versus power amplifier register setting, f =76.5GHz, V CC = V, Table 13/ Datasheet 31 Rev. 1.0,

32 VCO 18 Power reduction, V cc = 3.3 V 12 6 P TX (dbm) = -10 C = 25 C = 65 C = 125 C A 14 1E C PA1 setting (HEX) Figure 25 6 bit output power reduction versus power amplifier register setting, f = 76.5 GHz, V CC =3.3V, Table 13/ Power reduction, V cc = V 12 6 P TX (dbm) = -10 C = 25 C = 65 C = 125 C A 14 1E C PA1 setting (HEX) Figure 26 6 bit output power reduction versus power amplifier register setting, f =76.5GHz, V CC = V, Table 13/ Datasheet 32 Rev. 1.0,

33 VCO Phase noise T = -10 C T = 25 C T = 65 C T = 125 C N PN (dbc/hz) df (Hz) Figure 27 Phase noise versus offset frequency, f =76.5GHz, V CC =3.3V, Table 13/ Output power Q1, V cc = 3.3 V -6 P DIVQ1 (dbm) Div 4 Div 32 Div 36 Div 64 Div 68 Div 128 Div T ( C) Figure 28 Output power Q1 versus temperature, f =76.5GHz, V CC =3.3V, Table 13/ Datasheet 33 Rev. 1.0,

34 Frequency Divider 5 Frequency Divider The frequency divider of the RTN7735PL contains divider stages for the 77 GHz VCO, as well as for the 18 GHz down converter. A functional block diagram of the divider architecture is shown in Figure 29. The output Q1 is the high frequency divider output of the 77 GHz VCO with frequencies up to 19 GHz. Q2 is the low frequency output of the 77 GHz VCO and also of the down converter. The output Q3 is used for the lower divider ratios of the down converter. Do not connect the output Q1 or Q3 to signal ground. The different divider ratios and the static modulus control of the divider with divider ratio 28/29 in the down converter chain are programmable via the serial configuration interface (Chapter 7). Divider ratios of 4, 32, 36, 64, 68, 128, 132 at the output Q1/Q1N and 768, 816, 864, 1536, 1584, , , , , at the output Q2/Q2N can be achieved. As stated above Q2 is used as low-frequency output for both the 77 GHz VCO and the down converter. If the bit DIVLF in the register DCON is set to 1, the output Q2 is used for the down converter independent of the settings for the 77 GHz divider chain. 5.1 Block Diagram 8/9 24 Q1 77 GHz SMC 4 16/17 12 SMC SMC 1024 Q2 Modulus Control 32/33 12 Serial Conf. Interface SMC 6 28/29 18 GHz 2 Q3 4 Figure 29 Functional block diagram of the frequency dividers Datasheet 34 Rev. 1.0,

35 Frequency Divider 5.2 Divider Ratios Output Q1 is the high frequency divider output of the 77 GHz VCO with output frequencies up to 19 GHz. The available divider ratios can be found in Table 14 and can be selected by bits Q1 in register FDIV. The divider is used as the first stage for the low frequency divider output Q2. The provided divider ratios for the divider chain Q2 can be seen in Table 14 also. The divider output Q2 can be controlled by bits Q2 from register FDIV as described in Table 15. The output Q2 can also be used as low frequency divider output of the down converter. The bit DIVLF in register DCON enables the down converter divider at output Q2 and overrules the settings of the bits Q2 in register FDIV. Output Q3 is the frequency divider output of the down converter. The divider ratios can be selected by bits Q3 in register DCON and are listed in Table 16. Table 14 Frequency Divider Output Q1 Q1:2 Q1:1 Q1:0 Output Q1 Divider ratio at Q1 Divider ratio for Divider 12/24 divider chain Q off 32/ off 32/ off 64/ off 128/ on 4 32/ on 32/36 32/ on 64/68 64/ on 128/ / Table 15 Frequency Divider Output Q2 Q2:1 Q2:0 Q3:1 Q3:0 DIVLF Output Q2 0 0 X X 0 off 0 1 X X 0 77 GHz divider: divider ratio as selected by bits Q1 1 0 X X 0 77 GHz divider: divider ratio selected by bits Q1 divided by X X 0 reserved X X GHz divider: divider ratio X X GHz divider: divider ratio X X GHz divider: divider ratio X X GHz divider: divider ratio Table 16 Frequency Divider Output Q3 Q3:1 Q3:0 Output Q3 0 0 off 0 1 DIV DIV DIV 58 Datasheet 35 Rev. 1.0,

36 Frequency Divider Example 1: Set divider Q1 to divider ratio 64, divider Q2 to divide the 77 GHz signal by and divider Q3 to divider ratio 8. Program bits Q1 in register FDIV to 101 B (see Table 14 rows Output Q1 and Divider ratio at Q1 ) to activate the divider output Q1 and set the divider ratio 64. The static modulos control bit SMC can be let at the default value 1 B. With this setting also the first divider stages for the divider output Q2 are preselected. Using Table 14, rows Divider ratio for divider chain Q2 and Divider 12/24 a divider ratio of 768 results. Setting bits Q2 in register FDIV to 10 B the divider output Q2 is activated and the additional divider stage by 1024 is chosen resulting in an overall divider ratio of In operation the divider output Q2 can be disabled using bit Q2DIS in register FDIV without affecting the divider ratio settings. The divider output Q3 can be activated and adjusted to divider ratio 8 by changing bits Q3 in Register DCON to 01 B. Example 2: Suppose the same settings for divider output Q1 and Q3 as in Example 1. The divider output Q2 should now by used in conjunction with the 18 GHz oscillator providing a divider ratio of Program bits Q1 and Q3 according to example 1. The divider output Q2 is assigned to the 18 GHz oscillator and turned on by using bit DIVLF in Register DCON. This bit overrules the setting programmed by bits Q2 in register FDIV. The divider ratio at divider output Q2 is depending on bits Q3 in register DCON. Choosing a divider ratio of 8 at divider output Q3 results in a divider ratio of at divider output Q2 (see Table 15). Datasheet 36 Rev. 1.0,

37 Down Converter 6 Down Converter 6.1 Description Down Converter The RTN7735PL allows an easy integration into frequency control circuits like a phase locked loop (PLL) by providing an integrated down converter. The down converter is implemented as a fully differential voltage controlled 18 GHz oscillator (VCO) with integrated resonator, a Gilbert cell based mixer and an additional divider block with divider ratios of 8, 56, 58, and The operational mode of the down converter can be programmed through the serial configuration interface described in Chapter Electrical Characteristics Down Converter Table 17 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Tunable frequency range f DC GHz Tuning voltage V t,dc V usable tuning voltage range V required tuning voltage range to achieve the tunable frequency range constant die Tuning sensitivity S t,dc MHz/V Frequency pushing f pu_v 100 MHz/V vs. V cc backside temperature Tuning input C tin,dc 2.5 pf impedance Tuning input current I t μa Phase noise N PN10kHz khz N PN100kHz khz IF output frequency f IF GHz range IF output power P IF dbm differential IF output Z IF 100 Ohm impedance IF output common mode voltage V IF,CM V CC V Datasheet 37 Rev. 1.0,

38 Down Converter Table 17 Electrical Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Output power divider Q3 Noise floor divider output Q3 Common mode voltage output Q3 Output impedance Q3 P Q dbm differential N Q3-125 divide ratio V Q3,CM V CC V Z Q3 100 Ohm differential Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. 6.3 Typical Performance Characteristics 19.2 Frequency vs. V t, V CC = 3.3 V f (GHz) T = -10 C T = 25 C T = 65 C T = 125 C V (V) t Figure GHz VCO frequency versus tuning voltage, V CC =3.3V, Table 17/ Datasheet 38 Rev. 1.0,

39 Down Converter 19.2 Frequency vs., V cc = 3.3 V f (GHz) V t = [0.5:0.5:4.4] (V) T ( C) Figure GHz VCO frequency over temperature, V CC =3.3V, Table 17/ S t, DC (MHz/V) GHz VCO tuning sensitivity, V = 3.3 V cc T = -10 C T = 25 C T = 65 C T = 125 C V (V) t Figure GHz VCO tuning sensitivity versus tuning voltage, V CC =3.3V, Table 17/ Datasheet 39 Rev. 1.0,

40 Down Converter 0 Frequency pushing f pu_v (MHz/V) = -10 C = 25 C = 125 C V (V) CC Figure GHz VCO frequency pushing versus supply voltage, =25 C, Table 17/ RF frequency vs. V cc = -10 C = 25 C = 125 C f (GHz) V (V) CC Figure 34 Frequency versus supply voltage Datasheet 40 Rev. 1.0,

41 Down Converter -70 Phase noise, f = GHz, V CC = V N PN (dbc/hz) T = -10 C T = 25 C T = 65 C T = 125 C df (Hz) Figure GHz VCO phase noise versus offset frequency, V CC =3.465V, Table 17/ Output power IF, f RF = 76.5 GHz -8-9 P IF (dbm) V cc = V V cc = V V cc = V T ( C) Figure 36 IF output power versus temperature, f =76.5GHz, Table 17/ Datasheet 41 Rev. 1.0,

42 Down Converter -3-5 Output power Q3, V cc =3.3 V Div 8 Div 56 Div 58-7 P Q3 (dbm) T ( C) Figure 37 Output power Q3 versus temperature, V CC =3.3V, Table 17/ Datasheet 42 Rev. 1.0,

43 Serial Configuration Interface 7 Serial Configuration Interface The serial configuration interface is implemented with a 16-bit shift register and 8-bit data registers (Figure 38). The interface is programmed by a 16-bit sequence consisting of a command/address byte and a data byte. All the registers, as well as the chip-id, set by 48 fuses, can be read back by applying a Write-Verify, a Read or a Read Chip-ID command. A reset of the serial configuration interface is enforced at power-on. If the serial configuration interface is not used the default settings remain valid. When writing to the serial configuration interface unused (reserved) bits have to be set to their default value to avoid a possible malfunction of the chip. If the inputs SI, CLK and ENA are left open, the inputs are forced to logical high by an internal pull-up resistor. Register N 8.. Register 1 8 Register 0 8 Address Decoder 8 SI CLK ENA 16 Bit Shift Register 8 SO 16 3 x 16 Chip ID Fuses Figure 38 Serial configuration interface block diagram Datasheet 43 Rev. 1.0,

44 Serial Configuration Interface 7.1 Timing The signal ENA acts as chip select or enable and is low-active. The transmission of the serial data provided to the serial data input SI is started by a negative edge on the enable input ENA. Data at the serial input SI is then read at the falling edge of the clock input CLK. The most significant bit (MSB) is read first (Figure 39). The serial output SO is high impedance while ENA remains inactive (logic high). Output data is clocked out at the rising edge of the clock input CLK with the MSB first (Figure 40). The timing parameters specified in Table 18 have to be considered. SI CLK ENA SO Figure 39 Serial configuration interface transmission scheme t ENA(lead) t DATA(su) t DATA(h) t ENA(lag) ENA SI MSB LSB CLK SO t SO(en) t SO(v) t CLK(H) t CLK(L) t SO(dis) Figure 40 Serial configuration interface timing diagram Datasheet 44 Rev. 1.0,

45 Serial Configuration Interface Table 18 Timing Characteristics, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C. Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition Serial clock high t CLK(H) 10 ns time Serial clock low t CLK(L) 10 ns time Chip select lead t ENA(lead) 20 ns time Chip select lag time t ENA(lag) 20 ns Data setup time t DATA(su) 10 ns Data hold time t DATA(h) 10 ns CLK to SO valid time ENA to SO active time ENA to SO high-z time t SO(v) 20 ns load capacitance 20 pf Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization t SO(en) 100 ns t SO(dis) 100 ns Datasheet 45 Rev. 1.0,

46 Serial Configuration Interface 7.2 Logic Levels The digital inputs and the digital output are designed to be compatible with standard CMOS / TTL levels (Table 19). Table 19 Logic levels, V CC = V to V, = -40 C to 125 C, ambient temperature not below -40 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Number Min. Typ. Max. Test Condition LOW level input V IN(L) V 1) HIGH level input V IN(H) 2.0 VCC V 1) Input current I IN μa 2) Input hysteresis V H 50 mv guaranteed by design 1) LOW level output V OUT(L) V 3) HIGH level output V OUT(H) VCC-0.66 VCC V 3) Output current I OUT(L) 1.5 ma 3) LOW Output current I OUT(H) -1.5 ma 3) HIGH 1) Valid for ENA, SI, CLK 2) V IN = 0 V to VCC 3) Valid for SO Attention: Test means that the parameter is not subject to production test. It was verified by design/characterization. Datasheet 46 Rev. 1.0,

47 Serial Configuration Interface 7.3 Address Modes The serial configuration interface is programmed using a 16-bit word consisting of eight command/address bits and eight data bits. The address space of the RTN7735PL and the RRN7745PL is not overlapping allowing the parallel operation of the chip using only one programming interface. For that purpose either the output signals SO needs to be connected separately for each chip or an individual ENA for each chip is used. The latter concept can also be used to operate more than one chip of the same type in parallel Programming Word Description Programming Word CMD w ADDR w DATA rw Field Bits Type Description CMD 15:14 w Command 11 B write-verify 10 B read 01 B NOP 00 B read-out of chip_id ADDR 13:8 w Offset Address DATA 7:0 rw Data Datasheet 47 Rev. 1.0,

48 Serial Configuration Interface 7.4 Write-Verify Mode Figure 41 shows the write-verify command. The two most significant bits have to be set to logic 1 to select the write-verify mode, followed by six address bits A0-A5. The programming sequence is completed by eight data bits D0-D7. While the 16-bit sequence consisting of command, address and data is clocked into the interface, 16 bits are shifted out at the serial output SO, depending on the previous command. In the subsequent command cycle the command bits and the address bits A0-A5 of the write command and the data bits D0-D7, which are read back from the addressed register, are shifted out. The command, address and data bits at the input SI following bit D0 may contain any value as well as a further Write-Verify command, Read Chip-ID command, Read command or NOP command. 1 1 A5 A3 A1 D7 D5 D3 D1 A4 A2 A0 D6 D4 D2 D0 X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx A5 A3 A1 D7 D5 D3 D1 1 1 A4 A2 A0 D6 D4 D2 D0 SO Figure 41 Write-Verify Mode 7.5 Read Mode In Figure 42 a read sequence is depicted. The most significant bit has to be set to logic 1 to select the read mode, followed by a logic 0 and six address bits A0-A5. The programming sequence is completed by eight data bits containing any arbitrary value. During a second part of the read sequence the command bits and the address bits of the read command and the 8 data bits of the selected register are provided at the serial output SO. During the second part of the read sequence, the command, address and data bits at the input SI may contain any value as well as a further Read command, Read Chip-ID command, Write-Verify command or NOP command. A5 A3 A1 1 0 A4 A2 A0 X X X X X X X X X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx 1 A5 A3 A1 D7 D5 D3 D1 0 A4 A2 A0 D6 D4 D2 D0 SO Figure 42 Read Mode Datasheet 48 Rev. 1.0,

49 Serial Configuration Interface 7.6 Read Chip-ID Mode The chip-id consists of 48 bits, where 45 bits contain information for Infineon-internal use. Three bits are used for a consecutive numbering of different versions of the chip Chip-ID Read Sequence In Figure 43 a chip-id read sequence is depicted. The chip-id is read in three times 16-bit sections. The section to be read is selected by the two address bits A1 and A0. Valid addresses are 0 H to 2 H. If the address 3 H is selected 16-bit at logical 1 are shifted out at the output SO. The read chip-id sequence consists of two parts. First a read chip-id command is sent to the interface. The two most significant bits are logic 0, followed by six address bits and eight data bits which may contain any arbitrary value. The most significant bit A5 of the six address bits is logic 0 to select the RTN7735PL. The two least significant bits of the address are the bits A1 and A0, which are used to select the 16-bit sections of the Chip-ID. During a second part of the read sequence the selected 16-bit section of the chip-id is provided at the serial output SO. During the second part of the read chip-id sequence, the command, address and data bits at the input SI may contain any value as well as a further Read Chip-ID command, Read command, Write-Verify command or NOP command. A5 A3 A1 0 0 A4 A2 A0 X X X X X X X X X X X X X X X X X X X X X X X X SI CLK ENA SO Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx D15 D13 D11 D9 D7 D5 D3 D1 D14 D12 D10 D8 D6 D4 D2 D0 Figure 43 Read Chip-ID mode The register addresses and the data content of the three 16-bit sections of the chip-id are shown in the subsequent register description. Chip-ID: Most significant word (bits 47:32) Chip_ID_3 Offset Reset Value Most significant word 2 H XXXX H 15 0 Infineon_internal r Datasheet 49 Rev. 1.0,

50 Serial Configuration Interface Field Bits Type Description Infineon_internal 15:0 r Internally used Chip-ID: Second significant word (bits 31:16) Chip_ID_2 Offset Reset Value Second significant word 1 H XXXX H Infineon_internal V1 E V0 Infineon_internal r r r r r Field Bits Type Description Infineon_internal 15:8 r Internally used V1 7 r Version bit 1 Consecutive numbering of different variants from mono-mask. E 6 r Engineering bit V0 5 r Version bit 0 Consecutive numbering of different variants from mono-mask. Infineon_internal 4:0 r Internally used Mapping of mono mask samples to Chip-ID Table 20 Designation of mono mask mono mask V1 E V0 RTN7735PL Chip-ID: Least significant word (bits 15:0) Chip_ID_1 Offset Reset Value Least significant word 0 H XXXX H 15 0 Infineon_internal r Field Bits Type Description Infineon_internal 15:0 r Internally used Datasheet 50 Rev. 1.0,

51 Serial Configuration Interface 7.7 No Operation (NOP) Command In Figure 44 a NOP command is depicted. In the subsequent command cycle to a NOP instruction the 16 bits used within the NOP command are shifted out unmodified at the output SO. The address space is chosen so that it is not overlapping between RTN7735PL and RRN7745PL. If an address of the contrary chip is addressed, the chip shifts out the current command sequence at the output SO in the subsequent programming cycle, just as using a NOP command. This allows the operation of the chip set in daisy chain mode. 0 1 A5 A3 A1 D7 D5 D3 D1 A4 A2 A0 D6 D4 D2 D0 X X X X X X X X X X X X X X X X SI CLK ENA Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx Dx A5 A3 A1 D7 D5 D3 D1 0 1 A4 A2 A0 D6 D4 D2 D0 SO Figure 44 NOP Command Datasheet 51 Rev. 1.0,