SPC570S40E1, SPC570S40E3, SPC570S50E1, SPC570S50E3

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1 SP570S40E1, SP570S40E3, SP570S50E1, SP570S50E3 32-bit Power Architecture microcontroller for automotive ASILD applications Datasheet - production data etqfp100 (14 x 14 x 1.0 mm) Features etqfp64 (10 x 10 x 1.0 mm) AE-Q100 qualified High performance e200z0h dual core 32-bit Power Architecture technology PU ore frequency as high as 80 MHz Single issue 4-stage pipeline in-order execution core Variable Length Encoding (VLE) Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Up to 48 KB on-chip general-purpose SRAM Multi-channel direct memory access controller (edma paired in lockstep) with 16 channels omprehensive new generation ASILD safety concept Safety of bus masters (core+int, DMA) by delayed lockstep approach Safety of storage (Flash, SRAM) by mainly E Safety of the data path to storage and periphery by mainly End-to-End ED (E2E ED) lock and power, generation and distribution, supervised by dedicated monitors Fault ollection and ontrol Unit (FU) for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Boot time MBIST and LBIST for latent faults heck of safety mechanisms availability and error reaction path functionality by dedicated mechanisms Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST Further measures on dedicated peripherals (e.g. AD supervisor) Junction temperature sensor 8-region system memory protection unit (SMPU) with process ID support (tasks isolation) Enhanced SW watchdog yclic redundancy check (R) unit Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus lass 3 debug and trace interface ommunication interfaces 2 LINFlexD modules, 3 deserial serial peripheral interface (DSPI) modules, and Up to 2 FlexAN interfaces with 32 message buffers each On-chip AN/UART Bootstrap loader with Boot Assisted Flash (BAF). Physical Interface (PHY) can be UART and AN 2 enhanced 12-bit SAR analog converters 1.5 µs conversion time (12 MHz) 16 physical channels (fully shared between the 2 SARAD units) Supervisor AD concept Programmable ross Triggering Unit (TU) Single 3.3 V or 5 V voltage supply 4 general purpose etimer units (6 channels each) Junction temperature range -40 to 150 (165 grade optional) January 2018 DocID Rev 7 1/75 This is information on a product in full production.

2 ontents SP570S40Ex, SP570S50Ex ontents 1 Introduction Document overview Description Feature overview Block diagram Package pinouts and signal descriptions Package pinouts Pin descriptions Package pads/pins Electrical characteristics Introduction Parameter classification Absolute maximum ratings Electromagnetic compatibility (EM) Electrostatic discharge (ESD) Operating conditions Thermal characteristics Package thermal characteristics Power considerations urrent consumption I/O pad electrical characteristics I/O pad types I/O input D characteristics I/O output D characteristics RESET electrical characteristics Power management electrical characteristics Voltage regulator electrical characteristics PMU monitor specifications Nomenclature /75 DocID Rev 7

3 SP570S40Ex, SP570S50Ex ontents Power up/down sequencing Platform Flash controller electrical characteristics Flash memory electrical characteristics PLL0/PLL1 electrical characteristics External oscillator (XOS) electrical characteristics Internal R oscillator (16 MHz) electrical characteristics AD electrical characteristics Introduction AD electrical characteristics Temperature sensor JTAG interface timings DSPI MOS master mode timing lassic timing Modified timing Package information etqfp64 package information etqfp100 package information Ordering information Revision history DocID Rev 7 3/75 3

4 List of tables SP570S40Ex, SP570S50Ex List of tables Table 1. SP570Sx device feature summary (Family Superset onfiguration)6 Table 2. SP570S40Ex, SP570S50Ex device configuration differences Table 3. SP570Sx series block summary Table 4. etqfp64 and etqfp100 pinout Table 5. Parameter classifications Table 6. Absolute maximum ratings Table 7. Radiated emissions testing specification, Table 8. ESD ratings, Table 9. Device operating conditions Table 10. Thermal characteristics for etqfp Table 11. Thermal characteristics for etqfp Table 12. urrent consumption Table 13. I/O pad specification descriptions Table 14. I/O input D electrical characteristics Table 15. I/O pull-up/pull-down D electrical characteristics Table 16. Weak configuration I/O output characteristics, Table 17. Medium configuration I/O output characteristics, Table 18. Strong configuration I/O output characteristics Table 19. Very Strong configuration I/O output characteristics Table 20. I/O output characteristics for pads 4, 9, 11, 55, Table 21. Reset electrical characteristics Table 22. Voltage regulator electrical characteristics Table 23. Trimmed (PVT) values Table 24. RWS settings Table 25. Flash memory program and erase specifications Table 26. Flash memory Life Specification Table 27. PLL1 electrical characteristics Table 28. PLL0 electrical characteristics Table 29. External Oscillator electrical specifications Table 30. Selectable load capacitance Table 31. Internal R oscillator electrical specifications Table 32. AD input leakage current Table 33. AD pin specification, Table 34. AD conversion characteristics Table 35. Temperature sensor electrical characteristics Table 36. JTAG pin A electrical characteristics Table 37. DSPI MOS master classic timing (full duplex and output only) MTFE = Table 38. DSPI MOS master modified timing (full duplex and output only) MTFE = 160 Table 39. etqfp64 package mechanical data Table 40. etqfp100 package mechanical data Table 41. Document revision history /75 DocID Rev 7

5 SP570S40Ex, SP570S50Ex List of figures List of figures Figure 1. Block diagram Figure 2. etqfp 64-pin configuration Figure 3. etqfp 100-pin configuration Figure 4. I/O input D electrical characteristics definition Figure 5. Start-up reset requirements Figure 6. Noise filtering on reset signal Figure 7. Recommended parasitics on board Figure 8. rystal/resonator onnections Figure 9. Test circuit Figure 10. AD characteristic and error definitions Figure 11. Input equivalent circuit (12- bit SAR) Figure 12. JTAG test clock input timing Figure 13. JTAG test access port timing Figure 14. JTAG boundary scan timing Figure 15. DSPI MOS master mode classic timing, PHA = Figure 16. DSPI MOS master mode classic timing, PHA = Figure 17. DSPI PS strobe (PSS) timing (master mode) Figure 18. DSPI MOS master mode modified timing, PHA = Figure 19. DSPI MOS master mode modified timing, PHA = Figure 20. DSPI PS strobe (PSS) timing (master mode) Figure 21. etqfp64 package outline Figure 22. etqfp100 package outline Figure 23. Ordering information scheme DocID Rev 7 5/75 5

6 Introduction SP570S40Ex, SP570S50Ex 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The SP570Sx is a family of next generation microcontrollers built on the Power Architecture embedded category. The SP570Sx family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of hassis and Safety electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 80 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. SP570Sx device feature summary (Family Superset onfiguration) Feature Description Process Main processor ore 55 nm e200z0h Number of main cores 1 Number of checker cores 1 VLE Yes Main processor frequency 80 MHz (1) Interrupt controllers (including interrupt controller checker) 1 Software watchdog timer 1 System timers 1 AUTOSAR STM 1 PIT with four 32-bit channels DMA (including DMA checker) 1 DMA channels 16 SMPU Yes (8 regions) (2) System SRAM ode flash memory Up to 48 KB Up to 512 KB 6/75 DocID Rev 7

7 SP570S40Ex, SP570S50Ex Introduction Table 1. SP570Sx device feature summary (Family Superset onfiguration) (continued) Feature Description Data flash memory (suitable for EEPROM emulation) UTEST flash memory Boot assist flash (BAF) R 1 32 KB 8 KB 8 KB LINFlexD Up to 2 FlexAN Up to 2 DSPI 3 etimer 4 x 6 channels AD (SAR) 2 (3) TU (ross Triggering Unit) 1 Temperature sensor 1 Self-test control unit (memory and logic BIST) 1 FU 1 MEMU 1 PLL Dual PLL with FM Nexus 3 (4) Sequence processing unit (SPU) 1 External power supplies Junction temperature Packages Device SP570SxxE3 Device SP570SxxE1 5V (5) 3.3 V (5) 40 to grade optional (6) etqfp100 etqfp64 1. Includes user programmable PU core and one safety core. The two e200z0h processors in the lockstep pair run at 80 MHz. The e200z0h is compatible with the Power Architecture embedded specification. 2. SMPU with process ID support extension 3. One AD can be used as supervisor AD 4. Including trace for the crossbar masters (data & instruction trace on core and data trace on edma). 4 MDO pin Nexus trace port. 5. All I/Os can be supplied at 3.3 V or 5 V (mutually exclusive) 6. Refer to technical note "SP570S family - High Temperature "D" Grade (DocID TN1262)" for associated specification limitation. DocID Rev 7 7/75 74

8 Introduction SP570S40Ex, SP570S50Ex Table 2. SP570S40Ex, SP570S50Ex device configuration differences SP570S40 (full option configuration) SP570S50 (full option configuration) Flash 256 KB (1) 512 KB RAM 32 KB (2) 48 KB AN 1 (3) 2 Others aligned to the SP570Sx device feature summary (Family Superset onfiguration) described in Table 1 1. Flash blocks excluded on SP570S40: 128K Block 0 [0x0100_0000 0x0101_FFFF] 128K Block 1 [0x0102_0000 0x0103_FFFF] 2. SRAM area excluded on SP570S40 [0x4000_8000 0x4000_BFFF] 3. FlexAN1 excluded on SP570S40 8/75 DocID Rev 7

9 SP570S40Ex, SP570S50Ex Introduction 1.3 Feature overview On-chip modules within the SP570Sx include the following features: 2 main PUs, single-issue, 32-bit PU core complexes (e200z0h), running in lockstep Power Architecture embedded specification compliance Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Up to 48 KB on-chip general-purpose SRAM Multi-channel direct memory access controller (edma paired in lockstep) 16 channels per edma Interrupt controller (INT) with dedicated interrupt source channels, including software interrupts and 32 priority levels Dual phase-locked loops with stable clock domain for peripherals and frequency modulation domain for computational shell rossbar switch architecture for concurrent access to peripherals, flash memory, or SRAM from multiple bus masters with end-to-end E System integration unit lite (SIUL2) Boot Assist Flash (BAF) supports factory programming using serial bootload through UART Serial Boot Mode Protocol. Physical Interface (PHY) can be UART / LIN AN Enhanced analog-to-digital converter system 2 separate 12-bit SAR analog converters 1.5 µs conversion time (at 12 MHz) 16 physical channels Temperature sensor Range 40 to +150 Sensitivity approximately 5.14 mv/ STU2 Support for Logic BIST and Memory BIST at power on ASIL D 3 deserial serial peripheral interface (DSPI) modules 2 LIN and UART communication interface (LINFlexD) modules LINFlexD_0 (master/slave) LINFlexD_1 (master) Up to 2 FlexAN modules Nexus development interface (NDI) per IEEE-ISTO standard, with partial support for 2010 standard Device and board test support per Joint Test Action Group (JTAG) (IEEE ) On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core logic DocID Rev 7 9/75 74

10 Block diagram SP570S40Ex, SP570S50Ex 2 Block diagram Figure 1 shows the top-level block diagram. Figure 1. Block diagram Nexus3 JTAGM JTAG DI SPU DMAHMUX RU DMAHMUX (lockstep) Nexus 2+ RU Nexus 2+ DMA RU DMA (lockstep) Power P e200z0h INT RU INT (lockstep) Power P e200z0h (lockstep) RU e2eed e2eed e2eed XBI XBAR RAM controller Flash controller PBRIDGE_1 AI1 AI0 PBRIDGE_0 RAM Flash etimer_2 DSPI_2 MU_1 XBAR SMPU XBI SRAM PFLASH INT_0 etimer_3 FU MU_2 SWT STM DMA_0 etimer_0 etimer_1 TU FlexAN_1 LINFlexD_1 MU_3 SARAD_0 SARAD_B FlexAN_0 STU JTAGM PMDIG DSPI_0 DSPI_1 LINFlexD_0 MEMU R M_GM M_RGM M_ME DMA HMUX_0 PIT M_PU SSM PLL_DIG_0 MU_0 SIUL JD IROS_DIG XOS_DIG FLASH_INF WKPU 10/75 DocID Rev 7

11 SP570S40Ex, SP570S50Ex Block diagram Table 3 summarizes the functions of all blocks present in the SP570Sx series of microcontrollers. Please note that the presence and number of blocks vary by device and package. Table 3. SP570Sx series block summary e200z0 PU Block Analog-to-digital converter (AD) ross triggering unit (TU) Deserial serial peripheral interface (DSPI) Enhanced Direct Memory Access (edma) DMAHMUX Flash memory FlexAN (controller area network) PLL0 Frequency-modulated phaselocked loop (PLL1) Interrupt controller (INT) AIPS RAM controller System RAM Flash memory controller Flash memory IROS XOS JTAG Master JTAG Data ommunication Module PASS Sequence Processing Unit LINFlex controller Function Allows single clock instruction execution Multi-channel, 12-bit analog-to-digital converter Enables synchronization of AD conversions with a timer event from the emios or from the PIT Provides a synchronous serial interface for communication with external devices Performs complex data transfers with minimal intervention from a host processor via 16 programmable channels. Allows to route a defined number of DMA peripheral sources to the DMA channels Provides non-volatile storage for program code, constants and variables Supports the standard AN communications protocol Output independent of core clock frequency Generates high-speed system clocks and supports programmable frequency modulation Provides priority-based preemptive scheduling of interrupt requests System bus to peripheral bus interface Acts as an interface between the system bus and the integrated system RAM Supports read/write accesses mapped to the SRAM memory from any master Acts as an interface between the system bus and the Flash memory module Up to 512 KB of programmable, non-volatile Flash memory for code and 32 KB for data ontrols the internal 16 MHz R oscillator system ontrols the on-chip oscillator (XOS) and provides the register interface for the programmable features Provides software the option to write data for driving JTAG Provides the capability to move register data between the IPS and JTAG domains Programs a set of Flash memory access protections, based on user programmable passwords Provides an on-device trigger functions similar to those found on a logic analyzer Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of PU load DocID Rev 7 11/75 74

12 Block diagram SP570S40Ex, SP570S50Ex Table 3. SP570Sx series block summary (continued) lock generation module (M_GM) Mode entry module (M_ME) M_PM Reset generation module (M_RGM) Memory protection unit (MPU) etimer FU RU MEMU XBI STU2 R RegProt Block Temperature sensor Debug ontrol Interface Nexus Port ontroller Nexus Multimaster Trace lient Periodic interrupt timer (PIT) System integration unit (SIUL) System status configuration module (SSM) System timer module (STM) System watchdog timer (SWT) Provides logic and control required for the generation of system and peripheral clocks Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications ontains registers that enable/disable the various voltage monitors entralizes reset sources and manages the device reset sequence of the device Provides hardware access control for all memory references generated in a device Has six 16-bit general purpose counter, where each counter can be used as input capture or output compare function ollects fault event notification from the rest of the system and translates them into internal and/or external system reactions ompares input signals and issues an alarm in the case of a mismatch ollects and reports error events associated with E (Error orrection ode) logic used on SRAM, DMA RAM and Flash memory Verifies the integrity of the attribute information for crossbar transfers and signals the Fault ollection and ontrol Unit (FU) when an error is detected Handles the BIST procedure ontrols the computation of R, off-loading this work from the PU Protects several registers against accidental writing, locking their value till the next reset phase Monitors the device temperature Provides debug features for the MU Monitor a variety of signals including addresses, data, control signals, status signals, etc. Monitors the system bus and provides real-time trace information to debug or development tools Produces periodic interrupts and triggers Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AUTOSAR and operating system tasks Provides protection from runaway code Function 12/75 DocID Rev 7

13 SP570S40Ex, SP570S50Ex Block diagram Table 3. SP570Sx series block summary (continued) Block Wakeup unit (WKPU) rossbar (XBAR) switch Function The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. DocID Rev 7 13/75 74

14 Package pinouts and signal descriptions SP570S40Ex, SP570S50Ex 3 Package pinouts and signal descriptions 3.1 Package pinouts The available etqfp pinouts are provided in the following figures. For pin signal descriptions, please refer to the device reference manual. Figure 2. etqfp 64-pin configuration (a) FU_F0 PA[0] PA[3] PA[4] PA[7] PA[8] PA[9] PA[11] PA[12] PA[13] PA[14 ] VDD_LV VDD_HV_IO PB[3] PB[4] PB[5] PE[15] PE[14] PE[11] VDD_HV_IO PE[8] PE[7] PE[6] PE[5] PE[3] PE[2] VDD_HV_IO PD[15] PD[14] PD[11] PD[10] PD[9] etqfp64 Top view PD[8] PD[7] VDD_HV_IO VDD_LV PORST TESTMODE TK P[15] TDO TMS TDI VDD_HV_OS_PM XTAL EXTAL VDD_LV VDD_HV_IO PB[6] PB[7] VREFH_AD PB[10] PB[11] PB[14] PB[15] P[1] VDD_HV_AD_TSENS P[2] P[3] P[4] P[7] P[8] P[11] FU_F1 Note: Availability of port pin alternate functions depends on product selection. a. All etqfp64 information is indicative and must be confirmed during silicon validation. 14/75 DocID Rev 7

15 SP570S40Ex, SP570S50Ex Package pinouts and signal descriptions Figure 3. etqfp 100-pin configuration FU_F0 PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PA[8] PA[9] PA[10] PA[11] PA[12] PA[13] PA[14] PA[15] PB[0] VDD_LV VDD_HV_IO PB[1] PB[2] PB[3] PB[4] PB[5] PD[8] PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] VDD_LV PD[1] PORST PD[0] TESTMODE TK P[15] TDO TMS TDI P[14] P[13] P[12] VDD_HV_OS_PM XTAL EXTAL VDD_LV VDD_HV_IO PB[6] PB[7] PB[8] VREFH_AD PB[9] PB[10] PB[11] PB[12] PB[13] PB[14] PB[15] P[0] P[1] VDD_HV_AD_TSENS P[2] P[3] P[4] P[5] P[6] P[7] P[8] P[9] P[10] P[11] FU_F1 PE[15] PE[14] PE[13] PE[12] PE[11] VDD_HV_IO PE[10] PE[9] PE[8] PE[7] PE[6] PE[5] PE[4] PE[3] PE[2] VDD_HV_IO PE[1] PE[0] PD[15] PD[14] PD[13] PD[12] PD[11] PD[10] PD[9] etqfp100 Top view Note: Availability of port pin alternate functions depends on product selection. DocID Rev 7 15/75 74

16 Package pinouts and signal descriptions SP570S40Ex, SP570S50Ex 3.2 Pin descriptions The following sections provide signal descriptions and related information about the functionality and configuration of the SP570Sx devices. For information on the signal descriptions and related information about the functionality and configuration of the SP570Sx devices, refer to the "Signal description chapter in the devices reference manual. 3.3 Package pads/pins Note: Table 4 shows the etqfp64 and etqfp100 pinouts. The default reset state for all the pins associated with a programmable alternate function is GPIO. Nexus pins can be enabled via JTAG during the reset phase Table 4. etqfp64 and etqfp100 pinout Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 FU_F0 1 1 IO FU_F0 (1) PA[0] PAD[0] 2 2 IO DSPI 0 - S 0 Ext. INT 0 DSPI 1 - S 1 Timer 0 - ch. 0 PA[1] PAD[1] 3 IO DSPI 1 - S 1 Timer 0 - ch. 0 Nexus EVTI Timer 1 - ch. 0 PA[2] PAD[2] 4 IO DSPI 2 - S 1 DSPI 0 - S 4 Nexus EVTO Timer 1 - ch. 1 PA[3] PAD[3] 3 5 IO DSPI 0 - LK Ext. INT 1 Timer 0 - ch. 0 DSPI 1 - LK PA[4] PAD[4] 4 6 IO DSPI 0 - Serial Data NMI Timer 0 - ch. 1 DSPI 1 - Serial Data PA[5] PAD[5] 7 IO LINFlex 1 - TX Timer 0 - ch. 1 Nexus MK 0 Timer 1 - ch. 2 PA[6] PAD[6] 8 IO LINFlex 1 - RX Timer 0 - ch. 2 Nexus MDO 0 Timer 1 - ch. 3 PA[7] PAD[7] 5 9 IO DSPI 0 - Serial Data Timer 0 - ch. 2 DSPI 1 - Serial Data PA[8] PAD[8] 6 10 IO DSPI 0 - S 1 DSPI 2 - S 0 LINFlex 1 - TX Timer 0 - ch. 1 PA[9] PAD[9] 7 11 IO DSPI 0 - S 2 DSPI 0 - S 7 LINFlex 1 - RX Timer 0 - ch. 2 PA[10] PAD[10] 12 IO DSPI 1 - S 1 Nexus MDO 1 Ext. INT 3 16/75 DocID Rev 7

17 SP570S40Ex, SP570S50Ex Package pinouts and signal descriptions Table 4. etqfp64 and etqfp100 pinout (continued) Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 PA[11] PAD[11] 8 13 IO PA[12] PAD[12] 9 14 IO PA[13] PAD[13] IO PA[14] PAD[14] IO PA[15] PAD[15] 17 IO PB[0] PAD[16] 18 IO DSPI 0 - S 3 LINFlex 0 - RX LINFlex 0 - TX Timer 0 - ch. 4 FlexAN 1 - RX FlexAN 1 - TX DSPI 0 - S 5 FlexAN 1 - RX FlexAN 1 - TX DSPI 1 - S 1 Timer 1 - ch. 0 Timer 1 - ch. 1 VDD_LV PW VDD_HV_IO PWB20 PB[1] PAD[17] 21 IO PB[2] PAD[18] 22 IN/ANA PB[3] PAD[19] IN/ANA PB[4] PAD[20] IN/ANA PB[5] PAD[21] IN/ANA PB[6] PAD[22] IN/ANA Timer 1 - ch. 5 Timer 0 - ch. 4 Timer 0 - ch. 0 Timer 0 - ch. 1 Timer 0 - ch. 2 Timer 0 - ch. 3 DSPI 0 - S 6 Timer 0 - ch. 3 LINFlex 1 - RX LINFlex 1 - TX Ext. INT 3 Nexus MDO 2 Nexus MDO 3 Nexus MSEO 0 AD ch. 15 Ext. INT 3 AD ch. 9 AD ch. 8 AD ch. 7 AD ch. 6 PB[7] PAD[23] IN/ANA Ext. INT 0 AD ch. 5 PB[8] PAD[24] 28 IN/ANA Timer 0 - ch. 5 Timer 1 - ch. 0 Timer 1 - ch. 1 Timer 1 - ch. 2 Timer 1 - ch. 3 Timer 0 - ch. 4 AD ch.14 Ext. INT 4 VREFH_AD REF PB[9] PAD[25] 30 IN/ANA Timer 2 - ch. 3 PB[10] PAD[26] IN/ANA Ext. INT 1 AD ch. 4 PB[11] PAD[27] IN/ANA Ext. INT 2 AD ch. 3 AD ch. 13 Ext. INT 5 Timer 0 - ch. 5 Timer 1 - ch. 4 Ext. INT 4 Timer 0 - ch. 3 Timer 0 - ch. 4 Timer 0 - ch. 5 Timer 1 - ch. 4 Timer 1 - ch. 5 DSPI 1 - S 0 FlexAN 0 - RX DSPI 0 - Serial Data DSPI 1 - Serial Data DSPI 2 - Serial Data Timer 1 - ch. 4 FlexAN 1 - RX LINFlex 0 - RX Timer 1 - ch. 5 Timer 0 - ch. 4 DocID Rev 7 17/75 74

18 Package pinouts and signal descriptions SP570S40Ex, SP570S50Ex Table 4. etqfp64 and etqfp100 pinout (continued) Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 PB[12] PAD[28] 33 IN/ANA PB[13] PAD[29] 34 IN/ANA PB[14] PAD[30] IN/ANA PB[15] PAD[31] IN/ANA P[0] PAD[32] 37 IN/ANA P[1] PAD[33] IN/ANA Timer 2 - ch. 4 Timer 2 - ch. 5 Timer 2 - ch. 0 Timer 2 - ch. 1 Timer 1 - ch. 0 Timer 2 - ch. 2 AD ch. 12 AD ch. 11 AD ch. 2 AD ch. 1 AD ch. 10 AD ch. 0 VDD_HV_AD_TSENS PW P[2] PAD[34] IO P[3] PAD[35] IO P[4] PAD[36] IO P[5] PAD[37] 43 IO P[6] PAD[38] 44 IO P[7] PAD[39] IO P[8] PAD[40] IO P[9] PAD[41] 47 IO P[10] PAD[42] 48 IO P[11] PAD[43] IO Timer 0 - ch. 5 Timer 1 - ch. 0 Timer 1 - ch. 1 DSPI 1 - S 0 DSPI 1 - Serial Data Timer 1 - ch. 2 Timer 1 - ch. 3 DSPI 1 - Serial Data DSPI 1 - LK Timer 1 - ch. 4 DSPI 2 - S 1 DSPI 2 - S 2 DSPI 1 - S 0 Timer 1 - ch. 2 Timer 1 - ch. 3 DSPI 1 - Serial Data DSPI 1 - Serial Data Timer 1 - ch. 4 Timer 1 - ch. 5 DSPI 1 - LK FU_F IO FU_F1 VDD_HV_IO PWB51 VDD_LV PW EXTAL ANA Timer 1 - ch. 5 Timer 3 - ch. 0 Timer 3 - ch. 1 Timer 3 - ch. 2 Timer 3 - ch. 3 Timer 3 - ch. 4 FlexAN 1 - RX FlexAN 1 - TX Ext. INT 1 LINFlex 1 - RX NMI Timer 2 - ch. 1 Timer 2 - ch. 2 Ext. INT 0 Timer 2 - ch. 4 FlexAN 0 - RX FlexAN 0 - TX FlexAN 1 - RX Nexus RDY FlexAN 1 - TX DSPI 2 - S 4 DSPI 2 - S 5 DSPI 2 - S 6 DSPI 2 - S 7 DSPI 0 - Serial Data DSPI 0 - S 0 DSPI 0 - S 1 DSPI 0 - Serial Data DSPI 0 - LK DSPI 0 - S 2 18/75 DocID Rev 7

19 SP570S40Ex, SP570S50Ex Package pinouts and signal descriptions Table 4. etqfp64 and etqfp100 pinout (continued) Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 XTAL ANA VDD_HV_OS_PM PW P[12] PAD[44] 56 IO P[13] PAD[45] 57 IO P[14] PAD[46] 58 IO Timer 0 - ch. 0 Timer 0 - ch. 1 Timer 0 - ch. 2 DSPI 1 - S 3 DSPI 1 - S 4 DSPI 1 - S 5 TDI IO TMS IO TDO IO P[15] PAD[47] IO NMI DSPI 1 - S 2 TK IO TESTMODE IO PD[0] PAD[48] 65 IO DSPI 1 - S 6 Ext. INT 4 Ext. INT 0 PORST IO PD[1] PAD[49] 67 IO Timer 0 - ch. 3 DSPI 1 - S 7 VDD_LV PW PD[2] PAD[50] 69 IO PD[3] PAD[51] 70 IO PD[4] PAD[52] 71 IO Timer 2 - ch. 0 Timer 2 - ch. 1 Timer 2 - ch. 2 DSPI 2 - S 1 DSPI 2 - S 2 DSPI 2 - S 3 VDD_HV_IO 46 PWB51 PD[5] PAD[53] 72 IO PD[6] PAD[54] 73 IO PD[7] PAD[55] IO PD[8] PAD[56] IO DSPI 2 - S 0 DSPI 2 - Serial Data Timer 3 - ch. 0 Timer 3 - ch. 1 Timer 2 - ch. 1 Timer 2 - ch. 2 TU trg_inp TU trg_outp DSPI 1 - S 6 DSPI 1 - S 4 DSPI 1 - S 7 DSPI 1 - S 6 DSPI 1 - S 5 DSPI 1 - S 2 DSPI 1 - S 6 LINFlex 0 - RX LINFlex 0 - TX DSPI 0 - S 3 Timer 2 - ch. 0 Timer 2 - ch. 1 DSPI 0 - S 4 Timer 3 - ch. 0 Timer 3 - ch. 1 Timer 3 - ch. 2 Timer 3 - ch. 3 DSPI 0 - S 5 LINFlex 1 - RX LINFlex 1 - TX DocID Rev 7 19/75 74

20 Package pinouts and signal descriptions SP570S40Ex, SP570S50Ex Table 4. etqfp64 and etqfp100 pinout (continued) Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 PD[9] PAD[57] IO PD[10] PAD[58] IO PD[11] PAD[59] IO PD[12] PAD[60] 79 IO PD[13] PAD[61] 80 IO PD[14] PAD[62] IO PD[15] PAD[63] IO PE[0] PAD[64] 83 IO PE[1] PAD[65] 84 IO FlexAN 0 - RX FlexAN 0 - TX Timer 3 - ch. 2 DSPI 2 - Serial Data DSPI 2 - LK Timer 2 - ch. 3 Timer 2 - ch. 4 Timer 3 - ch. 3 Timer 3 - ch. 4 DSPI 2 - S 1 DSPI 2 - LK Timer 2 - ch. 3 Timer 2 - ch. 4 DSPI 2 - Serial Data DSPI 2 - Serial Data FlexAN 1 - RX FlexAN 1 - TX DSPI 1 - S 7 DSPI 2 - S 2 DSPI 2 - S 3 Timer 3 - ch. 3 Timer 3 - ch. 4 Ext. INT 2 VDD_HV_IO PWB85 PE[2] PAD[66] IO PE[3] PAD[67] IO PE[4] PAD[68] 88 IO PE[5] PAD[69] IO PE[6] PAD[70] IO PE[7] PAD[71] IO PE[8] PAD[72] IO Timer 2 - ch. 5 DSPI 2 - S 0 Nexus MSEO (2) Timer 3 - ch. 5 PE[9] PAD[73] 93 IO PE[10] PAD[74] 94 IO DSPI 2 - S 2 DSPI 0 - S 3 DSPI 0 - S 4 Timer 2 - ch. 4 Nexus MDO 3 (2) LOKOUT Nexus MDO 2 (2) Nexus MDO 1 (2) Nexus DSPI 0 - MDO 0 (2) S 0 Timer 3 - ch. 2 Timer 3 - ch. 3 VDD_HV_IO PW DSPI 0 - S 6 DSPI 0 - S 7 Ext. INT 3 Ext. INT 4 DSPI 0 - S 5 Timer 2 - ch. 2 Timer 2 - ch. 3 Timer 2 - ch. 4 Timer 2 - ch. 5 DSPI 2 - LK DSPI 2 - Serial Data DSPI 2 - Serial Data Timer 3 - ch. 4 Timer 3 - ch. 5 DSPI 2 - S 1 DSPI 2 - S 2 20/75 DocID Rev 7

21 SP570S40Ex, SP570S50Ex Package pinouts and signal descriptions Table 4. etqfp64 and etqfp100 pinout (continued) Pin No. Alternate functions Port pin Pad etqfp64 etqfp100 Type AF1 AF2 AF3 AF4 PE[11] PAD[75] IO PE[12] PAD[76] 97 IO PE[13] PAD[77] 98 IO PE[14] PAD[78] IO PE[15] PAD[79] IO 1. annot be changed 2. an be enabled via JTAG during the reset phase Nexus DSPI 0 - MK0 (2) LK Timer 3 - ch. 4 Timer 3 - ch. 5 Nexus DSPI 0 - EVTO (2) Serial Data Nexus DSPI 0 - EVTI (2) Serial Data DSPI 0 - S 1 DSPI 2 - S 0 DSPI 2 - S 1 DSPI 0 - S 2 DSPI 1 - S 3 DSPI 1 - S 3 DSPI 1 - S 2 DSPI 1 - S 1 DSPI 2 - S 3 DocID Rev 7 21/75 74

22 Electrical characteristics SP570S40Ex, SP570S50Ex 4 Electrical characteristics 4.1 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid applying any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V DD or V SS ). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol for ontroller haracteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol SR for System Requirement is included in the Symbol column. 4.2 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 5 are used and the parameters are tagged accordingly in the tables where appropriate. Table 5. Parameter classifications lassification tag P T D Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. Note: The classification is shown in the column labeled in the parameter tables where appropriate. 22/75 DocID Rev 7

23 SP570S40Ex, SP570S50Ex Electrical characteristics 4.3 Absolute maximum ratings Table 6. Absolute maximum ratings (1) Symbol Parameter onditions Min Value Max Unit ycle T Lifetime power cycles 1000k V SS Ground voltage V DD_LV 1.2 V core supply voltage V V DD_HV_IO I/O supply voltage (2) V V DD_HV_OS_PM Power management unit and OS power supply V V DD_HV_AD_TSENS AD & TSENS power supply V V REFH_AD AD reference supply 0 V DD_HV_AD_TSENS V V IN I/O input voltage range (3) Relative to V SS I INJD I INJA I MAXD I MAXSEG T STG STORAGE T SDR T T SR SR SR SR SR Maximum D injection current for digital pad during overload condition Maximum D injection current for analog pad during overload condition Maximum output D current when driven Relative to V DD_HV_IO 0.3 Per pin, applies to all digital pins Per pin, applies to all analog pins -3 3 ma -3 3 ma Medium -7 8 Strong Very strong Maximum current per power segment (4) ma Storage temperature range and non-operating times Maximum storage time, assembled part programmed in EU Maximum solder temperature (5) Pb-free package V ma No supply; storage temperature in range -40 to years 260 MSL SR Moisture sensitivity level (6) 3 X-rays dose T Maximum cumulated dose allowable Range for x-rays source during inspection: KV; µa 1 Grey DocID Rev 7 23/75 74

24 Electrical characteristics SP570S40Ex, SP570S50Ex 1. Functional operating conditions are given in the D electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability or cause permanent damage to the device. During overload conditions (V IN > V DD_HV_IO or V IN < V SS ), the voltage on pins with respect to ground (V SS ) must not exceed the recommended values. 2. Allowed V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, T J = 150 remaining time at or below 5.5 V. 3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal calculations. 4. A V DD_HV_IO power segment is defined as one or more GPIO pins located between two V DD_HV_IO supply pins. 5. Solder profile per IP/JEDE J-STD-020D 6. Moisture sensitivity per JEDE test method A Electromagnetic compatibility (EM) Table 7 describes the EM characteristics of the device. Table 7. Radiated emissions testing specification (1),(2) oupling structure Test setup Function Functional configuration BISS radiated emissions limit Entire I (G) TEM Reference test 1-S3 18 dbµv Reference test with SSG 1-S3 18 dbµv Memory copy 4-S2 18 dbµv Memory copy with SSG 4-S2 18 dbµv 1. Reference BISS Generic I EM Test Specification, version 1.2, section 9.3, Emission test configuration for Is with PU. 2. The EM parameters are classified as T, validated on testbench. 4.5 Electrostatic discharge (ESD) The following table describes the ESD ratings of the device. Table 8. ESD ratings (1),(2) Parameter onditions Value Unit ESD for Human Body Model (HBM) (3) T All pins 2000 V ESD for field induced harged Device Model (DM) (4) T All pins 500 V 1. All ESD testing is in conformity with DF-AE-Q100 Stress Test Qualification for Automotive Grade Integrated ircuits. 2. Device failure is defined as: If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete D parametric and functional testing at room temperature and hot temperature. Maximum D parametrics variation within 10% of maximum specification 3. This parameter tested in conformity with ANSI/ESD STM Electrostatic Discharge Sensitivity Testing 4. This parameter tested in conformity with ANSI/ESD STM harged Device Model - omponent Level 24/75 DocID Rev 7

25 SP570S40Ex, SP570S50Ex Electrical characteristics 4.6 Operating conditions Table 9. Device operating conditions (1) Symbol Parameter onditions Frequency Value Min Typ Max Unit f SYS SR T J SR P T A (T L to T H ) SR P V DD_HV_IO V DD_HV_OS_PM V DD_HV_AD_TSENS SR SR SR P V REFH_AD SR P V REFH_AD - V DD_HV_AD_TSENS SR D V RAMP SR D V IN SR Device operating frequency (2) -40 < T J < MHz Operating temperature range - junction Operating temperature range - junction Ambient operating temperature range I/O supply voltage P PM and OS supply voltage D SAR AD supply voltage SAR AD reference voltage SAR AD reference differential voltage Slew rate on power supply pins I/O input voltage range Temperature Voltage LVD290/HVD400 enabled LVD290 enabled HVD400 disabled (4),(5) LVD290/HVD400 enabled LVD290 enabled HVD400 disabled (3) LVD400 enabled LVD400 disabled (4),(6) V DD_HV_AD_TSENS V 25 mv 0.5 V/µs V V V V DocID Rev 7 25/75 74

26 Electrical characteristics SP570S40Ex, SP570S50Ex Table 9. Device operating conditions (1) (continued) Symbol Parameter onditions Injection current Value Min Typ Max Unit I I SR T D injection current (per pin) (7),(8),(9) Digital pins and analog pins -3 3 ma I MAXSEG SR D Maximum current per power ma segment (10) 1. The ranges in this table are design targets and actual data may vary in the given range. 2. Maximum operating frequency is applicable to the computational cores and platform for the device. See the locking chapter in the SP570Sx Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device. 3. Refer to technical note "SP570S family - High Temperature "D" Grade (DocID TN1262)" for associated specific limitation. 4. Maximum voltage is not permitted for entire product life. See Absolute maximum ratings. 5. Reduced output/input capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics. 6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the reset sequence, and the LVD/HVD are active until that point. 7. Full device lifetime without performance degradation 8. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Table 6: Absolute maximum ratings for maximum input current for reliability requirements. 9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above the supply rail, current will be injected through the clamp diode to the supply rail. For external R network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more information, see the device characterization report. 10. A V DD_HV_IO power segment is defined as one or more GPIO pins located between two V DD_HV_IO supply pins. 4.7 Thermal characteristics Package thermal characteristics Table 10. Thermal characteristics for etqfp64 Symbol Parameter onditions Value Unit R θja D Junction to ambient, natural convection (1) Four layer board - 2s2p board 32.3 /W R θjma D Junction to ambient in forced 200 ft/min (1 m/s) (1) Four layer board - 2s2p board 26.5 /W R θjb D Junction to board (2) 12.1 /W R θjtop D Junction to top case (3) 19.0 /W R θjbotttom D Junction to bottom case thermal resistance (4) 1.9 /W Ψ JT D Junction to package top, natural convection (5) 0.6 /W 1. Per JEDE JESD51-6 with the board (JESD51-7) horizontal. 2. Thermal resistance between the die and the printed circuit board per JEDE JESD51-8. Board temperature is measured on the top surface of the board near the package. 26/75 DocID Rev 7

27 SP570S40Ex, SP570S50Ex Electrical characteristics 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPE-883 Method ). 4. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance. 5. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDE JESD51-2. Table 11. Thermal characteristics for etqfp100 (1) Symbol Parameter onditions Value Unit R θja D Junction-to-ambient, natural convection (2) Four layer board 2s2p 30.7 /W R θjma D Junction-to-moving-air, ambient (2) At 200 ft./min., four layer board 2s2p 24.3 /W R θjb D Junction-to-board (3) Ring cold plate 11.3 /W R θjtop D Junction-to-case top (4) old plate 16.0 /W R θjbotttom D Junction-to-case bottom (5) old plate 1.5 /W Ψ JT D Junction-to-package top (6) Natural convection 0.5 /W 1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to change per final device design and characterization. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDE JESD51-6 with the board (JESD51-7) horizontal 3. Thermal resistance between the die and the printed circuit board per JEDE JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPE-883 Method ). 5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDE JESD Power considerations An estimation of the chip junction temperature, T J can be obtained from the equation: Equation 1: T J = T A + (R θja * P D ) where: T A = ambient temperature for the package ( ) R θja = junction-to-ambient thermal resistance ( /W) P D = power dissipation in the package (W) The thermal resistance values used are based on the JEDE JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has DocID Rev 7 27/75 74

28 Electrical characteristics SP570S40Ex, SP570S50Ex two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: onstruction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components onnect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: One oz. (35 micron nominal thickness) internal planes omponents are well separated Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: Equation 2: T J = T B + (R qjb * P D ) where: T B = board temperature for the package perimeter ( ) R qjb = junction-to-board thermal resistance ( /W) per JESD51-8 P D = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: Equation 3: R qja = R qj + R qa where: R qja = junction-to-ambient thermal resistance ( /W) R qj = junction-to-case thermal resistance ( /W) R qa = case to ambient thermal resistance ( /W) R qj is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R qa. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the 28/75 DocID Rev 7

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