Revision History Rev. No. History Issue Date Remark 0.0 Initial issue -0 September, Add BOM September, Pcb Version update -0 April, 00 0

Transcription

1 A dbm module specification (-06) Important Notice: AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer.

2 Revision History Rev. No. History Issue Date Remark 0.0 Initial issue -0 September, Add BOM September, Pcb Version update -0 April, Pcb Version update -0 June, 00 Change some components from 060 size to 00 size 0. Pcb Version update -0 July, 00 Change A00 footpriont 0. Change English Company Name Nov. 0, 00

3 Table of Contents. General Description.... Electrical specification.... Interface.... PA & LNA control state.... Application circuit Reference Layout Timing contril for passing CE/FCC Bill of Material... 8

4 . General Description The module is designed for.ghz ISM band with dbm output power wireless applications using AMICCOM s A FSK/GFSK transceiver and A00 RF Front End IC. This module features a fully programmable frequency synthesizer by SPI. The data rate is Mbps and Mbps.. Electrical specification Item Specification Remark Supply voltage Current consumption.v+/-0.(v) mode (Sleep current includes power consumption of mode Mode power = dbm mode typical Frequency MHz ISM band Transmit output power Maximum Power Setting * typical Rx sensitivity Modulation Interface -9 dbm M mode, Dev = 0 KHz -88 dbm M mode, Dev = 0 KHz FSK and GFSK 0 pin.mm header BER E-, FSK PCB Dimension 9(L) x 9(W) x 0.8(H) mm without antenna Operating temperature 0 ~ 0 Annotation:. In direct mode operation, customers can use timing control as page and set the Pout = dbm. It still can pass CE/FCC regulation. In FIFO mode operation, customers can only set the Pout = dbm to pass CE/FCC.

5 . Interface Pin No. Pin name Comment Note SPI_CS SPI chip select SPI_CLK SPI clock SPI_RXD SPI data input SPI_TXD SPI data output RX_CLK RX data sampling clock output 6 RX_SYN RX sync signal output CD_TXEN 8 TRXD 9 TXD TX data input TX mode: Modulation enable Rx mode: Carrier detector Input: TX data input Output: RX data output 0 F_CLK Clock for FIFO data RESETN Chip reset MS0 Transceiver operation mode selection input MS Transceiver operation mode selection input BB_CLK Clock output VIN RF module supply voltage input 6 FP_RDY 8 Multi-function pin of FIFO packet R/W complete or ready signal 9 TXSW RF front end PA/LNA select 0 RXSW RF front end PA/LNA select. PA & LNA control state Control function RX ON TX ON TRX OFF Inhibit TXSW 0 0 RXSW 0 0

6 . Application circuit OUT IN VIN TP TEST POINT C U BF0 C6 8.pF C 00n C 0.pF OUT VIN TRX IN EN VDD_PA L 0 R 0 R C 8.pF HGM C 00n U LDO/SOT- VIN ANT 6 HGM VDD_PA RXSW RXSW TXSW TXSW A00 6 C VDD. C 0u BG VDD_A 8 BG RFO RFI R 6.8K U 0 9 C 00pF RFO RFI C9 C 0.uF VIN L 0 C8 u C C 00n 00n L.8nH C LNA_OUT PA_IN C 00n C0 C 0 VDD. VDD. LNA_OUT PA_IN C C8 0 pf C0 n 6 8 C9 0p C9 0p BP_LI M BP_LI M BP_BPF VDD_A RFI RFO C0 0p R 9K VDD_VCO BP_VCO RSSI VT 9 C n BP_DS CPO 0 0 BP_LPF VDD_PLL VDD. C6 00n SPI_CS C 00n Y 8M CL=pF 9 SPI_CS XI SPI_CLK 8 SPI_CLK XS C 0p SPI_TXD SPI_TXD FP_RDY SPI_RXD 6 A C 6p R SPI_RXD BB_CLK 0(x) VDD. MS FP_RDY VDD_D MS 6 C 00n RX_CLK RX_SYN CD_TXEN TRXD TXD F_CLK RESETN MS0 U BB_CLK RX_CLK RX_SYN CD_TXEN TRXD TXD F_CLK RESETN MS0 SPI_CS SPI_CLK SPI_RXD SPI_TXD RX_CLK RX_SYN CD_TXEN TRXD TXD F_CLK RESETN MS0 MS BB_CLK VIN FP_RDY TXSW RXSW J RF CON J RF CON J CON

7 6. Reference Layout 6

8 . Timing Control for passing CE/FCC: () For FIFO mode operation: If customers use FIFO mode, the max. output power of should be set to dbm in order to pass CE/FCC. () For direct mode operation: For passing CE/FCC regulation, customers can use the timing control below and set the output power to dbm.

9 8. Bill of Material Item Component Description Size Value Tol. Part Number Remark C C0G ceramic capacitor 00 0.pF 0.pF GRMCHR0B Murata C8 C0G ceramic capacitor 00 pf 0.pF GRMCHRC Murata C6 C NPO ceramic capacitor 00 8.pF 0.pF GRMCH8RD Murata C C0G ceramic capacitor 00 00pF % GRMCH0J Murata C XR ceramic capacitor 00 00nF % GRMRC0K Murata 6 L Chip inductor 00.8nH 0.nH LQGHSN8S0 Murata L L R C C Chip resistor % 8 R Chip resistor k % 9 R Chip resistor 060 9K % 0 C C0 XR ceramic capacitor 060 nf 0% GRM88CH0J Murata C8 YV ceramic capacitor 060 uf 0% GRM88RA0K Murata C0 NPO ceramic capacitor 060 0pF % 060N00J00L Walsin C NPO ceramic capacitor 060 0pF % GRM88CH00J Murata C NPO ceramic capacitor 060 6pF % GRM88CH60J Murata C9 NPO ceramic capacitor 060 0pF % GRM88CHJ Murata 6 C9 XR ceramic capacitor 060 0pF 0% GRM88CHJ Murata C C C C C6 C C C YV ceramic capacitor nF 0% GRM88RE0K Murata 8 C YV ceramic capacitor 06 0uF 0% GRMCRA06K Murata 0 U.V 00mA LDO SOT-- AP60L-PA AP60L-PA Anwell * 9 U.G Transceiver QFNL A AMICCOM A AMICCOM U.G RF Front End IC QFN6 A00 AMICCOM A00 AMICCOM U Multilayer chip band pass filter BPF BF0-BRCAC ACX CROP. Y Crystal DIP +/- 8MHz,CL=pF type,9s 0ppm SIWARD, YOKETAN CROP. * Note:. About the spec. of X tal, please see AN_A_0_crystal_circuit_v..pdf for detail.. The rising time of LDO input voltage(.v) should be smaller than 0msec for AP60L-PA application.. C, C9, C0, C,, C, R, R is. In FIFO mode operation, the max. Pout should be set to dbm to pass CE/FCC. Therefore, customers should change C8,C to 0 ohm, L to ohm. 8