Reconfigurable Equalization for 10-Gb/sec Serial Data Links

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1 Reconfigurable Equalization for 10-Gb/sec Serial Data Links in a 0.18-µm CMOS Technology A Dissertation Presented to The Academic Faculty by Franklin Bien In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Electrical and Computer Engineering Georgia Institute of Technology December 2006 Copyright 2006 by Franklin Bien

2 Reconfigurable Equalization for 10-Gb/sec Serial Data Links in a 0.18-µm CMOS Technology Approved by: Dr. Joy Laskar, Advisor School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Kevin Kornegay School of Electrical & Computer Engineering Georgia Institute of Technology Dr. Jianmin Qu School of Mechanical Engineering Georgia Institute of Technology Dr. Emmanouil. M. Tentzeris School of Electrical & Computer Engineering Georgia Institute of Technology Dr. Nikil Jayant School of Electrical & Computer Engineering Georgia Institute of Technology Date Approved: October 31, 2006

3 ACKNOWLEDGEMENTS First, I would like to acknowledge the enthusiastic supervision of my research advisor, Professor Joy Laskar. He kept me giving a research motivation in this research area. Without his guidance and support, this research would not be completed. I am also grateful to my committee members, Professor Emmanouil M. Tentzeris, Professor Kevin Kornegay and Professor Nikil Jayant for their time in reviewing my thesis. I would like to specially thank Dr. Edward Gebara for his helpful comments, deep discussion through the research work. I also would like to thank Dr. Changho Lee, Dr. Kyutae Lim, Dr. Chris Scholtz and Dr. Stephan Pinel for their technical discussion and guidance for the research directions. I am indebted my colleague members in Microwave Application Group for making good environment as a team supporting each other. I owe special thanks to the mixed signal team members for their numerous technical discussions in circuit and system design. Finally, I must acknowledge my parents, Dr. Zeungnam Zenn Bien, and Songsook Chyung for their constant love and support throughout my life. I have to acknowledge my beloved wife, Jennifer Jiyun Bien for her endless support during the research work. She has been the source of encouragement in my life. Without her help and love, this work would not be completed. ii

4 TABLE OF CONTENTS ACKNOWLEDGEMENTS...II LIST OF TABLES...V LIST OF FIGURES...VI LIST OF SYMBOLS AND ABBREVIATIONS...X SUMMARY...XI CHAPTER I....1 CHAPTER II BAND-LIMITED CHANNEL FIBER OPTICAL LINK BACKPLANE MULTI-GB/SEC DATA INTERFACE EQUALIZER TOPOLOGY STUDY LINEAR EQUALIZER NONLINEAR EQUALIZERS BODE EQUALIZER TRANSMITTER AND RECEIVER SIDE EQUALIZER BAND-LIMITED CHANNEL COMPENSATION FEED-FORWARD EQUALIZER (FFE) SETTABLE EQUALIZER WITH PASSIVE DELAY LINE...34 CHAPTER III RECONFIGURABLE EQUALIZER SYSTEM OVERVIEW SETTABLE EQUALIZER WITH ACTIVE DELAY LINE...47 iii

5 3.3 RECONFIGURABLE EQUALIZER IMPLEMENTATION WIDE TUNING RANGE ACTIVE DELAY LINE VARIABLE TAP GAIN AMPLIFIER RECONFIGURABLE EQUALIZER MEASUREMENT RESULTS...73 CHAPTER IV...83 CHAPTER V...95 REFERENCES PUBLICATIONS VITA iv

6 LIST OF TABLES TABLE 3.1. SYSTEM SPECIFICATIONS FOR RECONFIGURABLE EQUALIZER. 55 v

7 LIST OF FIGURES FIG BANDWIDTH GROWTH TIMELINE....1 FIG (A) SATELLITE BASED DIGITAL MULTIMEDIA BROADCASTING HANDHELDS THAT REQUIRES BROADER BANDWIDTH CAPABILITIES OF THE COPPER-BASED PCBS INSIDE, (B) INCREASING DEMAND ON STREAMING MULTIMEDIA CONTENTS OVER THE INTERNET PUSHING THE OVERALL DATA THROUGHPUT HIGHER IN THE NETWORK...2 FIG CONCEPTUAL ILLUSTRATION OF EQUALIZATION (A) CHANNEL RESPONSE, (B) EQUALIZER RESPONSE, AND (C) EQUALIZED RESPONSE IN FREQUENCY DOMAIN...4 FIG IMPULSE RESPONSE OF AN UN-EQUALIZED AND EQUALIZED CHANNEL....4 FIG FUNCTIONAL BLOCK DIAGRAM OF FIR-BASED LINEAR EQUALIZER....5 FIG (A) BACKPLANE CHANNEL CONFIGURATION INCLUDING 8-IN AND 20-IN FR-4 TRACE LENGTH AND (B) THE CORRESPONDING CHANNEL FREQUENCY RESPONSE...7 FIG IMPULSE RESPONSE OF (A) 8-, 20-IN BACKPLANE CHANNELS AND (B) 500-M MMF FIG OPTICAL LINK SYSTEM SIMULATION (A) SCHEMATIC, (B) CHANNEL RESPONSE, AND (C) EYE DIAGRAM AFTER 25-KM SMF WITH 10-GB/SEC NRZ SIGNAL INPUT...14 FIG FORWARD TRANSMISSION FR-4 BACKPLANE TRACES. (A) SCHEMATIC OF THE SYSTEM CONFIGURATION, AND (B) EYE-DIAGRAM AT THE RECEIVER INPUT OF A 10- GB/SEC NRZ SIGNAL AFTER 20-IN BACKPLANE TRACE...17 FIG FORWARD TRANSMISSION FREQUENCY RESPONSE OF A 8-, 20-IN FR4 BACKPLANE TRACES FIG FORWARD TRANSMISSION FREQUENCY RESPONSE OF A 100- AND 500-M MMF...19 FIG IMPULSE RESPONSE OF A COPPER-BASED CHANNEL WITH DISPERSION...21 FIG LINEAR FIR EQUALIZER FIG ADAPTIVE EQUALIZATION (A) USING TRAINING SEQUENCE AND (B) USING THE DECISION SIGNAL AT THE RECEIVER AS THE DESIRED SIGNAL...24 FIG BLOCK DIAGRAM OF THE CONVENTIONAL DFE FIG (A) BLOCK DIAGRAM FOR THE SIMPLE CABLE EQUALIZER AND (B) CORRESPONDING FREQUENCY RESPONSE INDICATING POLE LOCATIONS FIG EQUALIZATION AT THE TRANSMITTER SIDE, RECEIVER SIDE AND BOTH SIDES...30 FIG THE FFE CONFIGURATION WITH PASSIVE LC LADDER DELAY LINE APPROACHES...33 FIG PASSIVE DELAY LINE PERFORMANCE SHOW GOOD AGREEMENT BETWEEN (A) SIMULATION AND (B) MEASURED PERFORMANCE FOR THE TARGETED FIXED-TS/3 (=33PS) TAP SPACING...36 vi

8 FIG MEASURED PERFORMANCE OF THE FFE WITH PASSIVE DELAY LINE WITH A 10- GB/SEC NRZ DATA INPUT. (A) BEFORE AND (B) AFTER THE EQUALIZATION. 50-PS/DIV DISPLAYED FIG CHIP MICROPHOTOGRAPH OF THE FFE WITH PASSIVE DELAY LINE APPROACH..38 FIG FREQUENCY RESPONSES OF THREE EXAMPLE CHANNELS AND THE CORRESPONDING OPTIMAL EQUALIZER RESPONSES FIG. 3.2.(A) BACKPLANE CHANNEL CONFIGURATION INCLUDING 8-IN AND 20-IN FR-4 TRACE LENGTH AND (B) THE CORRESPONDING CHANNEL FREQUENCY RESPONSE...41 FIG FUNCTIONAL BLOCK DIAGRAM OF THE RECONFIGURABLE EQUALIZER THAT IS SHOWN WITH VTGA AND ACTIVE TUNABLE DELAY LINES...43 FIG SYSTEM SIMULATION RESULT AT 10-GB/SEC NRZ SIGNAL (A) BEFORE EQUALIZATION OVER 8-IN BACKPLANE, (B) EQUALIZATION WITH TAU/3 TAP SPACING, AND (C) TAU/2 TAP SPACING...45 FIG BLOCK DIAGRAM OF THE SETTABLE EQUALIZER WITH ACTIVE DELAY LINE FIG BANDWIDTH COMPARISON OF ACTIVE DELAY LINE WITH CONVENTIONAL PASSIVE LOAD VS. ACTIVE DELAY WITH ACTIVE INDUCTANCE LOAD FIG ACTIVE DELAY LINE PERFORMANCE SHOW GOOD AGREEMENT BETWEEN (A) SIMULATION AND (B) MEASURED PERFORMANCE FOR THE TARGETED TS/3 TAP SPACING FIG MEASURED PERFORMANCE OF THE FFE WITH ACTIVE DELAY LINE WITH A 10- GB/SEC NRZ DATA INPUT (A) BEFORE AND (B) AFTER EQUALIZATION OF A 20-IN BACKPLANE CHANNEL FIG MICROPHOTOGRAPH OF THE FFE WITH ACTIVE DELAY LINE APPROACH FIG RECONFIGURABLE FFE BLOCK DIAGRAM...54 FIG FUNCTION BLOCK DIAGRAM OF THE ACTIVE TUNABLE DELAY LINE...57 FIG SCHEMATIC OF THE ACTIVE TUNABLE DELAY LINE...58 FIG SIMULATION RESULT OF THE ACTIVE TUNABLE DELAY LINE ILLUSTRATING TRANSITION FROM FAST PATH TO SLOW PATH...59 FIG DELAY TIME VERSUS CORRESPONDING CONTROL VOLTAGE...60 FIG AC SIMULATION OF THE ACTIVE TUNABLE DELAY LINE DEMONSTRATING 7GHZ OF -3DB BANDWIDTH...61 FIG TRANSIENT RESPONSE OF A RECONFIGURABLE EQUALIZER THROUGH THREE ACTIVE TUNABLE DELAYS WITH 25PS TAP SPACING FIG BIT-MODULE-BASED 8-BIT DAC WITH MODIFIED R-2R TOPOLOGY...62 FIG CHIP MICROPHOTOGRAPH OF A 6-BIT MODULAR DAC INTEGRATED WITH AN ACTIVE TUNABLE DELAY...63 FIG MODULAR 6-BIT DAC DC OUTPUT READING vii

9 FIG MEASUREMENT RESULTS OF THE DIGITALLY CONTROLLED ACTIVE TUNABLE DELAY WITH 3-PS EFFECTIVE TUNING RESOLUTION...65 FIGURE GAIN VARIATION FOR DIFFERENTIAL PAIR. (A) DIFFERENTIAL PAIR WITH CURRENT SINK VARIATION. (B) DIFFERENTIAL PAIR WITH SOURCE DEGENERATION VARIATION FIG CONVENTIONAL GILBERT CELL TOPOLOGY...68 FIG MODIFIED GILBERT CELL-BASED VTGA WITH FOLDED GAIN CONTROL BLOCK. 69 FIG DC GAIN CURVE OF THE VTGA CELL SHOWING DYNAMIC RANGE AND LINEARITY...70 FIG BANDWIDTH PERFORMANCE OF THE VTGA IN EXCESS OF 7GHZ ACROSS VARIOUS GAIN SETTINGS FIG ILLUSTRATION OF THE LAYOUT ARTWORK WITH MINIMIZED PARASITIC CAPACITANCE AND SYMMETRIC DATA PATHS TO IMPROVE THE RECONFIGURABLE FFE PERFORMANCE...72 FIG THE RECONFIGURABLE EQUALIZER PERFORMANCE MEASUREMENT SETUP OVER 8-IN AND 20-IN BACKPLANE TRACE LENGTHS...73 FIG PHOTO CAPTURE OF THE CORRESPONDING MEASUREMENT SETUP FIG BANDWIDTH OF THE RECONFIGURABLE EQUALIZER FIG BANDWIDTH TEST WITH A 10-GB/SEC PRBS 2^31 NRZ DATA PASSING THROUGH ONE TUNABLE DELAY AND ONE VTGA...75 FIG OUTPUT AFTER 8-IN BACKPLANE WITH 10-GB/SEC PRBS 2^-31 NRZ...76 FIG OUTPUT AFTER 8-IN BACKPLANE WITH 10-GB/SEC PRBS 2^-31 NRZ WITH TAP SPACING IS SET TO TAU/2 (τ=50ps) FIG OUTPUT AFTER 8-IN BACKPLANE WITH 10-GB/SEC PRBS 2^-31 NRZ WITH TAP SPACING IS SET TO (A) TAU/3 (τ=33ps) AND (B) TAU/4 (τ=25ps) FIG OUTPUT AFTER 20-IN BACKPLANE WITH 10-GB/SEC PRBS 2^-31 NRZ WITH TAP SPACING IS SET TO TAU/2 (τ=50ps) FIG OUTPUT AFTER 8-IN BACKPLANE WITH 10-GB/SEC PRBS 2^-31 NRZ WITH TAP SPACING IS SET TO (A) TAU/3 (τ=33ps) AND (B) TAU/4 (τ=25ps) FIG CHIP MICROPHOTOGRAPH OF THE RECONFIGURABLE EQUALIZER IC FIG FUNCTIONAL BLOCK DIAGRAM OF THE NOVEL TRANSITION DETECTOR-BASED OUTPUT MONITORING BLOCKS INTEGRATED WITH THE RECONFIGURABLE EQUALIZER FIG CONCEPTUAL ILLUSTRATION OF TRANSITION DETECTOR FIG SCHEMATIC OF THE PROPOSED FIXED ACTIVE DELAY LINE...86 FIG SCHEMATIC OF THE PROPOSED SUBTRACT-AND-SQUARE CIRCUIT viii

10 FIG TRANSITION DETECTION SIMULATION. WITH MORE TRANSITION (I.E. MORE OPEN EYE-DIAGRAM), THE OVERALL OUTPUT POWER IS HIGHER, RESULTING IS HIGHER DC LEVEL WHEN SQUARED AND INTEGRATED FIG SCHEMATIC OF A CHARGE PUMP-BASED INTEGRATOR FIG SIMULATION RESULTS OF A CHARGE PUMP-BASED INTEGRATOR...92 FIG SIMULATION RESULTS THAT DEMONSTRATE THE PROPOSED TRANSITION DETECTOR-BASED OUTPUT MONITORING TECHNIQUE...93 FIG. 5.1 PROPOSED DLL ARCHITECTURE FOR FUTURE RESEARCH ix

11 LIST OF SYMBOLS AND ABBREVIATIONS BER BERT BPF CD CMOS CP CW DAC DFE DLL DMD FFE FIR FSE IC ISI LE LMS LMSE LPF MLSD MMF MMSE NEXT NMOS NRZ PAM PD PMD PMOS PRBS PRML SMF TD-OM VGA VTGA ZF Bit-Error Rate Bit-Error Rate Test Band Pass Filter Chromatic Dispersion Complimentary Metal Oxide Semiconductor Charge Pump Continuous Wave Digital-to-Analog Converter Decision-Feedback Equalizer Delay-Locked Loop Differential Modal Dispersion Feed-Forward Equalizer Finite-Impulse Response Fractionally Spaced Equalizer Integrated Circuit Inter-Symbol Interference Linear Equalizer Least Mean Square Least-Mean Square Error Low Pass Filter Maximum Likelihood Sequence Detection Multi-Mode Fiber Minimum Mean Square Error Near End Cross Talk N-type Metal Oxide Semiconductor None Return-to-Zero Pulse Amplitude Modulation Phase Detector Polarization Mode Dispersion P-type Metal Oxide Semiconductor Pseudo Random Bit Sequence Partial Response Maximum Likelihood Single Mode Fiber Transition Detector-based Output Monitoring Variable Gain Amplifier Variable Tap-Gain Amplifier Zero Forcing x

12 SUMMARY The objective of the proposed research is to realize a 10-Gb/sec serial data link over band-limited channels, such as backplanes, multi-mode fiber, and copper-based cables that were originally designed for data rates less than 1Gb/sec. This is achieved using electrical equalization implemented in an integrated circuit (IC). To successfully compensate for various band-limited channels at the targeted data rate with a single equalizer IC, a reconfigurable equalizer topology is proposed. In order to realize the proposed goal, various channels are characterized of their forward transmission frequency response. Based on the measured channel data, system simulations are performed to identify the required specifications for IC implementation. This provides information such as optimal number of taps, fractionally-spaced tap delay, and tap coefficients for the proposed IC. With the obtained system requirements, IC building blocks are designed and fabricated in a 0.18-µm CMOS technology. The fully-integrated reconfigurable CMOS equalizer provides a single-chip solution for compensating various band-limited channels. This enables 10-Gb/sec serial data transmission achieving signal integrity beyond their designed specifications. xi

13 CHAPTER I. INTRODUCTION The demand for higher data throughput has been increasing tremendously over the past decade. Fig. 1.1 illustrates bandwidth growth from the 1980 s. The time interval between one order of magnitude growths has been decreasing, indicating the need for 10- Gb/sec data transmission is now imminent over existing band-limited channels such as copper based cables, backplanes and fibers. As of 2006, the IEEE 802.3ae, the IEEE 802.3ak, the IEEE 802.3an, and the IEEE 802.3aq standards for 10 Gigabit Ethernet over fiber, 10 Gigabit Ethernet over twin-axial cable, 10 Gigabit Ethernet over unshielded twisted-pair respectively, and 10 Gigabit Ethernet over multi-mode fiber (MMF) have been approved. The IEEE 802.3ap standard for 10 Gigabit Backplane Ethernet is expected to be approved in 2007 [1]. Fig Bandwidth growth timeline. 1

14 Moreover, increasing demand of multi-media contents usage such as streaming video over internet and satellite broadcasting over hand-held devices as illustrated in Fig. 1.2(a) and Fig. 1.2(b), has further increased the requirements for higher data-rate processing over the existing infrastructures that was originally designed to handle lower data throughputs. Meanwhile, the advances in optical links and the supporting electronics have dramatically increased the speed and amount of data traffic handled by a network system. However, the band-limited links are not keeping pace with these technical improvements for multi-gbit serial data communication and are becoming a critical bottleneck. (a) (b) Fig (a) Satellite based digital multimedia broadcasting handhelds that requires broader bandwidth capabilities of the copper-based PCBs inside, (b) Increasing demand on streaming multimedia contents over the internet, pushing the overall data throughput higher in the network. The primary physical impediments to high data rates in legacy backplane channels are the frequency-dependent loss characteristics of copper channels. Above 2

15 rates of 2 Gb/sec, the skin effect and dielectric loss in backplane copper channels distort the signal to such a degree that signal integrity is severely impaired [1-4]. This dispersive forward channel characteristic contributes to the Inter-Symbol Interference (ISI). Meanwhile, a major limiting factor to increasing transmission speeds and distances in fiber-optic communication links is modal dispersion causing ISI. Modal dispersion results when the numerous guided modes are transmitted with different paths in the multi-mode fiber (MMF), resulting in different receiving times at the receiver side of the fiber communication system. Modal dispersion becomes a severe factor as the length of the MMF is extended or the data rates are increased. The channel bandwidth limitation and modal dispersion can be addressed by using a channel-compensation technique, namely, equalization at the transmitter and/or receiver side [5, 6]. An equalization technique compensates the frequency-dependent channel loss characteristics. The band-limited channel has a low-pass frequency response, as shown in Fig. 1.3(a). The larger loss in high frequency range causes the signal power to smear into the neighboring symbols. The equalization technique restores the high frequency component of the original transmitted signal. Thus, the frequency response of equalizer has larger gain values for the high frequencies compared to low frequencies around DC, as shown in Fig. 1.3(b). Meanwhile, the equalization can be interpreted as a process to sharpen the channel impulse response, as shown in Fig The width of the channel impulse response means the degree of signal power dispersion in the time domain for a given pulse width. Therefore, an equalizer can be regarded as a spectrumshaping filter to shorten the channel impulse response to bring it back to its original transmission width. 3

16 Channel Response Equalizer Response Combined System Response 1/A f A o 1/A o 1 A f Frequency(f) Frequency(f) Frequency(f) (a) (b) (c) Fig Conceptual illustration of equalization (a) Channel response, (b) equalizer response, and (c) equalized response in frequency domain. Impulse Response Dispersive Channel Equalized Channel Time Fig Impulse response of an un-equalized and equalized channel. Digital equalization techniques have traditionally been used to reduce ISI in bandlimited wire-line applications, but such techniques require high-resolution analog-todigital converters with sampling rates at or above the symbol rate. The increased circuit complexity and power consumption required to apply these techniques to high-speed serial data transmission are prohibitive at the considered data rates. Hence, analog or mixed-signal equalization techniques are attractive alternatives for multi-gb/sec serial transmission [7, 8]. 4

17 The most common type of analog equalizer used in practice to compensate for ISI is a linear FIR filter with adjustable tap-coefficients, as shown in Figure 1.5. Each tap coefficient is updated through certain equalization algorithms. With the FIR structure implementation, there are several equalization algorithm criteria to reduce the ISI. Fig Functional block diagram of FIR-based linear equalizer. Meanwhile, if the channel frequency-dependent loss characteristics are time invariant, the channel can be measured and the tap coefficients for the equalization can be extracted from the measured channel characteristics. As the channel is time invariant, once the tap coefficients are set, the data can be transmitted without further adjusting the tap values. Another popular equalization technique is pre-emphasis, which was suggested to realize transmit-side equalization [9]. This equalization scheme pre-distorts transmit signal waveforms to enhance the data transition. As channel loss increases as a result of longer trace geometry, this technique needs to increase the amount of pre-distortion. 5

18 However, the maximum voltage swing is limited by the system constraints as well as the voltage headroom issue in IC implementation. Thus, the resulting decreased average signal level thereby leads to reducing the overall signal-to-noise ratio. Furthermore, this equalization technique may increase the amount of near-end cross talk, which is another major signal impairment factor in backplane applications [4,9]. Thus, the receive-side equalization technique is considered suitable for multi-gigabit data transfer. The receive-side equalization technique using a finite impulse response (FIR) filter structure was reported for a 10-Gb/sec backplane applications [10]. On-chip passive components were adopted to offer a bandwidth benefit necessary for 10Gb/sec equalization. Because of the intrinsic loss problem of this passive delay line, this analog equalizer has the limitation of the maximum number of taps in the FIR structure. Therefore, the development of a novel delay line structure is still requested. Furthermore, this passive component-based equalizer cannot provide adjustable compensation to diverse channel configurations. Figure 1.6(a) and Fig. 1.6(b) show a typical legacy backplane configuration and the corresponding channel loss characteristics, respectively. The loss characteristics are quite different depending on the trace length and the board material as shown in Fig. 2.4(b). Therefore, the amount of channel equalization needs to be adjusted and reconfigured to reflect each channel configuration. 6

19 (a) Fig (a) Backplane channel configuration including 8-in and 20-in FR-4 trace length and (b) the corresponding channel frequency response. (b) 7

20 In this dissertation, the background knowledge on band-limited serial data links is studied. More specifically, channel characteristics on FR-4-based backplane channels, and fiber optic cables are analyzed. The history and different types of equalization to compensate for backplanes and fiber dispersion is studied. From the literature survey of various type of equalizer implementation method, finite impulse response (FIR) type of equalizer is selected for this work. The system level equalizer simulation is performed for the given band-limited channels and the optimum system specification is extracted. In order to compensate for various channel characteristics with given process technology, it is demonstrated the need for a reconfigurable equalizer that can not only have different tap weights for equalization, but also have adjustable tap spacing to further improve the channel compensation ability. The reconfigurable equalizer is implemented on a single IC using a 0.18-µm CMOS technology. The reconfigurable equalizer IC is designed, fabricated and tested by transmitting and receiving an NRZ data successfully up to 10 Gb/sec data throughput. Finally, a novel output monitoring scheme is introduced for optimum coefficient extraction of the reconfigurable equalizer. The original contributions and main focus of this dissertation include: 1. Development of a novel adjustable active delay line in a 0.18-µm CMOS technology, which is first in its scheme for equalizer applications. 2. First reconfigurable FFE with 0.18-µm CMOS technology for 10-Gb/sec data throughput over backplane channels and fiber channels. 3. First to introduce transition detection-based output monitoring scheme for10-gb/sec serial data link applications. 8

21 This dissertation is organized as follows: In chapter 1, a brief historical background and origin of the problem for 10- Gb/sec serial data communication over band-limited channels is introduced. Following that, the organization of the dissertation is described. In chapter 2, serial data link for 10- Gb/sec is described in detail. The characteristics of band-limited channels such as FR-4- based backplanes and dispersion in MMF are analyzed. Various channels are characterized by S-parameter measurements. The measured frequency dependent loss characteristic of the channel is used to extract the optimum equalizer specification such as the number of tap, tap coefficients, and tap delay amount. An equalizer design to compensate for such channel is overviewed. The various types of band-limitation in backplane are described. The various types of dispersion in fiber are described with its effect on fiber communication system. The technical solutions to resolve these issues are introduced. Also various types of equalizers are presented from the system level configuration to the IC level implementation. As an initial approach, a settable equalizer with on-chip inductors is fabricated and measured for equalization of such channels. Chapter 3 focuses on the reconfigurable equalizer design with tunable active delay-line. First, the system level analysis is describe and demonstrate the need for a reconfigurable equalization for maximum performance achievable from a given process technology. Then the detailed CMOS IC implementation issues are presented with focus on circuit level design details. Building blocks for implementing a reconfigurable equalizer is described. Both transistor level simulation results and measurement results are presented to illustrate step-by-step design procedures. Finally, measurement results demonstrating performance improvement is presented. The overall equalizer 9

22 configurations, design procedure, and transistor level building block is described in this chapter. The simulation and measurement result of this equalizer to compensate various band-limited channels at 10 Gb/sec data through put is shown as well. The chapter 4 describes a novel output monitoring scheme for further adjustments over time in order to provide optimum compensation in the reconfigurable equalizer performance. The feasibility of the transition detection-based output-monitoring scheme is demonstrated. Finally, chapter 5 summarizes the dissertation and provides guidance towards future research possibilities. 10

23 CHAPTER II. BACKGROUND ON SERIAL DATA LINKS 2.1 Band-limited Channel When a signal goes through a band-limited dispersive channel with an impulse response illustrated in Fig. 2.1(a) or Fig. 2.1(b), its output signal power spreads in time. This spreading of signal power causes ISI. In other words, transmitting a square pulse through such a dispersive channel results in a widened and flattened pulse at the far end. This implies that each data bit of information overlaps with its adjacent bits. This overlap can cause major distortions of the signal. At high data rates and in long channels, the ISI can be so severe that it becomes impossible to recover the original transmitted data. This is a major phenomenon limiting data transmission and must be addressed for multi- Gb/sec serial data communications over band-limited channels. Therefore, it is necessary to analyze the impact of channel characteristics on signal integrity in order to compensate for the degradation caused by each channel. In this section, optical fiber links and backplane channels are investigated in more detail. The major cause of signal dispersion in both fiber optic channels and backplane channels are analyzed with the suggested solution to recover signal integrity. Following that is the summary of different channel compensation techniques to improve signal integrity over 11

24 serial data links. Finally, channel compensation with a settable equalizer is shown to demonstrate the channel compensation. (a) (b) Fig Impulse Response of (a) 8-, 20-in backplane channels and (b) 500-m MMF. 12

25 Fiber Optical Link The major concern in fiber optic communications is pulse dispersion resulting in ISI. The ISI becomes more severe as data rate and distances are increased. In this section, three different types of dispersion are briefly reviewed. In a multi-mode fiber (MMF), the numerous guided modes travel at different speeds, resulting in pulse dispersion at the receiver. This is called differential-modal delay (DMD) and results in ISI. Due to DMD and the resulting ISI, MMF usage is limited to short-haul applications at 10-Gb/sec up to 300 m with none-return to zero (NRZ) serial data [5, 8]. In a single-mode fiber (SMF) data links as illustrated in Fig. 2.2(a), polarizationmode dispersion (PMD) and chromatic dispersion (CD) cause ISI. PMD is created when two polarization modes experience slightly different conditions, as a result of a generic imperfect circular symmetry of fibers and other external stress on the fibers, and travel along the fibers at different speeds. CD is created by the variation of the speed of light through the fiber depending on a wavelength. The CD is the sum of two quantities, dispersion inherent to the material and dispersion arising from the structure of the waveguide. PMD and CD are the main dispersion factors in SMF [9]. An optical system for the characterization of 25-km SMF is shown in Fig. 2.2(a). The optical signal is transmitted with a continuous-wave laser module, and received with a pin diode, forming a 2-port network. The corresponding impulse response of the optical link is plotted in Fig. 2.2(b). As expected, the channel is dispersive. As shown in Fig. 2.2(c), the signal integrity of the transmitted 10-Gb/sec signal has been severely degraded and the original information is unrecoverable without compensation [10]. 13

26 (a) (b) Fig Optical link system simulation (a) schematic, (b) channel response, and (c) eye diagram after 25-km SMF with 10-Gb/sec NRZ signal input. (c) 14

27 As illustrated above, fiber optical links introduce dispersion in signals, which results in degraded signal integrity. As data rate and/or link distance increases, dispersion in the fiber optical links becomes more severe and contributes to ISI. Thus, it is necessary to compensate this degradation. Moreover, a fixed compensation for degraded signals cannot cover different types of channels such as MMF and SMF that has different channel impulse responses as illustrated in Fig. 2.1(b) and Fig. 2.2(b). Hence, it is necessary to include a method to flexibly adjust to variations in data rate, types of fiber, and link distances for optimum channel compensation. In this chapter, a settable equalizer is introduced with variable tap weights that can address the channel dispersion to a certain extent. In the following chapter, and reconfigurable equalizer is introduced with variable tap spacing in addition to the variable tap weights to further improve the channel compensation Backplane multi-gb/sec Data Interface Channel loss is an important electrical parameter that affects the channel response and influences the design of various components in a backplane link. The channel loss is composed of conductor loss and dielectric loss. Both conductor loss and dielectric loss are directly proportional to frequency and thus become severe in the microwave frequency range (i.e. beyond 1 GHz) for FR-4 dielectric-based components such as backplanes. This channel loss induces dispersion and degrades signal integrity severely. The channel loss is a major impediment in multi-gb/sec backplane signaling [11]. At low frequency around DC, the conductor loss depends on the resistivity of the conductor and total area over which current is flowing. Since the dielectric material in 15

28 printed circuit boards (PCBs) is not a perfect insulator, there is DC loss associated with flowing current through the dielectric material between a signal conductor and a reference plane. However, the conductor loss at DC for commercial PCB substrates is usually very negligible and can be ignored. However, as frequency increases, skin effect comes into play. The skin effect is a physical phenomenon in which current flowing in a conductor migrates toward the periphery of skin of the conductor as frequency increases. With increasing frequency, the non-uniform current distribution in the transmission line causes the resistance of a conductor to increase with the square-root of frequency. Thus, high-frequency components experience more loss than low frequency components [12]. Figure 2.3(a) shows the system setup to characterize backplane channels. Two line cards are connected by transmission lines on a backplane, forming a 2-port network, and S21 of the network has been measured for 8- and 20-in channels. The line card can be inserted at different separation length via connectors resulting in various overall trace lengths. As can be expected from the impulse responses illustrated in Fig. 2.1(a), they behave like low-pass filters, depressing high-frequency components, thus causing dispersion for longer trace length. Figure 2.3(b) shows the resulting eye diagram of a 10- Gb/sec NRZ signal at the output of a 20-in FR-4 backplane channel. As shown in Fig. 2.3(b), the output signal is severely degraded for the 20-in case such that the signal cannot be recovered. It clearly illustrates the need for compensation to maximize the link distance while maintaining signal integrity. Furthermore, different board materials with unique dielectric constants show different characteristics. This implies that the compensation should be adjustable or reconfigurable to cover these variations. 16

29 (a) Fig Forward Transmission FR-4 backplane traces. (a) schematic of the system configuration, and (b) eye-diagram at the receiver input of a 10-Gb/sec NRZ signal after 20-in backplane trace. (b) 17

30 The backplane channel loss characteristics are frequency-dependent. Specifically, high-frequency components of the input signal experience larger loss than the lower frequency components around DC. This high-frequency loss becomes worse in the longer backplane channel environment, as shown in Fig Figure 2.4 show that 20-in FR-4 backplane has a much larger attenuation or loss compared to 8-in FR-4 backplane observed in the frequency domain. The resulting impulse response of the 20-in FR-4 backplane has more DC signal power loss and more widened pulse shape compare to 8-in channel, as shown in Fig. 2.1(a). Fig Forward transmission frequency response of a 8-, 20-in FR4 backplane traces. Meanwhile, Fig. 2.5 shows the forward transmission characteristics of a MMF with different lengths (100 m and 500 m). As expected, the 500-m MMF has more channel loss compared to the 100-m MMF. Figure 2.1(b) shows the impulse response of 18

31 the 500-m MMF channel. The second major mode is followed by the first major mode by approximately 100ps, which is the single symbol duration for the 10-Gb/sec data rate. Fig Forward transmission frequency response of a 100- and 500-m MMF. As illustrated above, data communications through both fiber and backplane copper channels distort the transmitted signal, causing considerable ISI. As a result, it becomes impossible to communicate at high speeds beyond a certain distance using existing infrastructure. Furthermore, the difference in width of the dispersive channel from the impulse response shown in Fig. 2.1(a) and Fig. 2.1(b) suggests that different tap spacing is needed for optimal equalization. These impulse responses of the dispersive channel support the need for reconfigurable equalization for effective channel compensation. In the following section, various equalizer topologies are summarized. 19

32 2.2 Equalizer topology study The basic function of an equalizer is to compensate any signal distortions or any general losses resulting from channel loss characteristics. A simple linear equalizer has the equivalent mathematical transfer function as follows, G E ( f ) = 1 C( f ) = 1 C( f ) e" j# c ( f ) (2.1) where, C(f) is the channel characteristics and G E (f) is equalizer transfer function characteristics [12, 13]. Therefore the amplitude response of the equalizer is G E ( f ) = 1/ C( f ) and its phase response is " E ( f ) = #" c ( f ). As the equalizer transfer function is inverse form of the channel, the equalizer completely eliminates the ISI cause by channel. This equalizer is called zero-forcing equalizer. For example, the copper channel such as telephone line or twist cable, has low pass filter characteristics resulting in increased rising time and falling time of the transmitted signal. The increased rising time and falling time causes the ISI, in other words, the dispersion in the channel impulse response. The ISI is the main source of the signal distortion in digital communication systems. Figure 2.6 shows the conceptual view of the signal dispersion in lossy channel. 20

33 Fig Impulse response of a copper-based channel with dispersion. Through the equalization at the receiver side, one can rebuild the transmitted signal shape from the dispersive signal at the receiver front end. This work can be done in the receiver side as explained above, or the signal can be transmitted with some intended signal distortion at the transmitter side. This is called pre-emphasis technique. This section will touch the background knowledge of equalization, various types of equalizations, and the pros and cons of the each equalization techniques Linear equalizer Most common types of a channel equalizer used in practice to compensate ISI are a linear FIR filter with adjustable tap coefficients as shown in Fig Each tap coefficients are updated through the certain equalization algorithms. With the FIR 21

34 structure implementation, there are several equalization algorithm criteria to reduce the ISI. Fig Linear FIR equalizer. Most simple linear equalizer type is the zero-forcing equalizer as described previously. The zero-forcing equalizer has the transfer function characteristics as described in equation 2.1. The time delay element in Fig. 2.7 is called tap delay. The tap delay can be as large as symbol interval so the delayed version of the signal is x(t " k#) (where τ=t, T is the symbol period of the signal, and k=1,..., n). Also τ can be smaller than T, in this case, it is called fractionally spaced equalizer. The fractionally spaced equalizer can reduce the aliasing problem in a symbol spaced equalizer and improve the performance assuming the delay is implemented by sampling [14, 15]. As the zero forcing equalizer has inverse channel transfer function characteristics, it can significantly 22

35 increase the additive noise in the channel. An alternative solution to ameliorate this problem is the minimum-mean-square-error (MMSE) algorithm, where the tap value is optimized to minimize the power in the residual ISI and the additive noise in the channel. If the channel frequency dependent loss characteristics are time-invariant, the channel can be measured and the tap coefficients for the equalization can be extracted from the measured channel characteristics. As the channel is time-invariant, once the tap coefficients are set, the data can be transmitted without further adjusting the tap values. However, if the channel is time-variant such as the wireless channel, the equalizer tap values should be updated periodically based on the real-time channel frequency characteristics. The equalizer that can update the tap value by tacking the channel characteristics is called adaptive equalizer. Most commonly used adaptive equalization algorithm is LMS algorithm [16]. The tap coefficients to be updated based on the LMS algorithm are shown as follow: p(k+1)=p(k)-µ "E[e2 ] "p or, p(k+1)=p(k)+2µ e(k) φ(k) (2.2) where, p(k) is the tap coefficients, µ is the parameter controlling the adaptation rate, e(k) is the error signal between the desired signal and received signal, and φ(k) is the derivative form of the received signal (i.e. "y, where y is the signal after the adaptive "p equalization). Figure 2.8 shows the one example of adaptive equalization. In this example, the transmitted signal is required at the receiver side (i.e. training sequence) as 23

36 shown in Fig. 2.8(a), or desired signal can be extracted from the receiver s decision block as shown in Fig. 2.8(b). (a) (b) Fig Adaptive equalization (a) using training sequence and (b) using the decision signal at the receiver as the desired signal. The practical implementation of the LMS algorithm still requires lots of hardware. So there are several alternative simplified algorithms to reduce the burden in hardware implementation. The simplified version of LMS algorithms is as follow [17, 18]: 24

37 Sign-data LMS: p(k+1)=p(k)+2µ e(k) sgn(φ(k)) Sign-error LMS: p(k+1)=p(k)+2µ sgn(e(k)) φ(k) Sign-sign LMS: p(k+1)=p(k)+2µ sgn(e(k)) sgn(φ(k)) Despite the advantages in hardware implementation, these simplified algorithms have potentials that they may not be converted and they may have slower adaptation time than the original algorithm Nonlinear equalizers Linear equalizers described in previous section are very effective on channels, such as wire line telephone channels, where the ISI is not severe. However in some channel environments, for example the channel where spectrum null exists, the linear equalizer will introduce large amount of gain to compensate the spectrum null. Thus the noise in the channel will be enhanced severely. Such channels are often encountered in mobile radio channel, such as those used for cellular radio communications. A decision-feedback equalizer (DFE) is a nonlinear equalizer that employs previous decisions to eliminate the ISI caused by previously detected symbols on the current symbol to be detected. The block diagram for the conventional DFE is shown in Fig

38 Fig Block diagram of the conventional DFE. The DFE is typically used with the conjunction of a linear feed-forward equalizer (FFE) as shown in Fig Even though the linear FFE alone can be used to cancel the ISI, the combination of the linear FFE and DFE has better performance. The principle reason for this improvement is that the DFE uses the linear combination of the noiseless binary decisions to eliminate some of the ISI and does not add noise at the input of the decision circuit. The linear FFE amplifies the high-frequency portion of the signal and the noise to cancel the ISI, which is not compensated by DFE. So the noise enhancement of the linear FFE in conjunction with DFE is less than the one when the linear FFE alone is used. Recently, the DFE is reported as a good candidate for backplane channel equalization, where the near-end-crosstalk is severe [19]. Otherwise the FFE alone will 26

39 significantly amplifies the near-end-crosstalk because the near-end-crosstalk frequency response is similar to the high pass filter response. One potential problem with a DFE is the error propagation [20, 21]. If the DFE outputs an incorrect decision, the error will propagate through the feedback filter and increase the probability that another incorrect decision will be made. There is another algorithm, which finds the sequence that maximizes the joint probability of the received sequence conditioned on desired sequence. This sequence is called the maximum-likelihood sequence detector. An algorithm that implements maximum-likelihood sequence detection (MLSD) is the Viterbi algorithm. Partialresponse maximum-likelihood (PRML) detectors using various implementations of the Viterbi algorithms are a popular choice for hard disk drive read channel, where digital communication techniques are adapted to combat the ISI [21, 22]. The major drawback of MLSD is the exponential behavior of the computational complexity, which is a function of the ISI span. Thus the MLSD is practical for the channel where the ISI spans only a few symbols [23] Bode equalizer In this section, one typical form of the equalizer specifically for the cable channel will be covered. As the cable channel can be modeled with simple low pass filter transfer function, the cable equalizer can be implemented with the combination of the high pass filter with several poles as design parameters and variable gain controller as shown in Fig

40 (a) (b) Fig (a) Block diagram for the simple cable equalizer and (b) corresponding frequency response indicating pole locations. The variable gain can be controlled via a LMS or other algorithm for adaptation. The cable equalizer is practical to implement by analog continuous time signal processing compared to other type of equalizer. The continuous time equalization techniques have some advantage over discrete time counterpart. For example, the continuous time equalizer does not need any sampling phase recovery block, so that the equalizer 28

41 adaptation can be realized independently with the timing recovery function [24, 25]. Also the continuous time equalization is well fit for high-speed operation over the discrete time counterpart, as it does not need any high-speed sampling function. Even though these advantages, the cable equalizer has some potential problem that it can boost up the high-frequency noise, which is analogous phenomenon in the linear FFE Transmitter and receiver side equalizer As it is mentioned previously, the equalizer can be installed at the transmitter side or receiver side. The conceptual block diagram is shown in Fig The transmitter side equalizer, which is called pre-emphasis, has an advantage over receiver side equalizer such as ease to build by FIR filter type with digital control [26]. However, firstly, the preemphasis boost up the high-frequency portion on the transmitter side so that it can increase the near-end-crosstalk for high-speed chip-to-chip interconnections. Secondly, the pre-emphasis requires the information sent from the receiver side for dynamic or finetuned tap coefficients updates. Finally, as channel loss increases, the pre-emphasis needs to apply more gain to boost the high-frequency components of the transmit signal. Since the maximum signal swing is limited by the system constraints and the IC process technology, the average signal swing level at the transmitter side needs to be decreased thereby requiring additional gain at the receiver side. By these reasons, the equalizer at the receiver side is better candidate over the pre-emphasis for adaptive or fine tuned equalization. However as it is mentioned previously, the FIR type equalizer alone at the receiver side enhance the noise at high-frequency ranges, while it compensates the 29

42 channel loss to reduce the ISI. This is the one of the reason why we use DFE with combination of FFE, not just using FFE at the receiver side in the channel environment where the large amount of gain is required to compensate any severe spectral loss. Fig Equalization at the transmitter side, receiver side and both sides. It is also possible to use the combination of the pre-emphasis and receiver side equalization to further increase the overall bit-error rate (BER) of the high-speed interconnections. By using the pre-emphasis and receiver side equalization simultaneously, the gain-boosting requirement for specific spectral loss can be relaxed for each equalizer. However it needs more complex hardware implementation increasing the overall system cost. For the digital communication systems, the typical equalizer is implemented with digital circuitry as the required data rate is below Gb/sec. For example, the wireless communication system requires the equalization to compensate the multi-path-fading 30

43 effects. The equalizer IC for this type of channel has been implemented by conventional digital circuitry because the required data rate is still far below 1 Gb/sec. However, as the data rate is increased over multi-gb/sec, the conventional digital approaches are not proper solution anymore. By this reason, several standard task forces have been made such as XAUI, PCI-express, and UXPI to address any high-speed interconnection problems in system and packaging level. Also in an IC implementation point of view, there have been several efforts for equalizer IC implementation by approaching in continuous-time analog signal processing, mixed-signal circuit, or RF/microwave techniques over conventional digital circuit approaches [27, 28, 29]. In the following section, an FFE with fixed-delay is presented for demonstration of channel compensation technique at 10-Gb/sec with detailed theoretical background for the targeted circuit design with on-chip passive inductors. Measurement results that clearly shows improvements in signal integrity is presented. 2.3 Band-limited channel compensation Feed-Forward Equalizer (FFE) Receiver equalization can be implemented with analog FIR filter structures, which can be classified as zero forcing-linear equalizer (ZF-LE) or minimum mean squared error-linear equalizer (MMSE-LE), depending on the tap coefficient calculation principles [30]. As the transfer function of ZF-LE is the reciprocal of the channel transfer 31

44 function, as is illustrated in Fig. 2.12, it can remove ISI completely but does so neglecting the impact of high-frequency cross-talk (Xtalk) noise, which is also amplified. In contrast, MMSE-LE can ameliorate this noise enhancement problem, since its tap coefficients are calculated to minimize overall signal degradation from both ISI and Xtalk noise. The frequency response relationship between the band-limited channel, ZF-LE, and MMSE-LE is illustrated in Fig Optimum tap coefficients for various bandlimited channels are extracted with the use of impulse response information, illustrated in Fig. 2.1(a) and Fig. 2.1(b). Fig Frequency response of band-limited channel, ZF-LE, and MMSE-LE The overall circuit is implemented using the continuous-time analog signal processing technique. The discrete time equalization requires clock phase information from the incoming data and the sampling circuitry, resulting in limited bandwidth characteristics. Thus the continuous-time analog signal processing technique makes it 32

45 easier to operate at high data rates compared with the discrete-time-based equalizers. The overall block diagram for the equalizer is shown in Fig Fig The FFE configuration with passive LC ladder delay line approaches The continuous-time delay line in the FFE is implemented via two different implementation approaches. The passive delay line-based equalizer and the active delay line-based equalizer are shown in Fig. 2.13, where the artificial transmission line is used as the delay element for the passive delay line and the active peaking load is used for the 33

46 active approach. This active approach is the basis for constructing a reconfigurable equalizer and will be covered in detail in Chapter III. The following section presents details on settable equalizers with passive delay line. It will be demonstrated that settable equalizers can improve the BER, but leaves room for improvements. In the next chapter, reconfigurable equalizer is introduced that can further improve the signal integrity with tunable tap spacing to cover various channel configurations Settable Equalizer with Passive Delay Line In this equalizer design, the distributed passive network is used for the continuous-time analog signal delay, as illustrated in Fig For the matched termination to the characteristic impedance of the artificial transmission line, a halfsection for the termination is used as shown in Fig By using the half-section termination, the bandwidth for the artificial transmission line is increased further [31, 32]. The artificial transmission line constructed by the LC ladder is designed with a 50-ohm differential characteristic impedance. This is achieved by the appropriate choice of inductance, L t and capacitance, C t, as shown in the following equation, where L t and C t are the inductance and capacitance of each LC section. The characteristic impedance, Z o, and the time delay of each segment, T delay, are defined as follows, Z 0 = L t C t, T delay = L t " C t (2.3) 34

47 The lumped-element analog LC delay line can work as a transmission line below the cutoff frequency. However, over this frequency the input impedance of the lumped- LC line will be eventually purely reactive. The input impedance of the lumped LC delay line can be presented as, Z in = jwl # 2 1± 1" 4 & % $ w 2 LC ' ( (2.4) Hence, the cutoff frequency, where the input impedance is purely reactive, is, w cutoff = 2 LC (2.5) From this simple calculation, we can verify that the lumped-lc line has enough bandwidth to work as a delay line for a given equalizer structure. A 1.5 nh inductor is designed using an Analysis and Simulation of Inductors and Transformers in Integrated Circuits, also known as an ASITIC simulator, and is implemented by optimizing the line space and number of turns to increase the selfresonance frequency of the inductor via enhancing the Q factor. Both the simulation and measured results for the LC ladder structure are shown in Fig. 2.14(a) and Fig. 2.14(b), respectively. From the figure, the zero crossing point for each adjacent signal is delayed by a fixed 33-ps tap spacing as designed. 35

48 (a) Fig Passive delay line performance show good agreement between (a) Simulation and (b) measured performance for the targeted fixed-ts/3 (=33ps) tap spacing. (b) 36

49 The performance of the FFE with passive delay line is demonstrated with equalization measurement over a 500-m MMF channel. Fig. 2.15(a) shows the received 10-Gb/sec NRZ signal eye diagram without equalization. The signal is severely impaired by ISI of the 500-m MMF and it cannot be mitigated with additional optical power. Fig. 2.15(b) shows the same eye diagram after the 4-tap FFE. The majority of the ISI is removed, where a 10-Gb/sec data can be retrieved. (a) (b) Fig Measured performance of the FFE with passive delay line with a 10-Gb/sec NRZ data input. (a) Before and (b) after the equalization. 50-ps/div displayed. 37

50 Figure 2.16 illustrates the chip microphotograph of the FFE with passive delay line. As it is clear from the figure, CMOS on-chip inductors occupy large die area. The overall chip size is 1.09 mm by 1 mm including pad area. Total power dissipation for the passive delay line based FFE is about 9mW. Fig Chip microphotograph of the FFE with passive delay line approach. Since the FFE with on-chip passive inductors have fixed tap spacing, it is not possible to tune the delay of the FIR. In the next chapter, a new approach in designing an equalizer, namely a reconfigurable equalizer, which can have adjustable delay to provide more flexibility in channel compensation, is introduced in detail. The detailed design procedure, system level performance and measurement results for the fabricated reconfigurable equalizer IC will be described as well. 38

51 CHAPTER III. RECONFIGURABLE EQUALIZER IC IMPLEMENTATION In Chapter II, band-limited channel characteristics were analyzed and various equalizer topologies were studied. For a 10-Gb/sec serial data links, analog continuoustime FFE was suggested for CMOS IC implementations. As a preliminary research, an FFE with passive delay line was fabricated and channel compensation was demonstrated at the end of the chapter. In this chapter, a novel concept of reconfigurable equalizer is introduced. For optimum equalization at the given process technology, increasing number of taps is not feasible due to bandwidth limitation for 10-Gb/sec applications. Hence, a new concept of reconfigurable equalizer is proposed that can adjust the tap spacing for further improving the channel compensation ability without having to increase the number of taps. For IC implementation, first the reconfigurable system will be overviewed. To realize a tunable active delay line, first the feasibility of active delay-based FFE needs to be shown. As active delay line have limited bandwidth compared to on-chip inductors, various design strategies will be introduced to improve the bandwidth for active delay approach. With demonstrated capability of implementing an active delay-based FFE at 10Gb/sec, the active tunable delay line will be introduced in details. Finally, measurement results demonstrating the performance of the reconfigurable FFE will be presented. 39

52 3.1 Reconfigurable Equalizer System overview Channel bandwidth limitation and modal dispersion can be addressed by using a channel-compensation technique, namely equalization at the transmitter and/or receiver side [33]. An equalization technique compensates the frequency-dependent channel loss characteristics. The band-limited channel has a low-pass frequency response, as shown in Fig The larger loss in high frequency range causes the signal power to smear into the neighboring symbols. The equalization technique restores the high frequency component of the original transmitted signal. Thus, the frequency response of equalizer has larger gain values for the high frequencies compared to low frequencies around DC, as shown in Fig Fig Frequency responses of three example channels and the corresponding optimal equalizer responses. 40

53 Figure 3.2(a) and (b) show a typical legacy backplane configuration and the corresponding channel loss characteristics, respectively. The loss characteristics are quite different depending on the trace length and the board material as shown in Fig. 3.2(b). Therefore, the amount of channel equalization needs be adjusted to each channel configuration. (a) (b) Fig. 3.2.(a) Backplane channel configuration including 8-in and 20-in FR-4 trace length and (b) the corresponding channel frequency response. 41

54 Meanwhile, the equalization can be interpreted as a process to sharpen the channel impulse response. The width of the channel impulse response corresponds to the degree of signal power dispersion in the time domain for a given pulse width. Therefore, the equalizer can be regarded as a spectrum-shaping filter that shortens the channel impulse response to bring it back to its original transmission width. An equalizer can be incorporated at the transmitter or the receiver. The transmitter equalizer, which is called a pre-emphasis equalizer, is easier to realize than a receiver equalizer, since the FIR filter can be built digitally. However, the pre-emphasis increases the near-end-crosstalk by boosting the high-frequency components for high-speed chipto-chip interconnections [34]. The pre-emphasis, moreover, requires the information gathered at the receiver to dynamically update the tap coefficients of the FIR filter at the transmitter. Also, since the maximum signal swing at the transmitter is limited by the system constraints and the IC process technology, it is necessary to have additional gain at the receiver to compensate the high frequency loss as the channel loss increases. For these reasons, the equalizer at the receiver is considered for the proposed work. The equalizer at the receiver can be realized with an analog FIR filter structure, which can be implemented as a Zero Forcing-Linear Equalizer (ZF-LE) or as a Minimum Mean Squared Error-Linear Equalizer (MMSE-LE) depending on the tap coefficient calculation principles [35]. As the transfer function of ZF-LE is the reciprocal of the channel transfer function, ISI caused by the frequency dependent channel loss can be removed. However, the high-frequency cross-talk noise can also be amplified. In contrast, MMSE-LE can ameliorate this noise enhancement problem, since its tap coefficients are calculated to minimize overall signal degradation caused by both ISI and 42

55 cross-talk noise. Frequency responses of the band-limited channel and the corresponding MMSE-LE are shown in Fig. 3.1 [36]. In order to make the system adjustable to various channel environments, a reconfigurable FIR filter is integrated at the receiver as illustrated in Fig The FIR filter consists of variable tap gain amplifiers (VTGA) and tunable tap delay lines. Based on the measured channel response, system simulation is performed to derive the optimal number of taps, the tap delay values, and the tap coefficients. In order to ameliorate the noise enhancement problem, the minimum-mean-squared error algorithm is used for calculation of the tap coefficients [37]. Fig Functional block diagram of the reconfigurable equalizer that is shown with VTGA and active tunable delay lines. 43

56 As is illustrated in Fig. 3.2, the reconfigurable equalizer has an additional degree of tuning capability with the added adjustable tap spacing, namely, τ χ. With this added tunable delay, the continuous-time analog filter now has the input to output relationship that is described as follows, y(t)=c 0 *x(t)+c 1 *x(t-τ χ )+C 2 *x(t-2τ χ )+C 3 *x(t-3τ χ ) (3.1) where, C 0 to C 3 is the tap weight values controlled by the VTGA in Fig To demonstrate the functionality of a reconfigurable equalizer, a system simulation is done with a 8-in backplane at 10-Gb/sec NRZ data. Figure 3.3(a) is the output eye-diagram after a 8-in backplane channel where the data is impossible to recover. For settable equalizers where only the tap weights can be varied such as the equalizer introduced in Chapter II, the tap spacing is already pre-determined and the equalization needs to be performed with varying the tap weights. Figure 3.3(b) is the output results with Tau/3 tap spacing where Tau/3 is a popular tap spacing distance used in many analog continuous-time FFEs [38]. As each channel configuration has different trace length geometries and unique channel materials, the impulse response can be different from each applications and the corresponding optimum tap spacing can be different for optimum equalization. Figure 3.3(c) illustrates the equalization with Tau/2 tap spacing with MMSE algorithm for the tap weights. It is clearly illustrated the BER can be improved further for the given IC technology. Hence, reconfigurable equalizers provide application and link configuration specific tailored channel compensation to further improve the BER overcoming the limitation of the given process technologies. 44

57 (a) (b) Fig System simulation result at 10-Gb/sec NRZ signal (a) before equalization over 8-in backplane, (b) equalization with Tau/3 tap spacing, and (c) Tau/2 tap spacing. (c) 45

58 As illustrated in Fig. 3.3, optimal equalizer system requirement varies for different channel configurations, demonstrating the need for a reconfigurable equalization technique to adjust over various band-limited signaling environments. In summary, Fig. 3.2 shows the functional block diagram of the FIR filter at the receiver for data communications over band-limited links. The 4-tap FIR filter is utilized to equalize the received signal. The FIR provides enough speed for 1- to 10-Gb/sec communications using relatively simple architecture. The FIR filter creates a frequency response for MMSE-LE as shown in Fig For optimum performance of the equalizer, system simulations were performed with Tau/4 (25ps), Tau/3 (33ps), and Tau/2 (50ps) tap spacing and were also investigated with 2, 3, and 4 tap quantities. Largest eye opening with minimum number of taps is chosen for a given channel to minimize power consumption. The number of taps can be chosen with the digital control and effectively turning off the VTGA for the targeted tap weights control. This added feature of controlling the tap weights and effectively switching off can be formulated as follows, y(t)=c 0 *x(t)+c 1 *x(t-τ χ )+SW1*C 2 *x(t-2τ χ )+SW2*C 3 *x(t-3τ χ ) (3.2) where, the SW1 and SW2 are the digitally controlled DC bias cutoff that can effectively switch off those taps for minimum power consumption while achieving maximum equalization performance. In the system simulation, practical implementation limitation, such as the 3dB bandwidth of each tunable delay line and VTGA, has been included to minimize coefficients discrepancies. 46

59 To implement the suggested reconfigurable equalizer in CMOS technology, it must be first demonstrated that an active delay approach can be realized at 10-Gb/sec data rate. Passive delay, as demonstrated in Chapter II, utilizes on-chip inductors for the delay line design. Passive delay lines composed of LC delay provides bandwidth that exceeds 10GHz, leaving no bandwidth limitation caused by the delay line itself. As a stepping-stone into realizing a tunable delay, an equalizer with an active delay line is first analyzed, designed, and fabricated. In the following section, the design issues, and design methodologies to overcome such issues are described in detail. 3.2 Settable Equalizer with Active Delay Line The equalizer introduced in section uses passive LC ladder emulating a transmission-line to ensure the broad bandwidth for the delay elements. However, the delay value of the passive delay line cannot be tuned once fabricated and would not be able to reconfigure for optimum equalization for various band-limited channel configurations. In order to verify the feasibility of reconfigurable equalization, first step is to demonstrate possibility of active delay line at 10-Gb/sec data rate as it is more challenging to satisfy the bandwidth requirements for 10-Gb/sec signal compared with its passive counter part. To meet the broad bandwidth requirements for the active delay line, active inductance peaking is considered with a simple differential pair as illustrated in Fig

60 Fig Block diagram of the settable equalizer with active delay line. From Fig. 3.4, the FIR structure also includes a half-sized delay cell at the output of the final delay for matching the capacitive loading. As the high-speed signal passes through each delay cell, the loading affects the design of the VTGA for the tap coefficient adjustment. For symmetry of the design, a matched C loading stage was added. The Unit delay cell is comprised of two identical active delay stages. To improve the bandwidth of each delay while achieving the required RC delay, an active inductance shunt peaking 48

61 technique is adopted [39]. The overall voltage gain for differential pair in unit delay cell is, A v = g m 3 " (Z in //C L ) = sc gs2 R s g m 3 + g m 3 C gs2 C L R s s 2 + (C gs2 + C L )s + g m 2. (3.3) where, the corresponding C L and Z in values can be calculated as follows: C L = C gd 3 (1+ A v ) + C db 3, and Z in = sc gs2 " R s +1 sc gs2 + g m 2 (3.4) The two poles are at, " 1 2 (C + C gs2 L ) ± 1 C gs2 C L R s 2 ( ) 2 " 4g m 2 (3.5) C L R s C gs2 R s C gs2 C L R s and the zero is at 1 R s C gs2. By varying the R s, (R s is turn on resistance of M1 in Fig. 3.4) the zero location can be controlled. Figure 3.5 shows the bandwidth comparison between the active delay line composed of differential pair with passive resistor load and the one with active inductance load. The peaking adjacent to the dominant pole enhances the 3-dB bandwidth of the delay line by approximately 3.9 GHz compared with the delay line with passive 49

62 resistor load. The simulation includes all the parasitic capacitance from the multiplier cell and the adjacent delay cell. With active inductance load With passive resistor load Fig Bandwidth comparison of active delay line with conventional passive load vs. active delay with active inductance load. For the initial active delay line implementation, which will be the foundation for tunable delay line, two cascaded NMOS differential pairs are used generating 33-ps (T s /3) delay per unit delay cell. The effective inductance value, which is proportional to R s /(1/g m2 ), is optimized for 10-Gb/sec NRZ signal transmissions. Figure 3.6(a) and Fig. 3.6(b) shows the simulation and measured result for the designed active delay line. The measurement result shows accurate 33-ps tap delay spacing through the active delay line cells. No apparent slewing occurred on the measurement result demonstrating enough bandwidth for high-speed data throughput. 50

63 (a) Fig Active delay line performance show good agreement between (a) Simulation and (b) measured performance for the targeted Ts/3 tap spacing. (b) 51

64 Figure 3.7(a) and (b) shows the eye diagram of a 10-Gb/sec signal before and after the equalization with active delay line FFE through a 20-in backplane configurations, respectively. Majority of the ISI is removed, providing an eye opening at 10Gb/sec. These initial results demonstrate the feasibility of a tunable delay FFE. (a) Fig Measured performance of the FFE with active delay line with a 10-Gb/sec NRZ data input (a) before and (b) after equalization of a 20-in backplane channel. (b) 52

65 Finally, Fig. 3.8 shows the chip microphotograph of the fabricated FFE with active delay line. The overall chip area is 1.1mm by 0.9mm including the pad area. Total power dissipation of the active delay approach FFE is about 27mW. Without the output buffer, the equalizer core area is 50% smaller compared to the equalizer with passive delay line while the power dissipation is increased from 9mW to 27mW. Fig Microphotograph of the FFE with active delay line approach. The results demonstrated above provide the necessary gateway to implementing the active tunable delay line. In the following section, detailed circuit designs of the building blocks for the reconfigurable equalizer is discussed. 53

66 3.3 Reconfigurable Equalizer Implementation The suggested reconfigurable equalizer IC requires two essential features: tunable tap delay and variable tap gain. Figure 3.9 shows the architecture of the reconfigurable FFE IC. The band-limited channel output signal goes through the tap delay lines. The delay amount determined by system simulations is controlled by the DAC 1-3. Then, these delayed signals are multiplied by the tap weights given by system simulation that is extracted using MMSE algorithm to minimize high-frequency coupling noise. The DAC 4-7 generate the corresponding tap weights being offered to the VTGAs. The resulting amplified signals are combined in current domain. Finally, the output voltage signal swing is obtained with the total current applied to the common load as illustrated in Fig Since this signal processing is performed in the analog domain, the suggested analog equalizer consumes less power and provides broad bandwidth compared to the digital equalization approaches [40, 41]. Fig Reconfigurable FFE block diagram. 54

67 For IC implementation of the reconfigurable equalizer at 10-Gb/sec, both the VTGA and the tunable delay line must have bandwidth in excess of 5GHz, which is the Nyquist frequency for 10-Gb/sec data throughput. For the VTGA, bi-polarity gain control is necessary to provide tap weights ranging from -1 to +1. The actual IC design was performed to have 10% margin in the gain while maintaining the bandwidth above 5GHz. The tunable delay line must have adjustable delay ranging from 25ps up to 50ps. The circuit is designed to cover such delay range over process, voltage and temperature variation. Since the delay amount is sensitive to the parasitic caused by layout artwork, high-speed layout techniques were applied throughout the building blocks. Details on layout art work will be discussed in the following sections. Table 3.1 summarizes the system specifications for the reconfigurable equalizer. TABLE 3.1. SYSTEM SPECIFICATIONS FOR RECONFIGURABLE EQUALIZER. 55

68 From Table 3.1, it must be noted that the input and output common mode voltages are design to be at 1.1V. This is to ensure symmetrical loading towards both VTGAs and tunable delay lines. Since the input transistors for these blocks are NMOS, it is critical to ensure sufficient headroom for the input pair transistors and the current source bias transistor. For broad bandwidth of each building block, input transistor pairs are designed with small device sizes that lead to smaller transistor trans-conductance. To meet the gain requirements, the DC current requires to be more than 10mA that leads to more than 600mV of gate to source voltage drop across the input transistor pairs. These requirements endorse headroom challenge for the current source to remain in saturation region. To provide sufficient headroom for all transistors while ensuring symmetrical signal loading, the input and output common mode voltages were designed and specified to have equal value at 1.1V. In the following section, details on the active tunable delay line are discussed Wide Tuning Range Active Delay Line From the system simulation, tap delay line of the proposed FFE requires 25- ~ 50- ps delay tuning range. A novel active tunable delay line is designed to provide wide tuning range while maintaining bandwidth in excess of 5GHz. For conceptual illustration, a function block diagram is shown in Fig As illustrated in Fig. 3.10, the active tunable delay line is consisted of three active delay stages with a signal path that is connected to both delay cell 1 and delay cell 3. A novel circuit scheme is applied to open passages for these two signal paths that is proportional the control voltage. The novel 56

69 circuit scheme is similar to a mixer stage that can control the passage amount in analogous steps. While digital step delay may seem more conceptually easier to understand the operation, switching noise necessary for such digital step delay and limitation is step size prohibits digital delay approach for 10-Gb/sec applications. The minimum gate delay from a standard 0.18-µm CMOS technology amounts to at least 20ps. In addition, the parasitic capacitance caused by the switches that is necessary for digital delay approach adds undesirable delays resulting is step sizes more than 30ps per step. For 10Gb/sec applications where single symbol period is 100ps, the tunable delay needs to have resolution smaller than 10ps for a reconfigurable equalization to be effective. The analog tunable delay approach provides resolution that is only limited by the resolution of a DAC that is associated with the tunable delay. With a 6-bit DAC, the effective resolution is approximately 3ps. Hence, it is necessary to implement the tunable delay in analog domain. Fig Function block diagram of the active tunable delay line. Figure 3.11 illustrates the schematic of the active tunable delay line. As depicted in the figure, M1~M6 represents the delay cell 1 from Fig Likewise, M7~M12 represents delay cell 2 from Fig. 3.10, and M13~M20 represents delay cell 3 with the 57

70 control unit for dividing the signal path. In order to achieve the required bandwidth, each delay cell is designed with an active inductance peaking loads. For further improvements in the bandwidth over the process, R S from Fig. 3.4 is designed with an active transistor that is forced to operated in linear region controlled by Vb. Transistors M5, M6, M11, M12, M19, and M20 are the transistor that determines the zero location providing inductance peaking the effectively enhances the bandwidth. Fig Schematic of the active tunable delay line. The input signal is connected to both M1-M2 pair and M15-M16 pair forming two delay paths that is consisted of either only the delay cell 3 (M15-M16) or all of the delay cell 1 through 3 (M1-M2, M7-M8, and M13-M14). The transistor size of M13-M14 pair need not be equivalent to that of M The amount of signal distribution between these two delay paths is determined by the control voltage applied to Vcont+ and Vcont-. These two delay paths form the slow path and the fast path. The fast path is designed to 58

71 provide minimum gate delay that can be achieved from the given process technology. On the other hand, the slow path is designed to provide the longest desirable delay the specific application is seeking. The trade-off is between total tuning range against the achievable bandwidth, as the delay is essentially achieved via RC delay of the dominant pole from each differential stages. SPICE simulation illustrated in Fig demonstrates the transition between the fast path to the slow path. Due to the current steering act between M13-M14 and M15-M16 transistor pairs, the slope of the output signal is falling as the control voltage is increased. Delay Increase Fig Simulation result of the active tunable delay line illustrating transition from fast path to slow path. 59

72 Fig summarizes the delay amount versus the corresponding control voltage. The overall tuning range can be increased at the cost of reduced bandwidth. The simulation result shown in Fig is the tunable delay with 7GHz of -3dB bandwidth, as shown in Fig 3.14, which is well beyond the required specification. The linearity of the tuning control is also a tradeoff against maximum bandwidth. As the linearity can be improved with a source degeneration in the delay cell 3, the addition of the source degeneration cuts off the headroom at the last stage requiring to reduce the total current. As a chain of result, the overall linearity is improved at the cost of bandwidth. In this design, the focus was made on achieving maximum bandwidth for implementing a 10-Gb/sec tunable delay in a 0.18-µm CMOS technology. Figure 3.15 depicts the transient response of a reconfigurable equalizer through three active tunable delays with 25ps tap spacing Delay Time [ps] Control Voltage [V] Fig Delay time versus corresponding control voltage. 60

73 Fig AC simulation of the active tunable delay line demonstrating 7GHz of -3dB bandwidth. Fig Transient response of a reconfigurable equalizer through three active tunable delays with 25ps tap spacing. 61

74 To digitally control the active tunable delay line, a modular DAC is designed and integrated to provide the control voltage to the tunable active delay line and the VTGAs. The modular DAC architecture is based on the R-2R ladder network [42]. However, the design is modified to consist of bit-modules, as illustrated in Fig This approach provides flexibility to the DAC resolution such that the desired number of bits can be designed by simply adding or deleting the standardized bit-modules. This design approach has been also applied to the layout artwork. Furthermore, this R-2R-based modular DAC uses ratios of single value standardized poly resistors, where these ratios can be highly tolerant over process variation especially with inter-digitated layout and added dummy resistors. An 8-bit modular DAC is shown as an example in Fig Fig Bit-module-based 8-bit DAC with modified R-2R topology 62

75 Meanwhile, the error performance of the DAC is critical for accurate equalizercontrol. The NMOS switches with large (W/L) ratio were adopted to minimize the offset error due to V DS voltage drop across the M1 and M2 switches [43, 44]. Moreover, in order to improve matching and minimize offset, adjacent bit input unit cells were placed further apart from each other in the layout. As a performance measure, offset error defined as the deviation from ideal value is monitored. Over all process corners, supply voltage and temperature variations, the DAC performed within less than 10% of the least significant bit offset across all cases. A 6-bit modular DAC was integrated with the active tunable delay, as illustrated in Fig This 6-bit DAC successfully controlled the active tunable delay and provided linear control over the tuning range. A separate DC output of the 6-bit modular DAC is shown in Fig Fig Chip microphotograph of a 6-bit modular DAC integrated with an active tunable delay. 63

76 Effective Control Range for Tunable Delay Fig Modular 6-bit DAC DC output reading. Finally, the measurement result from the IC illustrated in Fig 3.17 is shown in Fig This result shows tunable delay performance for the designed active delay line. Wide tuning range is achieved from 15ps (fast delay path) up to 83ps (slow delay path) from the DAC input of 18 up to 43. This corresponds to the control voltage from 0.5 volts to 1.2volts. The designed modular 6-bit DAC provides linear output steps from 0V to 1.8V. Since the active tunable delay takes control voltage from 0.5V to 1.2V, the effective tuning resolution is approximately 3ps. Figure 3.19 illustrates linear control of the tunable delay for up to 83ps. Total five point of interest are overlaid on the oscilloscope screen demonstrating the digital controlled tuning with linear tap spacing achieved. 64

77 Fig Measurement results of the digitally controlled active tunable delay with 3-ps effective tuning resolution Variable Tap Gain Amplifier As summarized in Table 3.1, the VTGA needs to provide bi-polarity gain from -1 to +1. Conventionally, a Gilbert cell architecture is used as a multiplier cell for such purposes [45, 46]. The major function for the multiplier cell is to adjust the amplitude of the signal, which comes after the delay line cell. The most simple way for the gain variation is to control the bias current in the simple differential pair as shown in Fig. 3.20(a). The gain is proportional to the square root of a bias current from the small signal gain calculation. The current sink control method is simple to implement, however it still 65

78 has undesirable characteristics such as the output common mode voltage variation depending on the gain. The other gain variation technique is to vary the degeneration resistor as shown in Fig. 3.20(b). The voltage gain for the source degenerated differential pair is, g m 1+ g m R s R d (3.6) where, g m is the trans-conductance of the negative metal oxide semiconductor (NMOS), R s is the degeneration resistance, and R d is the load resistance. By changing the R s, the overall voltage gain can be varied without changing the common mode output voltage. The variable resistor can be implemented by using on-resistance of the MOS. The bias condition for the MOS to be used as a variable resistance is when the MOS operates in triode region (i.e. V ds > V gs - V t, where V ds is the drain-source voltage and V t is the threshold voltage for the MOS). The on-resistance of the MOS is as follow: R on = 1 µ n C ox W L (V gs "V t ) (3.7) where, µ n is the mobility of the electrons, C ox is the gate oxide capacitance per unit area, W is the MOS width and L is the MOS channel length. By summary, the gain variation can be implemented by way of changing the bias current, degeneration resistance, or load resistance. However those methods are still not 66

79 appropriate to be used for the VTGA in a reconfigurable equalizers because the multiplier cell needs bi-polar gain variation. (a) Figure Gain variation for differential pair. (a) Differential pair with current sink variation. (b) Differential pair with source degeneration variation. (b) Therefore it is good idea to exploit the advantage of differential signaling, for example, the bi-polar gain is achievable by swapping the connection of differential pair. 67

80 Figure 3.21 shows the two differential pair tied together at their drain with opposite signal polarity. This is called Gilbert cell. The bi-polar gain variation characteristic of the Gilbert cell makes it as a good candidate for analog multiplier cell. By this reason, the conventional Gilbert cell is considered as the multiplier cell for this equalizer design. For high-speed circuit operation, passive loads are chosen over active loads as current summation node. However, despite the bandwidth advantage of the passive resistance loads, the open drain connection of the conventional Gilbert-multiplier cells to the resistive load results in a voltage drop across the passive load that increases linearly as the number of tap is increased (i.e. increased number of multiplier cell connection to the resistive load). This forces the transistors (M1, M2, M3 and M4) in Fig to operate in the triode region. Fig Conventional Gilbert cell topology. The proposed FFE has four VTGAs connected to the common load. Each amplifier flows DC current, resulting in four times the DC current flow through the 50-68

81 ohm resistor. This phenomenon induces the voltage headroom issue. In order to ensure proper voltage headroom for each VTGA, conventional Gilbert-cell is modified with a current steering bias scheme. Instead of applying control voltage directly to the differential pair below the common source, control voltages, Vcon+ and Vcon-, are applied to M5 and M6 to provide the bias currents proportional to the control input [47, 48]. In other words, the modified cell architecture uses folded gain control circuit with the bias current block folded effectively reducing the number of stacked devices, as shown in Fig With the current mirrors of M10-M15, this creates the current steering control delegating the gain control to the PMOS input pairs. This modified architecture reduces total number of stacked devices resulting in alleviated headroom condition. Fig Modified Gilbert cell-based VTGA with folded gain control block. 69

82 Meanwhile, the mirror pole capacitance at the AC ground node resulting from the proposed cell has negligible effect on the overall bandwidth performance since the gain control signal path does not require the high bandwidth. In addition, both linearity and voltage headroom are enhanced by applying an active degeneration scheme between divided common source branches. The ML transistor pairs represent such active degeneration with M7, M8, and M10 ~ M13 being the divided current sources [49, 50]. The gain control block also includes a degeneration circuit (ML) for linear gain control. Figure 3.23 shows the overall VTGA performance with gain changing from 1 to +1. Input and output dynamic range of 300-mVpp was achieved, while assuring wide linear range. Finally, the bandwidth performance of the VTGA is shown in Fig It is illustrated over different control voltage settings showing bandwidth and gain relationship. The bandwidth of the proposed VTGA is maintained over 7 GHz across the gain value that is enough for 10-Gb/sec data transmission. Fig DC gain curve of the VTGA cell showing dynamic range and linearity. 70

83 Fig Bandwidth performance of the VTGA in excess of 7GHz across various gain settings. As illustrated in Fig. 3.2, four VTGAs are sharing common load for summation of the analog processing output in the current domain. In other words, four of the VTGAs open drains are all connected together forming a dominant pole resulting in a major bandwidth limitation at this node. Hence, despite the excessive bandwidth achieved for the individual VTGA blocks, it is absolutely necessary to reduce any parasitic capacitance that may deteriorate the bandwidth of the overall reconfigurable equalizer. In order to minimize the parasitic capacitance, both the active tunable delay line and the VTGA were laid out with minimum trace length and maximum source sharing. Figure 3.25 illustrates the 4-tap reconfigurable FFE layout artwork, where each tunable delay line and VTGA perfectly abuts in all signal paths minimizing the signal trace length while reducing any unnecessary parasitic capacitances. Differential signal paths are never 71

84 crossed over the other. Poly contacts are removed leaving the only necessary number to further reduce parasitic caps. Also, all high-speed data paths do not go over any adjacent metal layer minimizing coupling parasitic capacitances. Fig Illustration of the layout artwork with minimized parasitic capacitance and symmetric data paths to improve the reconfigurable FFE performance. 72

85 3.4. Reconfigurable Equalizer Measurement Results In the previous sections, system overview and requirements for the reconfigurable equalizer was introduced in detail. In addition, critical building blocks for the reconfigurable equalizer implementation was demonstrated with its performance both in simulations and measurements. The main purpose of the reconfigurable equalizer is to further improve the BER by offering flexibility in tap spacing. With finite number of taps due to bandwidth limitations for a realistic implementation, the reconfigurable equalizers provide adjustable tap spacing allowing optimal channel compensation for the given process technology. Figure 3.26 illustrates the measurement setup that is composed of a 10-GHz BERT, variable length backplane with two daughter cards, the reconfigurable equalizer CMOS IC on the probe station, and a 20-GHz digital sampling oscilloscope (DSO). Figure 3.27 shows the corresponding physical setup. Fig The reconfigurable equalizer performance measurement setup over 8-in and 20-in backplane trace lengths. 73

86 Fig Photo capture of the corresponding measurement setup. For the fabrication of the equalizer, a standard 0.18-µm CMOS technology was used. This process has typical threshold voltage of 450 mv and a cut-off frequency of 40GHz. The bandwidth of the proposed equalizer is shown in Fig. 13. As can be seen from Fig. 13, the overall bandwidth is affected by four VTGAs as the primary load, and the serial data path limited by the three series of tunable delay. The solid line shows bandwidth through all four taps, while the dashed line shows bandwidth only through the first tap. The proposed equalizer is showing an ample 5.4-GHz overall bandwidth through all cases that is slightly higher than the Nyquist frequency of 5-GHz for 10-Gb/sec data communications. Figure 3.29 illustrates the bandwidth of the reconfigurable equalizer with a 10-Gb/sec PRBS 2^-31 NRZ signal thought the equalizer output. As can be clearly 74

87 seen from the figure, the fabricated equalizer has sufficient bandwidth for 10-Gb/sec data throughput. Fig Bandwidth of the reconfigurable equalizer. Fig Bandwidth test with a 10-Gb/sec PRBS 2^31 NRZ data passing through one tunable delay and one VTGA. 75

88 To demonstrate the reconfiguration option of the equalizer, the same equalizer is used to compensate for 8-in and 20-in backplane trace lengths. As illustrated in Fig. 3.27, the measurement setup with pluggable daughter cards that can vary the overall trace lengths is used. In detail, the HP70843B Error Performance Analyzer and the HP70340A Signal Generator was used to generate 10-Gb/sec pseudo-random bit sequences. After the reconfigurable FFE mounted on a probe station, an Agilent 86100A wide-bandwidth digital sampling oscilloscope is used to measure the output. For probing, DC probe with 7 signals and two GSSG probes with pitch of 150µm were used. First, the 8-in backplane trace length is measured. With 10-Gb/sec PRBS 2^-31 NRZ input signal, the output is severely degraded and the data cannot be recovered as illustrated in Fig Equalization is definitely needed for data recovery. Fig Output after 8-in backplane with 10-Gb/sec PRBS 2^-31 NRZ. 76

89 Meanwhile, the reconfigurable equalizer is set up with Tau/2 (50ps) tap spacing for initial trial. The output result with the same 10-Gb/sec PRBS 2^-31 NRZ applied is illustrated in Fig As the tap spacing is too wide to compensate for the channel, although the ISI is somewhat removed, the eye-diagram is not fully opened, and the BER is hitting close to Fig Output after 8-in backplane with 10-Gb/sec PRBS 2^-31 NRZ with tap spacing is set to Tau/2 (τ=50ps). Had the equalizer been a settable equalizer, where the tap spacing is fixed and only the tap weights are adjustable, with tap spacing fixed to 50ps, that equalizer would not been able to fully compensate for the given 8-in backplane channel link. In fact, halfsymbol period tap spacing is a popular number for many analog continuous-time filter equalizers [51, 52]. 77

90 With the tap spacing adjusted to Tau/3 (33ps), the tap weights are newly applied and the resulting eye diagram is illustrated in Fig. 3.32(a). The output after 8-in backplane with 10-Gb/sec PRBS 2^-31 NRZ signal is now recoverable. The tap weights are further narrowed down to Tau/4 (25ps) in Fig. 3.32(b). (a) (b) Fig Output after 8-in backplane with 10-Gb/sec PRBS 2^-31 NRZ with tap spacing is set to (a) Tau/3 (τ=33ps) and (b) Tau/4 (τ=25ps). 78

91 From these figures, the latter result provides lower BER with wider open eyediagram. The deterministic jitter performance also improved from 44ps down to 31ps. These results indicate for the given 8-in backplane trace, narrower tap spacing can more effectively compensate for the given channel. These series of measurement demonstrates how a reconfigurable equalizer can further improve the signal integrity for given fabricated equalizers. A new set of measurements was taken over a 20-in backplane trace length, where the loss is significantly larger due to band limitation. Figure 3.33 illustrates the output after 20-in backplane with 10-Gb/sec PRBS 2^-31 NRZ signal applied at the other end of the backplane. The output signal is completely closed due to severe ISI where no data information can be retrieved. Fig Output after 20-in backplane with 10-Gb/sec PRBS 2^-31 NRZ with tap spacing is set to Tau/2 (τ=50ps). 79

92 Figure 3.34(a) shows the eye-diagram after equalization using 4 taps and Tau/2 (50ps) delay. The ISI is somewhat removed, but not enough to fully open the eye for data information retrieval. This result suggests that smaller tap spacing is needed. Figure 3.34(b) is the output with Tau/3 (33ps) tap spacing. (a) Fig Output after 8-in backplane with 10-Gb/sec PRBS 2^-31 NRZ with tap spacing is set to (a) Tau/3 (τ=33ps) and (b) Tau/4 (τ=25ps). (b) 80

93 As the tap weights are correctly applied, the eye is open and the signal can now be recovered. The deterministic jitter is less than 40ps and the equalization is successful over 20-in of backplane trace length with Tau/3 and 4 tap FFE. From these measurement results, it is demonstrated the optimum equalization can be achieve with adjustable tap spacing. Furthermore, the signal integrity can be improved by lowering the BER for given equalization. Finally, the chip microphotograph is presented in Fig The overall chip dimension is 1.24mm x 0.98mm including the pad area. The total power consumption is 195mW with 1.8V power supply. Fig Chip microphotograph of the reconfigurable equalizer IC. 81

94 In this chapter, system overview and system requirements of a reconfigurable equalizer was introduce. In addition, detailed implementation issues and solutions for CMOS circuit design was discussed. Finally, demonstration with measurement results were presented and illustrated the concept and operation of the reconfigurable equalizers. In the next chapter, a novel method to monitor the output of the equalizer is introduced. With the output monitoring data, it is possible to calibrate the equalizer to compensate for the channel variation over longer period of time. This monitoring technique can be the basic foundation for implementing a fully adaptive equalizer. 82

95 CHAPTER IV. TRANSITION DETECTOR-BASED OUTPUT MONITORING In Chapter III, a universal channel compensation solution is presented with a reconfigurable equalizer using active tunable delay line. Channel output monitoring is desirable to provide the appropriate adjustment for the reconfigurable channel compensation solutions. Previously, eye-monitoring schemes were suggested for channel output monitoring [53, 54]. However, this approach requires 10-Gb/sec comparators that can be challenging for certain processes. Therefore, a new approach for channel output monitoring is proposed that can achieve 10-Gb/sec data rate and is easy to integrate with the reconfigurable FFE. In this work, a transition detector-based output monitoring (TD- OM) technique is suggested for channel output monitoring to adjust the tap-coefficients for optimal performance. Since the channel transfer function is not changing in real-time, the proposed TD-OM technique employs a simple architecture for lower power consumption while achieving the targeted data throughput. This output monitoring technique does not require clock and data recovery circuitry resulting in reduced complexity for easier circuit implementation. To determine the equalization amount for reconfiguration of the system, it is necessary to know how well the FFE is performing. This can be achieved by measuring how much the output signal of the FFE has been dispersed. As detailed in Chapter II, the 83

96 dispersion of the signal is mainly caused by the high-frequency component loss through the band-limited channel. This, then, causes ISI and closes the eye. Since the amount of the high frequency components is proportional to the amount of the fast transitions, the performance of the FFE can be measured by measuring the amount of the fast transitions. The loss of high-frequency components makes the fast transitions of the signal, such as the edge of the square pulse, smoother and widened. In other words, the integrity of the received signal is improved as the high-frequency components of the transmitted signal experience less loss, letting more fast transitions of the signal occur. Figure 4.1 illustrates the functional block diagram of the TD-OM blocks integrated with the reconfigurable equalizer discussed in Chapter IV. As depicted in Fig. 4.1, the TD-OM is composed of two different delay length paths, a subtractor, a squarer, and an integrator. Fig Functional block diagram of the novel transition detector-based output monitoring blocks integrated with the reconfigurable equalizer. 84

97 The transition signal can be detected by subtracting two delayed equalizer outputs. One path is delayed by τ and the other path is delayed by multiples of τ s depending on the data rate. The differences of two delayed signals for the transmitted signal can be interpreted as the transition detector, as illustrated in Fig This difference will be squared and integrated over a certain period of time to generate a DC value that is proportional to the amount of transition detected. In other words, the amount of transition detected can be used as a figure of merit to assess the quality of the eye. This DC information enables reconfiguration of the FFE for optimal equalization, with the optimizing algorithm implemented digitally. The overall system block diagram for this functionality is summarized in Fig Fig Conceptual illustration of transition detector. 85

98 As illustrated in the functional block diagram of Fig. 4.1, the transition detector block constantly monitors the equalized signal. To minimize the loading effect on the FFE output and maintain the bandwidth of the signal path, it is critical that the output sampling is performed with minimum gate size. Since the gate size of the summing circuit in Fig. 4.3 is larger than that of the delay circuit, an identical fixed delay block with minimum gate size is duplicated on both signal paths. The fixed delay block must provide more than 10 GHz of bandwidth for accurate sampling of the channel output. Figure 4.3 depicts the fixed-delay schematic that incorporates active inductance peaking for maximum bandwidth [55, 56, 57]. Each delay block produces about 20-ps latency. Fig Schematic of the proposed fixed active delay line. 86

99 Fixed-delay blocks are cascaded for transition amount control. Depending on the total delay from the second signal path, the total amount of overlap between the two signals varies. This overlap amount determines detected transition amount providing flexibility for various data rates. For complete operation of the transition detector between two differential signals, subtraction of the signals is needed. This subtracted waveform is converted to an absolute value for the integrator. Usually implementing those functions requires many transistors, resulting in degradation of high frequency performance due to parasitic capacitances of MOS transistors. Thus, implementing this with a simple architecture that requires small number of devices is critical. In this work, the error-detection and squaring functions are achieved at the same time by making use of a differential pair and the square relation between the gate voltages and drain current of the NMOS transistor. When two input signals are applied into the gate and the source of MOS transistor, the subtraction and squaring can be realized without additional components. Due to the inherent square law of the MOS transistor drain current in the saturation region, as expressed below, these two functions can be implemented using one circuit [58, 59]. General MOS transistor s square law is shown below. I DS = 1 2 K n ( W L )(V GS " V T ) 2 where, K n = µ 0 C ox. (4.1) The squaring circuit of difference of two differential inputs V1 and V2 are shown in Fig 4.4. Transistors M1, M2 act as the source followers and M3, M4 are squaring block. The aspect ratio of M1, M2 is much larger than that of M3, M4. All transistors are 87

100 operating in the saturation region. At node A and B, V2 is applied to the sources of M1 and M2 with a constant voltage drop. Assume Vs is the common-mode dc voltage for two inputs, voltages at node A and B are: V S " V 1 2 " V GS1 and V S + V 1 2 " V GS 2 (4.2) respectively. Output current (I SQ ) is given by where, I S1 = 1 2 K " W n$ # L I SQ = I S1 + I S 2 (4.2) % ' V S ( V 2 & 3 2 ( V ( V 2 )" " 1 $ S 2 ( V % %, + $ GS1 '( V T '. * + # # & & -. (4.3) I S 2 = 1 2 K " W n$ # L % ' V S + V 2 & 3 2 ( V S + V 2 )" " 1 $ 2 ( V % %, + $ GS 2 '( V T '. * + # # & & -. (4.4) and V GS1 = V GS 2 = K n 2I SF " $ # W L % ' & 1 + V T (4.5) ISF is the bias current of the source follower and given by I SF = " $ # W L " W % $ ' # L & 1 % " ' + $ W & 1 # L ( I % A. (4.6) ' & 2 88

101 Substituting I SF into V GS1 and V GS2, I SQ will be I SQ = 1 4 K " W n$ # L % ' & 3 ( V 1 ( V 2 ) 2 + I DSQ (4.7) " W % $ ' # L & I DSQ = 2 " W % $ ' # L & 3 1 ( I SF (4.8) The output current I SQ is the square of the difference between two input signals. Fig Schematic of the proposed subtract-and-square circuit. 89

102 Figure 4.5 demonstrates the operation of the transition detector-based outputmonitoring concept. When the output is un-equalized, the detected transition amount is relatively small compared to when the output signal is equalized. By integrating this detected transition, it is possible to monitor the status of the equalizer s output. Fig Transition detection simulation. With more transition (i.e. more open eyediagram), the overall output power is higher, resulting is higher DC level when squared and integrated. Since the transition data is the subtraction between the original signal and delayed signal, it is a high frequency signal. Therefore, the integrator requires a very high bandwidth. A conventional integrator with an op amp and switched capacitor cannot meet this requirement. Hence, in this work, an analog power integrator is implemented with charge-pump architecture as shown in Fig

103 The proposed charge pump consists of two current sources: one for sourcing and the other for sinking currents. When the UP signal is active, source currents flow into M5. The gate-channel capacitance of the PMOS transistor acts as a hold capacitor. As a result, the output voltage rises. If the DOWN signal is active, source currents flow out of M5. Normally a charge pump charges up and down as described. However, for this application, only charging up is needed for dc value. As shown in Fig. 4.6 the charge pump is modified to have only charge up at the output. To reset the dc value, an external control voltage is periodically applied to control the switch operation at M2 and reset the integrated value. When B is high, transistor M2 is on and all the charge will go to the ground. Fig Schematic of a charge pump-based integrator. 91

104 Figure 4.7 illustrates the simulated operation of the proposed charge-pump based integrator [60, 61, 62]. With un-equalized input coming in, the integrator output increases slowly over time. Whereas, when the input signal is equalized, the integrator receives more transition signals resulting in faster integrated output. This DC value is used at a digital control block illustrated in Fig. 5 for optimal control based on the output monitor status. Fig Simulation results of a charge pump-based integrator. Figure 4.8 is the simulation results that demonstrate the transition detector-based output monitoring technique. The first waveform is the transmitted data. After passing through a band-limited channel, the received data is severely degraded. The reconfigurable FFE restores the signal as shown in the third waveform. The fourth waveform is a fixed-delayed waveform. Finally, the subtract-and-square circuit is able to 92

105 take the difference and square the signal resulting in a positive signal ready for integration. As was illustrated in Fig. 4.7, the output of the integrator provides a DC signal that is proportional to the transition amount. This DC signal can be used for optimizing the equalizer tap coefficients. Fig Simulation results that demonstrate the proposed transition detector-based output monitoring technique. In this chapter, a novel transition detection-based output monitoring technique is discussed. This TD-OM can be integrated with the reconfigurable equalizer for compensating various band-limited channels providing a universal channel compensation solution. The feasibility is demonstrated for this new output monitoring technique that 93

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