DIGITAL ELECTRONICS GATE FUNDUMENTALS

Transcription

1 AM DIGITAL ELECTRONICS GATE FUNDUMENTALS September 2012 DISTRIBUTION RESTRICTION: Approved for public release. Distribution is unlimited. DEPARTMENT OF THE ARMY MILITARY AUXILIARY RADIO SYSTEM FORT HUACHUCA ARIZONA

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3 CHANGE PAGE LIST OF EFFECTIVE PAGES INSERT LATEST CHANGED PAGES. DISTROY SUPERSEDED PAGES NOTE The portion of this text affected by the changes is indicated by a vertical line in the outer margins of the page. Changes to illustrations are indicated by shaded or screened areas or by miniature pointing hands. Changes of issue for original and changed pages are: ORIGIONAL..0. Page NO. Change No. Title Page NO. Change No. Page No. Change No. *Zero in this column indicates an original page A Change 0 US Army 2. RETAIN THIS NOTICE AND INSERT BEFORE TABLE OF CONTENTS. 3. Holders of this document will verify that page changes and additions indicated above have been entered. This notice page will be retained as a check sheet. This issuance, together with appended pages, is a separate publication. Each notice is to be retained by the stocking points until the standard is completely revised of canceled Ver 0 a

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5 CONTENTS 1 INTRODUCTION: DIGITAL CIRCUIT SYMBOLS: RESISTOR, DIODE LOGIC GATES: Resistor-Resistor Logic: Diode logic: GATE FAN IN AND FAN OUT: Fan In: Fan Out: DIP PIN IDENTIFICATION: TTL (TRANSISTOR - TRANSISTOR) LOGIC: BASIC TTL LOGIC AND FUNCTIONS: COMMON GATES: AND Gates: OR Function: NOT Function: NAND and NOR gates Exclusive OR Function: BASIC NAND TTL Operation: COMMON TTL LOGIC: Input/output logic levels for TTL: TRANSISTOR SWITCHING THEORY: INTRODUCTION: OPERATING POINTS: TRI-STATE LOGIC MIMIC A LOGIC FUNCTION CONSTRUCTING THE INVERT FUNCTION: CONSTRUCTING THE "BUFFER" FUNCTION: CONSTRUCTING THE AND FUNCTION: CONSTRUCTING THE NAND FUNCTION: CONSTRUCTING THE OR FUNCTION: CONSTRUCTING THE NOR FUNCTION: Ver 0 i

6 AM 5-401, Basic Digital Circuits PREFACE Improvements Suggested corrections, or changes to this document, should be submitted through your State Director to the Regional Director. Any Changes will be made by the National documentation team. Distribution Distribution is unlimited. Versions The Versions are designated in the footer of each page if no version number is designated the version is considered to be 1.0 or the original issue. Documents may have pages with different versions designated; if so verify the versions on the Change Page at the beginning of each document. REFERENCES Allied Communications Publications (ACP): 4. ACP Communications Instruction, General 5. ACP Radiotelegraph Procedures 6. ACP Radiotelephone Procedures 7. ACP Communications Instructions Radio Teletypewriter 8. ACP Communications Instructions Operating Signals DOD Instructions 1. DOD Instruction US Army Documents US Army Regulations 1. AR Military Auxiliary Radio System (MARS) and Amateur Radio Program US Army FM/TM Manuals 1. FM Tactical Radio Operations 2. TM Electrical Design, Lightning and Static Electricity Protection US Army MARS 1. AM US Army MARS Net Plan Commercial References 1. Basic Electronics, Components, Devices and Circuits; ISBN X, By William P Hand and Gerald Williams Contributors This document has been produced by the Army MARS Technical Writing Team under the authority of Army MARS HQ, Ft Huachuca, AZ. The following individuals are subject matter experts who made significant contributions to this document. William P Hand Ver. 1.0 ii

7 1 INTRODUCTION: There are several types of logic circuits such as RTL, TTL etc. Along with this the Logic itself can either be Positive, where the active signal is a positive pulse, Negative, where the active is signal is a negative pulse. There are others such as NRZ (Non Return to Zero) where the signal is either a positive or a negative pulse and the signal in never a zero voltage. 1.1 DIGITAL CIRCUIT SYMBOLS: Generally a digital circuit is drawn with digital symbols rather than a schematic circuit. This will simplify the circuit diagram but since most digital, logic is available in integrated circuit packages rather that discrete component circuits. They symbols used for each common type of digital circuit are shown in Appendix RESISTOR, DIODE LOGIC GATES: One of the first logic gate circuits was the Resistor gate. It is a very simple circuit bur does consume power and the circuit does decrease the level of the signal, thus requiring amplifiers. It is very unusual to encounter circuits of this type; however they are very useful when simple quick constructed type gates are needed for temporary testing RESISTOR-RESISTOR LOGIC: A resistor logic gate such as that shown in Figure 1-1 utilizes a resistor network for the summation or subtraction of the various input voltages. The circuit can be power hungry in order to keep up the output signal. The circuit can be improved by adding a transistor follower. A B Y Figure 1-1 Resistor-Resistor OR Ver 0 1-1

8 1.2.2 DIODE LOGIC: A diode logic gate such as that shown in Figure 1-2 utilizes diodes in the summation circuit, thus network for the summation or subtraction of the various input voltages. The circuit can be improved by adding a transistor follower. 1.3 GATE FAN IN AND FAN OUT: FAN IN: Figure 1-2 Diode/Diode Logic Fan in is defined as the amount of input current a driven gate loads a driving gate. Knowledge of the input characteristics of a TIL gate is necessary to utilize these devices. An input parameter that must be specified is the input current for the logic 1 state. When both inputs of a TTL gate are at a logic 1, the emitter base junctions of Q1 (Reference Figure 1-3) are reverse biased and the collector-base junction is forward biased. Input current is a function of the leakage current of Q1. When reverse biased, the transistor operates in region 4. The emitter acts like the collector and the collector becomes the emitter. Current flow from the emitter to collector, therefore, determines the logic 1 load current in an input terminal. Each input of a multiple-emitter TTL gate represents a unit load (V.L.) of 1 at an input current of 40 µa, or less, at a voltage of 2.4 V for logic 1. For a logic 0 (zero), the emitter current is 1.6 ma FAN OUT: Fan out is defined as the output current a gate can deliver in logic 0 or 1 states. In logic 1 state, the driving gate must source current to the load; in logic 0 (zero) state, the driving gate must sink current from the load. If a gate input has a unit load of 1, the driving gate must source 40 µa in logic 1 state and 1.6 ma in logic 0 (zero) state. Ver

9 Figure 1-3 Circuit Diagram of a Standard TTL 2 Input NAND Gate For example, the loading imposed by the input of a gate is specified as 2 unit loads. The device that can drive 10 unit loads could then be loaded with up to five of these 2 unit load inputs, with ten of 1 unit load inputs, or with any other combination that keeps the total loading at 10 unit loads or less. 1.4 DIP PIN IDENTIFICATION: For 14 pin DIP packages, pin 7 is usually connected to ground (Gnd), and pin 14 is usually 1 connected to the 5V power supply (V CC ). These connections must be made or the chip will not work. While TTL circuits are fairly forgiving, they can be destroyed by wiring mistakes. Take care not to connect pin 7 to power and pin 14 to ground, or to connect the outputs of two or more gates together. Figure 1-4 Identifying Pins Only open collector and Tri-state gates are designed to operate with outputs of several gates connected together, and even in these cases, care must be taken. A complete logic diagram including pin numbers using the 7408 chip can be drawn as is done in either of Figure 3-5 Ver 0 1-3

10 Figure 3-5 Logic Diagram Showing Pin Numbers NOTE: TTL logic circuits are not passive! Ver

11 2 TTL (TRANSISTOR - TRANSISTOR) LOGIC: 2.1 BASIC TTL LOGIC AND FUNCTIONS: The basic logic functions and operations are the AND, OR, and the NOT (Invert) functions A positive AND function is shown in Figure 1-1, the AND function is a logic 1 if all logic inputs are 1s. 2.2 COMMON GATES: AND GATES: Figure 1-1 Logic AND Common TTL AND Gates, as shown in Figure 1-2, such as a 54/7408 series is easy to understand. It is called AND because the output of this gate will only be a 1 if and only if ALL inputs have a 1 applied. If any input is a 0 the output will be a 0. Figure 1-2 Typical AND Gates NOTE An AND gate can have many inputs but commonly, there are not over 4 inputs per gate. In the following circuit, with the 3-input AND gate subjected to all possibilities of input logic levels. An LED (Light-Emitting Diode) provides visual indication of the output logic level: Ver 0 2-1

12 A B C Figure 1-3 Inputs that Give NO Output Figure 1-4 Input that Gives an Output It is only with all inputs raised to "high" logic levels that the AND gate's output goes "high," thus energizing the LED for only one out of the four input combination states. Ver

13 2.2.2 OR FUNCTION: The OR function is logic 1 if at least one of the inputs is logic 1. For two inputs, A and B, Y = A + B can be represented by the truth table in Figure 1-4. The truth table shows that output Y is logic 1 when one, or both, inputs are logic 1. Figure 1-4 Logic OR NOT FUNCTION: For the NOT function (Figure 1-5), if the input is a logic 1, the output is a logic 0, and vice versa. Figure 1-5 Logic NOT Ver 0 2-3

14 2.2.4 NAND AND NOR GATES. The truth tables and logic symbol for these gates are provided in Figure 1-6. In the NAND gate, for two inputs A and B, output Y is a 1 only if one or both inputs are logic O. If A = B = 1, output Y = O. Referring to the truth table of the NOR gate, we find that output Y = 1 only when both inputs are logic Os. If one or both inputs are at a logic 1, output Y = O. Figure 1-6 NAND and NOR Logic EXCLUSIVE OR FUNCTION: Another gate that is used is the exclusive-or of Figure 1-7 Referring to its truth table, Y = 1 only if either A, or B, is a 1. If both inputs are the same (0 or 1), Y = O. A B Y Figure 1-7 Exclusive OR Logic Ver

15 2.2.6 BASIC NAND TTL OPERATION: Operation of the standard TTL NAND gate, reference Figure 1-8, all inputs must be logic 1 in order to obtain a logic O out. Any logic 0 input produces logic 1 at the output. The TTL voltage threshold for logic 0 is defined as 0.6 V maximum, and for logic 1 it is 1.3 V minimum. Figure 1-8 Typical NAND Gate Circuit If the voltage at input emitter A or B of the multiple-emitter transistor Q1 is less than 0.6 V (logic 0), transistors Q1and Q3 are turned off. This causes transistor Q4 to conduct, resulting in logic 1 output. The logic 1 output voltage level is related to the forward voltage drop across diode D, the base-emitter voltage of Q4, and the current supplied to the load, which results in a voltage drop across R4' Subtracting these items from V cc, which is typically 5 V, defines the logic 1 output voltage. Transistors Q3 and Q4 constitute a totem-pole output stage. When voltages at inputs A and B are greater than 1.3 V (logic 1), transistors Q2 and Q3 conduct, Q4 is off, and output is at logic O. The logic 0 output voltage is determined by the amount of current Q3 must sink from the load and saturation resistance of Q3 In practice, a guaranteed maximum voltage of 0.4 V is specified while sinking 16 ma of current. 2.3 COMMON TTL LOGIC: The most common application for a logic gate is to drive another similar logic gate. The input and output logic levels, therefore, must be compatible. Listed in Table 1.2 are typical input/output logic levels for Series 54/74 TTL. The circuit designer must distinguish the different load characteristics of various circuits. Ver 0 2-5

16 Table 1-1 A Partial List of Common TTL Chips Circuit P/N Quad 2-input NAND gate 54/7400 Quad 2-input NOR gate 54/7402 Quad 2-input AND gate 54/7408 Triple 3-input NOR gate 54/7427 Quad 2-input OR gate 54/7432 BCD/decimal decoder/driver 54/7445 JK flip flop 54/ bit binary full adder 54/7483 Decade counter 54/ bit shift register 54/ INPUT/OUTPUT LOGIC LEVELS FOR TTL: 1. V1L The maximum voltage level for a logic 0 at an input. Its guaranteed maximum is 0.8 V. 2. VIR The minimum voltage level for a logic 1 at an input. Its guaranteed minimum is 2.0 V. 3. VOL The maximum voltage level for a logic 0 at an output. Its guaranteed maximum is 0.4 V. 4. V OH The minimum voltage level for a logic 1 at an output. Its guaranteed minimum is 2.4 V. Ver

17 3 TRANSISTOR SWITCHING THEORY: 3.1 INTRODUCTION: Transistor switching times are a very fickle thing. There are three basic circuits as noted in other documents: 1. Common Emitter (CE) 2. Common Base (CB) 3. Common Collector(CC) These three transistor switch configurations, as seen in Figure 3-1, shows the three transistor circuit types. In the Common Emitter (CE) input, or control side of the transistor is the base-emitter terminals and the output, or switch, is the Collector-Emitter pair of terminals. Figure3-1 Common Transistor Switch Configurations Ver 0 3-1

18 3.2 OPERATING POINTS: In the CE (common-emitter) orientation, Figure 3-1a, the input or control side of the transistor switch consists, of the base-emitter pair, and output, or switch contacts, made up of the collectoremitter pair. 1. Emitter terminal is common to input and output for CE orientation 2. CB (common-base) orientation, Figure 3-1b, the base terminal is common 3. CC (common-collector) orientation, Figure 2-1c, the collector terminal is common, incrementally speaking (the supply voltage is also in the common leg) Figure 3-1 Switch Orientation Ver

19 For each orientation, input and output switch curtages, E 1, I 1 E 2, and I 2, are selected to be positive for region II (normal) operation. If these switches function as ON-OFF devices, ideally it is desired that I 2 = 0 when OFF and E 2 = 0 when ON. Also, it is desired that the switches have high gain so that E 1 and I I are minimized compared to ON curtage levels across the load. The objective is to switch supply voltage, E, to and from the load, R v with as little loss as possible due to switch contacts and with a minimum of driving power into the control side of the switch. When a triode switch is turned OFF, its currents are so small that ohmic body resistances create negligible voltage drops. The equivalent circuit of Figure 2-2 applies. To obtain minimum OFF load currents in the switches they should be driven well into cutoff (region I). Equations for this condition: ε Є V eb /δ V eb /δ << 1 << 1 Working to, say a 1 % accuracy, ε -4.6 = 0.01 and for δ = volt (at 20 C), applied junction voltages should be at least as negative as -4.6 X = v (although not too negative or reverse saturation currents may increase). Figure 3-2 Static Equivalent for OFF Condition For operation well into cutoff, the following equations give I e = -I es + α n I CS = -I cs + α n I CS = -(1 - α n ) I CS I c = -I es + α n I CS = -I cs + α n I CS = -(1 - α n ) I CS Then, from Figure 3-2, and noting that V EB = V eb and V CB = V eb ' I E = I e + V EB /R eb Ver 0 3-3

20 I c = I e + V CB /R eb Now comparing curtages in Figure 3-1 to those in Figure 3-2, for the CE switch V EB = E 1 V CB = E 1 - E 2 = E 1 - (E - 12RL) I 1 = I E + I C I 2 = -I C Solution of these equations leads to the formulas Formulas for CB and CC OFF currents can now be derived. The primary importance is OFF "leakage" currents through the load, I 2, and I 2 formulas for all three orientations are listed in Table 3-1 (for restrained inputs, E 1 << 0). The numerical values given are for an asymmetrical transistor in which: and for a circuit in which α i = 0.75 α n = 0.95 I es = 7.9 µa I es = 10 µa R eb = R eb = 10M (M = megohms) R L = 3K (K = kilohms) E = 6 volts E 1 = -1 volt. Each orientation exhibits a sufficiently good OFF quality (small current magnitude) for most switching applications. The CC orientation generally yields the best OFF quality of the three. The restrained OFF current of a CC switch is not well-behaved-off current, it reverses direction. Ver

21 Table 3-1 Output OFF Currents in Region I-Inputs Restrained A triode switch is frequently turned OFF simply by reducing input voltage to zero. The OFF quality then is generally not quite as good as, when the input is restrained. Assuming a large enough supply voltage so that εv Cb /6 <<1 and assuming V eb = 0 for CE and CB when their inputs are shorted, CE and CB solutions are readily derived (reference Table 3.2). Table 3-2 Output OFF Currents and Input Circulating Currents":-'Inputs Shorted For CC orientation, making E 1 = 0 does not make V eb = 0 because of the location of R L (reference Figure 3-3). A solution for I 2 cannot be obtained because of a necessary retention of both an algebraic and an exponential (transcendental) form containing I 2, The implicit solution for I 2 is given in Table 3-2, and example (using earlier cited transistor and circuit values) was obtained by successive trials. The input circulating current, I 1C is given for each orientation in Table 3-2. Ver 0 3-5

22 Figure 3-3 Equivalent Circuit for a CC Switch that is OFF A switch may also be driven by a circuit that effectively opens the input during OFF state. Assuming ЄV Cb /6 << 1 and I 1 = 0, all rigorous solutions are implicit. If V eb /R eb and V eb / R eb are negligible compared to other component currents, explicit solutions are readily attained using equivalent circuits like that in Figure 3-4 for C EO. Formulas for output currents are listed in Table 3-3, and numerical examples based on earlier cited parameter and circuit values are also given. NOTE With input open, V eb should be very small. Also, R eb and R eb are very large and show ratios are negligible. Figure 3-4 Equivalent Circuit for Region I Operation With switch input open, the input will assume a floating potential, E lf. These potentials are in Table 3-3. In both CE and CC switches, when the base of the transistor is open, a small positive potential occurs. Because of this, operation is slightly in region II and OFF current is rather large. In a CB switch, the floating potential is negative, keeping I 2 small and retaining operation within region 1. Ver

23 Figure 3-5 Static Equivalent Circuits of an OFF CE Switch with an Opened Input Table 3-3 Output OFF Currents and Input Floating Potentials-Inputs Opened The output currents in Tables 3-1, 3-2 and 3-3 are often used as quality checks by manufacturers and are sometimes reported on data sheets. If the first subscript represents the (output) terminal where the current is measured, the second subscript represents the common terminal, and the third subscript represents the constraint (R = restrained, S = shorted, and 0 = opened) on the third (input) terminal, in Table 3-1, for example; in Table 3-2 (I 2 )CC = I ECR (I 2 ) CB = I CBS = I cs Ver 0 3-7

24 and in Table 3-3 (I 2 ) CE = I CED (I 2 ) CB = I CBO = I co If the base terminal is the common terminal (as is frequently the case in tests), the middle subscript (B) is generally omitted. In the last example, I co, is the (quality check) current which is often reported and employed in circuit designs. When these currents are given on data sheets, they represent measurements at a specified temperature and voltage level, with R L = O. Thus, R L should be eliminated from Tables 3-1, 3-2 and 3-3 when employing this coding scheme, and appropriate measurement temperature and voltage(s) should accompany any measured current value. Some intrinsic formulas (useful for abbreviating expressions in formulas) under this coding scheme are: NOTE Observe that l eo was obtained from I co simply by an interchange of subscripts corresponding to an inverted sense of operation. In general, if the roles of emitter and collector are interchanged (the transistor is inverted"), all equations in Tables 3-1 to 3-3 are still valid via the simple expedient of interchanging α i and α n, I es, I cs,, R eb and R cb. In ICE (inverted CE operation) operation, from Table 3-1 (restrained input) evaluates as 1.1 µa compared to 3.2 µa for normal C eo. NOTE 1. From this data, it can be seen that inverted operation improves switching quality. 2. The Inverted Configuration will inhibit gain, but switch time will be much faster. Ver

25 When a switch is operated well into regions II, III, or IV, currents are large enough so that surface leakage resistances generally can be ignored; however other ohmic resistances are pertinent. The equivalent circuit is shown in Figure 3-6. Considering region II operation, it is assumed that Є Veb/δ >> 1 and Є Veb/δ <<1. Under these conditions, formulas in Table 2.4 were developed. Note here that I 2 solutions in terms of a current drive, I 1, is explicit, but transcendental factors necessitate implicit solutions in terms of a voltage drive, E 1,. Depending on design of a given switching circuit, either (or both) OFF (low-current) or ON (highcurrent) operating point may be in region II. Table 3-4 Output Curtages in Region II Frequently in region II operation, the desired output point is known. In Table 3.4, therefore, the formulas of Table 3-4 are solved for input curtages. Numerical examples are based on operation at the midpoint of the 3K load line-i 2 = 1 ma and E 2 = E L = 3 volts. CB orientation yields only a voltage gain (input current is slightly greater than load current), and CC orientation yields only a current gain (input voltage is slightly larger than load voltage). Only high gain CE switch gives both current and voltage gain (greater than unity). Tables 3-4 and 3-5 also apply to region IV operation (emitter and collector terminals interchanged) for an interchange between α i ; and α n, 1 es and 1 es, R e and R e and V eb and V eb. Ver 0 3-9

26 For operation well into saturation (region III) it is assumed that both that Є Veb/δ >> 1 and Є Veb/δ >>1. As an example of an ON voltage, E 2 derivation, consider the CB switch. Equations reduce to: From which Also, if switch is functioning respectfully, I 2 I 2S = E/R L that is, almost all the supply voltage is across the load. Therefore, where equation for I eo was employed. For numerical values, I 2S = 6v/3K = 2 ma. If R e = R e = 5 ohms and R b = 100 Ω and an ON drive current of I 1 = 4 ma, a calculation shows E volt. Table 3-5 Output ON Voltages in Region III and IV Ver

27 Derivations for the ON voltage drops across the switch "contacts" are given in Table 3.5 for all three orientations. From the table, it is clear that region II current gains are of the order of β n = α n /(1 - α n ) = 19 for CE, α n = 0.95, for CB, and γ n = 1/(1 - α n ) =. 20 for CC. Thus, a 4 ma ON drive for CB represented an overdrive (into region. III) by a factor of about two (to obtain 2 ma output). Using rough1y a factor of two overdrive ON for CE and CC, the ON drive for their numerical examples in Table 3.6 was I 2 = 2(2 ma/20) = 0.2 ma, NOTE During saturation, CB orientation is not well-behaved. The-ON voltage drop reverses polarity. The CE switch is well-behaved under all conditions. Table 3-5 is also valid for inverted operation by simply replacing α i with α n, and I ES with I CS and R E with R C. A calculation for ICE, β i = α i (1- α i ) = 3, with I 1 = 1.25 ma. This shows E 2 0,043 volts, compared to 0.78 volts for a normal CE. The inverted CE operation yields a much better switch, but with less gain. Figure 3-6 Load Line Superimposed on a Set of CE Output Data Ver

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29 4 TRI-STATE LOGIC The newer TTL families have an additional control input whereby the output of a gate is disabled. This allows the output to remain in a high-impedance (high Z) state, permitting different circuits to be connected to a common bus. A typical tri-state circuit is provided in Figure 4-1. The output enable function is connected through diodes to the bases of Q 2 and Q 3. A low signal input turns off Q 2 and Q 3, thereby disabling pullup and pull-down transistors, Q 4 and Qs, respectively. This represents the high-z state. When the circuit is enabled, the output high and low states are identical to TTL circuits without the tri-state feature. Figure 4-1 Tri-State Circuit Ver 0 4-1

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31 5 MIMIC A LOGIC FUNCTION NAND and NOR gates possess a special property: they are universal. That is, given enough gates, either type of gate is able to mimic the operation of any other gate type. The ability for a single gate type to be able to mimic any other gate type is one enjoyed only by the NAND and the NOR. In fact, digital control systems have been designed around nothing but either NAND or NOR gates, all the necessary logic functions being derived from collections of interconnected NANDs or NORs. 5.1 CONSTRUCTING THE INVERT FUNCTION: There are two ways to use a NAND gate as an inverter (Reference Figure 5-1), and two ways to use a NOR gate as an inverter. Either method works, although connecting TTL inputs together increases the amount of current loading to the driving gate. For CMOS gates, common input terminals decrease the switching speed of the gate due to increased input capacitance. Inverters are a fundamental tool for transforming one type of logic function into another, and so there will be many inverters shown in the illustrations to follow. In those diagrams, I will only show one method of inversion, and that will be where the unused NAND gate input is connected to +V (either V cc or V dd, depending on whether the circuit is TTL or CMOS) and where the unused input for the NOR gate is connected to ground. Bear in mind that the other inversion method (connecting both NAND or NOR inputs together) works just as well from a logical (1's and 0's) point of view, but is undesirable from the practical perspectives of increased current loading for TTL and increased input capacitance for CMOS. Figure 5-1 Constructing the NOT Function Ver 0 5-1

32 5.2 CONSTRUCTING THE "BUFFER" FUNCTION: Being that it is quite easy to employ NAND and NOR gates to perform the inverter (NOT) function, it stands to reason that two such stages of gates will result in a buffer function, where the output is the same logical state as the input. Figure 5-2 Constructing the BUFFER Function Ver

33 5.3 CONSTRUCTING THE AND FUNCTION: To make the AND function from NAND gates, all that is needed is an inverter (NOT) stage on the output of a NAND gate. This extra inversion "cancels out" the first N in NAND, leaving the AND function. It takes a little more work to wrestle the same functionality out of NOR gates, but it can be done by inverting ("NOT") all of the inputs to a NOR gate. Figure 5-3 Constructing the AND Function Ver 0 5-3

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35 5.4 CONSTRUCTING THE NAND FUNCTION: It would be pointless to show you how to "construct" the NAND function using a NAND gate, since there is nothing to do. To make a NOR gate perform the NAND function, we must invert all inputs to the NOR gate as well as the NOR gate's output. For a two-input gate, three additional NOR gates connected as inverters must be added. Figure 5-4 Constructing the NAND Function Ver 0 5-1

36 5.5 CONSTRUCTING THE OR FUNCTION: Inverting the output of a NOR gate (with another NOR gate connected as an inverter) results in the OR function. The NAND gate, on the other hand, requires inversion of all inputs to mimic the OR function, just as we needed to invert all inputs of a NOR gate to obtain the AND function. Remember that inversion of all inputs to a gate results in changing that gate's essential function from AND to OR (or vice versa), plus an inverted output. Thus, with all inputs inverted, a NAND behaves as an OR, a NOR behaves as an AND, an AND behaves as a NOR, and an OR behaves as a NAND. In Boolean algebra, this transformation is referred to as DeMorgan's Theorem, covered in more detail in a later chapter of this book. Figure 5-5 Constructing the OR Function Ver

37 5.6 CONSTRUCTING THE NOR FUNCTION: To making a NOR gate behave as a NAND, simply invert all inputs and output to make a NAND gate function as a NOR. Figure 5-6 Constructing the NOR Function Ver 0 5-3