MTI 7603 Pseudo-Ternary Codes
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1 Page 1 of 1 MTI 7603 Pseudo-Ternary Codes Contents Aims of the Exercise Learning about the attributes of different line codes (AMI, HDB3, modified AMI code) Learning about layer 1 of the ISDN at the base connection (transmitter setting) Overview of Exercises Generating Pseudo-Ternary Codes Exercise 1: Creating pseudo-ternary codes Presentation of the impulse frame presentation of the coding and the different signal processes Exercise 2: Signal and cycle retrieval Presentation of the phase jitter depending on the line codes used Exercise 3: Layer 1 of the ISDN Presentation of the complete frame the ISDN layer 1 using the modified AMI code
2 Page 1 of 6 MTI 7603 Pseudo-ternary Codes Introduction For transmitting digital signals on copper lines, the signals must be adapted to the characteristics of the line and encoded. The codes used here, must meet certain specifications, as described below: Absence of any DC: This is important because very often, transformers and frequency cross-over networks are included in transmission paths. Full use of bandwidth: Two-wire or coaxial copper lines can guarantee only a limited bandwidth. Therefore, binary squarewave signals must be restricted in their bandwidth. Clock recovery: Since a special line is not available for transmitting the clock for synchronisation between transmitter and receiver, the clock information must be included in the coding of the complete signal and reconstructed at the receiver end. Insensitive to interference: The line code is formed from the signal following fixed rules. It must be possible therefore to establish any violation of these rules at any section of the transmission path. Bit-sequence independence: The distribution of "1" and "0" bits must not be subjected to any limitations, i.e. longer sequences of "1" and / or "0" must be permissible. In the exercise here, the use of all three codes AMI, modified AMI (AMImod) and HDB3, is possible. AMI-Code In an AMI code (Alternate Mark Inversion), the binary data signal is encoded to a pseudo-ternary signal as follows: The "1"-values are alternately sent as "+1" and "-1", the "0"-values remain a "0". A code violation is recognised when two "1" bits follow in sequence with the same polarity.
3 Page 2 of 6 Fig. 1: Example of an AMI code HDB3-Code With long sequences of "0", the AMI-coded signal also loses the clock information so, in an HDB3 code (High Density Bipolar 3-level), whenever 3 zeroes follow in sequence, a "1" is inserted in place of the fourth zero. To be able to recognise this at the receive end, this "1" violates the AMI rule (see above) by having the same polarity as the previously sent "1". This "1" is therefore also known as the "V-bit" (violation bit). Since absence of DC is no longer guaranteed, any V-bits following in sequence must be of alternating polarity. In the case of an even number of "1"-bits between two V-bits, the last V-bit will not be recognised as such. For such a case, a further intervention must be made and the first of the four zeroes described above is replaced by a "Bbit" (balancing bit) set to "1", that has the same polarity as the next V-bit.
4 Page 3 of 6 Fig. 02: Example of an HDB3 code Modified AMI-Code (AMImod) In ISDN, the modified AMI c-code is used on the S0-interface. Here, the "0"-values are alternately encoded to the pseudo-ternary values +750 mv and -750mV, whilst the "1"- cvalues are transmitted as 0V. A framing recognition (see below) is ensured by the violation of the AMI rules. Fig. 03: Example of an AMImod code Advantages of a line code:
5 Page 4 of 6 The AMI code is easily formed, free of any DC and transparent. In the HDB3 code, in addition to the AMI code, clock extraction is realised, even with long sequences of zeroes. Disadvantages of a line code: In the AMI code, clock extraction is not possible with long sequences of "0". This influences the stability of the data transmission and phase jitter is produced. The HDB3 code is more resistant to problems of stability but is more difficult to form. Task of the pulse frame: To be able to recover the information from the PCM data stream, a clear, unique timerelationship must be created between the individual channels. This is the task of the pulse frame, where bit 1 of the frame initiates a reset of the coding circuit. Thus, a defined initial state of the signal coding is ensured. Phase jitter: As already mentioned above, in digital transmission a clock signal is required for correct demodulation, that must correspond to the transmitter clock signal. Since the transmitter clock signal is encoded with the PCM data stream, there must be a clock extraction at the receive end. This recovered clock varies, according to the cod and binary value of the information signal. This effect is known as phase jitter. When this variation is greater than half a clock-width, errors occur in the information signal caused by "bit-slip". Depending on the phase shift, a bit will not be recognised or one bit will be sampled twice. Layer 1 of ISDN at the basic access In the exercise here, it is possible to display and examine layer 1 (physical layer) of an ISDN basic access in the send direction (TE > NT). The frame structure for both directions of transmission is illustrated in Fig. 4 below. Since the transmission via the S0-interface is a multiplex transmission of two basic (B) and one signalling channel (D) in either direction, the information for transmission must each be assigned a frame. The width of a frame within which for each B channel, two octets are transmitted, is 250 ms. The bit-clock is f B = 192 khz, the frame cycle is f R = 1/250ms = 4 khz. 48 bits are transmitted in one frame, as follows: 16 Data bits, channel B1 16 Data bits, channel B2 4 Data bits, channel D 12 bits, frame and balancing Thus, the following data transfer rates on the So interface are given: Data transfer rate per B channel: 64 kbit/s
6 Page 5 of 6 Data transfer rate on the D channel 16 kbit/s Fig. 04: Frame structure in layer 1 In addition to the data bits in the two basic access channels B1 and B2, and the signalling channel D, the frame structure also uses the following bits: F Frame timing bit, always positive FA Auxiliary framing bit, always logic "0" L DC balancing bit E Echo-channel bit, repeats the D channel bit in the direction TE>NT A Activation bit N N-bit, always logic "1" S1 Reserve bits for future applications, always logic "0" S2 Reserve bits for future applications, always logic "0" The line code used for the S0 interface is the modified AMI code, described above. Frame synchronisation is made by two specific AMI code violations during transmission of one frame to the next. The first code violation is from the last ternary level of the previous frame to the first bit of the on-going frame. Thus, bit 1 as frame bit, is always positive and the associated bit 2 (DC-balancing bit) is always negative. The second code violation is made at bit 2 of the next ternary level by a bit set to logic "0". In the exercise here, all D-channel bits are set to logic "0", i.e. a transmission is made only of the two B-channels and the resulting DC-balancing bit, L. The functionality of the DC-balancing bit becomes particularly clear in the transmit direction, TE > NT. Each data block commences and ends with a DC-balancing bit. In this way, a change in a data block does not cause any change in the coding of a subsequent block. This results in ensuring a DC balance and additionally, a separation of the data channels.
7 Page 6 of 6
8 Page 1 of 5 MTI 7603 Pseudo-ternary Codes Exercise Assembly Assembly Assemble the basic units consisting of the UniTr@in Interface and the 3 Experimenter cards, according to the illustration above. Insert the cards PAM / PCM modulator (SO4201-7R), AMI / HDB3 coder / decoder (SO4201-3Q) and PAM / PCM demodulator (SO4201-7T) in sequence, in the Experimenter. Using 2mm connection cables, connect the inputs and outputs on the cards: CLCK, SYNC, PCMout / PCMin and GND. Connect the symmetric line output of the AMI / HDB3 coder with two 2mm cables to the symmetric line input on the AMI / HDB3 decoder on the SO4201-3Q PCB. Safety Notice: External sources of voltage must not be connected to the measurement points. Such action will cause damage to the components on the panels! Before switching on the power supply of the UniTr@in I, set all the following switches and potentiometers in their initial: Experimenter card Element Position SO4201-7R Gain potentiometer, channel 1 Fully CCW SO4201-7R Gain potentiometer, channel 2 Fully CCW SO4201-7R Compression mode selector A-Law linear SO4201-7R Channel selector Channel 1 SO4201-3Q Coding selector AMI
9 Page 2 of 5 SO4201-7T Expansion mode selector A-Law linear SO4201-7T Channel selector Both Check the PLL basic clock on the AMI / HDB3 decoder for khz: Adjust the PLL basic clock on the AMI / HDB3 decoder to khz as follows: Set the coding selector to its mid-position, "AMI". All inputs must remain open. Connect a frequency counter to the clock output of the AMI / HDB3 decoder CLOCK and the screening of the test cable to the earth connection on the PCB. With the "Clock" trimmer potentiometer, adjust the frequency to khz ±0.1kHz. Now, connect the symmetric line input "Line in" on the AMI / HDB3 decoder to the symmetric output "Line out" on the AMI / HDB3 coder. The clock frequency indicated on the frequency counter must now change to 192 khz. Sub-assemblies and components required Qty. Description Id.Nr. 1 UniTr@in-I Interface with virtual instruments Operator Elements and Sockets SO4203-2A 3 Experimenter SO4203-2B 1 PAM / PCM modulator SO4201-7R 1 PAM / PCM demodulator SO4201-7T 1 AMI-/ HDB3 coder / decoder SO4201-3Q 1 Measuring line set 2mm UniTr@in I SO5146-1L A B C Synchronous sinewave signal, 1kHz, 2Vpp Synchronous sinewave signal, 500Hz, 2Vpp Gain control, channel 1 D Input, channel 1 E Gain control, channel 2 F Input, channel 2 Output, DC K L U1.1 Test socket, lowpass filter Ch. 1 U2.1 Test socket, lowpass
10 Page 3 of 5 G source, - 5V...+5V H Preset trimmer for DC source M filter Ch. 2 U1.2 Test socket, Sample and Hold, Ch. 1 I J adjusted at works for zero offset maximum for the A/D converter Companding selection all open - A-Law 8 bit linear BR1 - A-Law noninverting BR2 - A-Law with inversion BR3 - µ-law 8 Bit linear BR3+BR1 - µ- LAW N U2.2 Test socket, Sample and Hold, Ch. 2 O Channel selector Fig. 2 Front panel of the PCM modulator A Companding selection all open - A-Law 8 bit linear BR1 - A-Law noninverting BR2 - A-Law with inversion BR3 - µ-law 8 Bit linear BR3+BR1 - µ- LAW C D E At-works setting, zero offset maximum for the D/A converter Test socket, Hold, Ch. 1 Test socket, Hold, Ch. 2 Channel
11 Page 4 of 5 B selector for the channel to be received Fig. 3 Front panel of the PCM demodulator A B C Line output, PCM highway, transmit direction Output impedance matching Control output of the line coded signal (asymmetric, 2:1) Coding type, J K L M Polarity indicator for correct line connection A-A, B-B Line input, PCM highway, receive direction Input impedance matching Control input of the line coded signal (asymmetric, 2:1)
12 Page 5 of 5 D change-over switch E F G Control output of the PCM product, timecoincident with the line output Clock input from PCM modulator Sync. pulse from PCM modulator N O P Potentiometer for adjusting the frequency of the PLL circuit for clock recovery Potentiometer for aligning the pulse length of the PLL circuit (factory setting) Clock output to the PCM demodulator H PCM signal input from PCM modulator R Sync. pulse output to PCM demodulator I Ground S PCM signal output to PCM demodulator T Ground Fig. 4 Front panel of the AMI / HDB3 coder
13 Page 1 of 6 MTI 7603 Pseudo-ternary Codes Assigning the Line Code to Specific PCM Data Words Exercise 1 Displaying the pulse frame After assembling the exercise, set all switches and potentiometers to their initial positions. Connect the input "PCMin" on the AMI /HDB3 coder (SO4201-3Q) to "GND". Set the coding type to "AMI". On channel A of the oscilloscope, measure the signal at the output of the line coder "AMIout" and on channel B, the sync. signal "Frame". Synchronise the oscilloscope on channel B and adjust the trigger level to 50% of the signal amplitude. Use a timebase of 50µs. Draw the signals displayed in the chart provided and comment on the results obtained. What is the purpose of a pulse frame Results: X = 50 µs/div X/T (B) Chan. A= 1 V/DIV DC Chan. B= 2 V/DIV DC Fig.: 1: Pulse frame without signals
14 Page 1 of 2 MTI 7603 Pseudo-ternary Codes Signal and Clock Recovery Exercise: Displaying the phase jitter as a function of the line code used Connect the input "PCMin" on the AMI / HDB3 coder / decoder (SO4201-3Q) to the "GND" socket. On channel B of the oscilloscope, measure the clock signal at the transmit side (signal input CLOCK on the AMI / HDB3 coder) and on channel A, measure the clock signal at the receive side (signal output CLOCK on the AMI / HDB3 decoder). Trigger on the clock signal at the transmit side, channel B! For better triggering, adjust the trigger level to 50% of the signal amplitude. Observe the response of the clock signal at the output of the AMI / HDB3 decoder (receive side). Repeat the procedure, using the HDB3 code (line code selector in the "HDB3" position). Draw the oscillograms and comment on the results. Results: X = 1 µs/div X/T (B) Chan. A= 2 Chan. B= 2 V/DIV DC V/DIV DC Fig.: 1: Phase jitter with the AMI code X = 1 µs/div X/T (B)
15 Page 2 of 2 Chan. A= 2 Chan. B= 2 V/DIV DC V/DIV DC Abb.: 2: Phase jitter with the HDB3 code
16 Page 1 of 3 MTI 7603 Pseudo-ternary Codes Layer 1 of ISDN Displaying the complete frame of layer 1 on ISDN, using modified AMI code In the exercise assembly, ensure that all switches and potentiometers are in their initial settings as given in the assembly notes. Remove the ground connection at the PCM input made in the previous exercise and replace the connection between the AMI-/HDB3 coder (SO4201-3Q) and the PCM modulator. Connect the two inputs LF1 and LF2 of the PAM-/PCM modulator (SO4201-7R) to the internal DC source. Set the logic data words as given in the tables on the worksheets, using the DC potentiometer and the gain controls for channels 1 and 2. Initially, set both gain controls fully clockwise (maximum value). Then, adjust the potentiometer "DC +/-5V" so that channel 1 just shows all 1's. Finally, adjust the gain control for channel 2 to set its value. As an aid, in the last two columns of the table, reference values are given for the voltage and gain values. Check the logic code set on the LED indicator on the PAM / PCM modulator and the PAM / PCM demodulator. Channel DC in /V ,0 5 Gain ,0 2,5 Set the "Coding" selector to AMImod. This corresponds to the modified AMI code on the S0-bus On channel A of the oscilloscope, measure the symmetric output of the line coder "LINE out" and on channel B, the sync signal, "Frame". Synchronise the oscilloscope on channel B and adjust the trigger level to 50% of the signal amplitude. Use a timebase of 50µs. Important: When measurements are made at a symmetric output, the ground connection to the measurement channel must be removed. In the case here, connect input A+ of the UniTr@in-Interface to the line output A on the AMI-/ HDB3 coder and input A- to line output B. Channel B of the UniTr@in-Interface should measure an asymmetric signal. Therefore, input B+ on the UniTr@in-Interface should be connected to the "Frame" socket and input B- to ground. In the lower part of the operating bar of the oscilloscope, the button will be seen for the cursor function. Set this for channel A. Also, two amplitude markers are available for measuring voltages and two time markers for measuring time or frequency.
17 Page 2 of 3 Measure the width of a pulse frame in layer 1 of the So-interface. To what repetition rate does this correspond Determine the amplitude of the line code on a symmetric two-wire line! Results: X = 50 µs/div X/T (B) Chan. A= 1 V/DIV DC Chan. B= 2 V/DIV DC Fig. 1: Frame width, layer 1 of the S0-interface The oscillogram shown below is taken from the exercise completed here. Label the channels B1 and B2. As an aid to identifying the channels, the gain controls for the inputs to channels B1 and B2 on the PAM / PCM modulator can be used to alternately change the information on the channels. In the frame of layer 1, why do 9 bits always change and not only the 8 bits on the channel What is the purpose of this 9th. bit Explain the function of the remaining bits! Using the measured frame width and the number of bits in one frame of layer 1, calculate the data transfer rate for the basic access channels B1 and B2 as well as for the signalling channel D.
18 Page 3 of 3 Fig. 2: Layer 1 of the S0-interface (TE > NT)
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