Input Series-Output Parallel Connected Converter for High Voltage Power Conversion Applications Employing Charge Control

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1 99IECEC12599 Input SeriesOutput Parallel Connected Converter for High Voltage Power Conversion Applications Employing Charge Control JungWon Kim, J. S. You and. H. Cho School of Electrical Engineering Seoul National University Seoul Korea Copyright 1999 Society of Automotive Engineers, Inc. ASTRACT In this paper, the charge control with the input voltage feed forward is proposed for the input seriesoutput parallel connected converter configuration for highvoltage power conversion applications. This control scheme accomplishes the output current sharing for the outputparallel connected modules as well as the input voltage sharing for the inputseries connected modules for all operating conditions including the transients. It also offers the robustness for the input voltage sharing control according to the component value mismatches among the modules. I. INTRODUCTION In the field of high voltage power conversion the circuit designer is often confronted with a problem that there are no semiconductor devices capable of sustaining the required voltage and suitable for the desired switching speed. For this reason, several deviceseries connection methods and converter topologies are proposed. ut the arising problem with deviceseries connection is the voltage balancing at the device turnoff. To get the voltage balancing, a passive or active balancing method is used. The passive method requires a snubber circuit and this causes slow switching speed and introduces additional losses. The active methods require complicated control circuits to get the voltage balancing [14]. And the control delay of the voltagebalancing controller [3,4] can increase the device stress, so the switching speed is restricted. Moreover, perfect balancing is hard to be accomplished during the switching transients. The problems mentioned above can be solved by the input seriesoutput parallelconnected converter configuration. The input seriesoutput parallel connected converter configuration has the input voltage balancing and the output current sharing requirements. In this paper, the charge control with the input voltage feed forward scheme is proposed, which balances the input voltage sharing as well as the output current sharing for each module. With this scheme, the converter modular approach can be easily implemented for any types of converter topologies. II. INPUT SERIESOUTPUT PARALLEL CONNECTED CONVERTER CONFIGURATION Fig.1 shows the input seriesoutput parallel connected converter configuration for highvoltage power conversion applications. Two modules are shown in this figure, but according to the input voltage range more modules can be series connected. Any topology can be used in this configuration if an isolation transformer is used in each module. In this configuration the input voltage is divided by the series connected input capacitors and the output is paralleled. The series connected converter experiences only divided input voltage so the device rating can be reduced. The input capacitors can be utilized as part of an input filter as shown in Fig.1. Fig.1 Input seriesoutput parallel connected converter configuration

2 In this system, there are two separate requirements for control: First, the load current must be shared equally by each outputparalleled module. Secondly, each inputseries module must share the input voltage equally. For the output current sharing, a current mode control can be used. However if the output current is controlled to be the same between the two modules for example, then even a slight mismatch in the transformer causes the input current imbalance and this fails the input voltage sharing. Thus, the average input current of each module must be controlled instead of the output current. For the forward type converter shown in Fig.2, the charge controller directly controls the average input current. Vg 114µH 1µF Vc2 12µF i in1 i in2 4 : µH 47. 7µH 42. 4mΩ 567. mω 3mΩ 22µF Vo. 25Ω the imbalance of the input capacitor voltage and the input capacitor voltage remains unbalanced. 2 1 Module #1 Inductor Current [A] Module #2 Inductor Current [A] Module #1 & #2 Input Capacitor Voltage [V] [sec] Fig.3 Simulation result of the charge capacitor mismatch 2 1 Module #1 Inductor Current [A] Module #2 Inductor Current [A] 2 d1 Mod# Module #1 & #2 Input Capacitor Voltage [V] 8 7 d2 Mod# [sec] Fig.4 Simulation result of the input capacitor mismatch III. CHARGE CONTROL WITH THE INPUT VOLTAGE FEEDACK Fig.2 Schematic of the input seriesoutput parallel connected forward converter with the charge control However, the conventional charge control scheme still has the following problems for the input voltage sharing. If the component value mismatches in the switch current sensing circuit and the charge capacitor,, the average input current can be mismatched, which eventually causes the input voltage imbalance. Fig.3 simulates this case with the twomodule forward converter system shown in Fig.2. In this simulation, there is 2% mismatch in the charge capacitors. As it is seen in this simulation, the imbalance in the input voltage causes the imbalance in the output current. Fig.4 illustrates the case where the value of the input voltage sharing capacitors is not perfectly matched. In this case the input capacitor voltage can be different during the transient. If the average input current of each module is the same, the voltage imbalance can never be fixed. Fig.4 simulates this case with the twomodule forward converter system shown in Fig.2. The initial input voltage is 13V and steps up to 15V at 2ms and the initial load current is 2A and steps down to 1A at 7ms. The 2% imbalance of the input capacitors causes In order to solve the problems discussed above, the charge control employing the input voltage feedback scheme is proposed as shown in Fig.5. Vc2 Vg Vc2 k*(vc2) k*(vc2) i in1 i in2 d1 d2 Mod#1 Mod#2 Input capacitor voltage difference k*(vc2) Input capacitor voltage difference k*(vc2) Vo Fig.5 Proposed charge control scheme

3 The input current of each module is adjusted according to the input capacitor voltage to achieve the voltage balance between the modules for all operating conditions. In this scheme, the input voltage difference is multiplied by a gain, k and this controls the offset voltage in the duty ratio modulator Module #2 Inductor Current [A] 2 1 Module #1 Inductor Current [A] Unbalanced Condition alanced Condition t on1 Module #1 k*(v1v2) Module #2 k*(v1v2) Module #1 & #2 Input Capacitor Voltage [V] [sec] Fig.7 Simulation result of the proposed scheme t on2 when V1 > V2 IV. SMALL SIGANL ANAYSIS Fig.6 alancing mechanism of the proposed method Fig.6 illustrates the balancing mechanism of the proposed method when v1 is higher than v2. ecause of the lowered offset voltage, k*(v1v2), module 1 input current increases and this increased input current makes input capacitor voltage decrease. On the other hand, module 2 input current decreases owing to the raised offset voltage, k*(v1v2), and this reduced input current makes input capacitor voltage increase. In this way v1 and v2 becomes equal and the power balance of two modules is accomplished. The amount of the difference in the input average current to balance the input voltage during the transient can be calculated by Eq.(1). Fig.8 shows the smallsignal equivalent circuit of a twomodule ISOP (input series output parallel) converter system. In this figure, all switches are replaced with its smallsignal PWM model [8]. Rp Lp C1 C2 1:N1 1:N2 I1dˆ1 ˆ2 I2d N1 dˆ1 D1 Vc2N2 dˆ2 D2 1:D1 1:D2 L1 L1 Rl1 Rl1 Rc C R I in max k = 2 C n T V t in max on (1) Fig.8 Small signal equivalent circuit model of ISOP system using PWM switch model where, V in max is the maximum of the input capacitor voltage difference, is the charge control capacitor, t on is the ontime of the switch, n is the turns ratio of current transformer and k is the gain of the differential amplifier of the input voltages. The higher the gain k, the larger I in max is, and lower the gain k makes I in max small but it takes longer time to reach the balanced steady state of the input capacitor voltages. Therefore, there must be a design tradeoff for the gain, k between the current rating of the converter and the settling time. Fig.7 shows the simulation result of the proposed scheme. There is 2% mismatch in the charge capacitor and in the input capacitor. The initial input voltage is 13V and steps up to 15V at 2ms and the initial load current is 2A and steps down to 1A at 7ms. As shown in this figure, to achieve the balance of the input capacitor voltage the input average currents are controlled to be different during the transient. The ISOP system uses input capacitor voltage as the control information for input capacitor voltage balancing. The input capacitor voltages adds new states to the system model and the overall small signal model can be completed adding this two input capacitor voltage feedback loop to the general two loop controlled parallel converter system. The overall small signal block diagram of the ISOP system including this control loop is shown in Fig.9. In Fig.9, Ri and FM are the equivalent current gain and the modulator gain, respectively. He(s) represents the sampledandhold effect in the current loop [9] and k represents the sensing gain of the input voltage difference. In order to obtain design information of the control loop for stability, it is necessary to simplify the system model in Fig.9. Since the system has additional input voltage feedback loops to the conventional current mode controlled parallel module system, the influence of the feedback loop is analyzed.

4 vˆ g ˆ Ggo Zo Gd2o vˆo ISOP system can be simplified to a equivalent single module, and its block diagram is shown in Fig.11. Where, Gd1o Gvc1 Gic1 Gd2c1 vˆc1 G dvo = 2G d1o, Ri ' = Ri / 2, G di = 2(G d1i1 G d2i1) (2) Gd1c1 Gvc2 Gic2 Gd2c2 Gd1c2 Gvi1 vˆc2 Hv vˆ g Gvgvo Zo Gdvo Vˆo Gii1 i în1 Gd2i1 Gd1i1 Gvi2 Gii2 Gd2i2 Gd1i2 iˆin 2 Ri2 k Ri1 He(s) k Gvgi Gioi Gdi î l Ri Tv Hv ˆd 2 dˆ 1 FM2 FM1 He(s) v c v c Fig.9 Overall small signal block diagram of ISOP system with input capacitor voltage feedback Fig.1 shows the transfer function from the control voltage, v c to the output voltage, v o (point ) in Fig.9 with and without the input capacitor voltage loop. As can be seen from this figure, the two plots are almost the same. This can be qualitatively interpreted as follows. Since amount of the input voltage feedback for each module is same but with opposite sign, there is a net canceling effect in the overall system. Phase (deg); Magnitude (d) Frequency (rad/sec) Fig.1 Transfer function from the control voltage to the output voltage with and without the input capacitor voltage feedback loop ( Gci ) Thus, we can conclude that the input capacitor voltage feedback loop has little effect on the control voltage to the output voltage transfer function at point. Then the FM Fig.11 Small signal block diagram of a equivalent singlemodule converter system V. CONTROL LOOP DESIGN The first step of the current loop design is to determine the charge control capacitor,. The voltage across, should not exceed the comparator supply voltage v cs. Thus, is chosen as follows [9]: C (3) 1 DmaxTs T > il, max vcs (t) dt FM, Ri and He(s) have the same expression as those in the conventional charge control [9]. The current loop gain, Ti in Fig.11 is then i G di Ti He T = Ri' He(s) FM (4) Ti can be used for the stability analysis of the current loop closed power stage. Once the current loop is designed, the current loop closed power stage can be treated as a new power stage for the voltage loop design(hv). The system loop gain defined at point is T = G H (5) ci v where, G ci is the transfer function from the control voltage, v c to the output voltage, v o with the current loop closed (new power stage) for a given operating conditions. Fig.1 shows G Ci, from which the voltage loop compensator, Hv can be designed. For Hv, an

5 integrator plus two poles and two zeros compensator is used. K I (1 s / ω z1 ) H v (s) = (6) s (1 s / ω ) p1 Fig. 12 shows the designed loop gain T, which has a wide control bandwidth with an appropriate phase margin. of the mismatches of the component values between the modules. Employing the charge control, the input average currents are controlled to be the same therefore the voltage imbalance is not fixed after the input voltage mismatch occurs. So the supplying power of two modules is unbalanced and one module suffers more stress than the other and this worsens the system reliability. 1 5 Phase (deg); Magnitude (d) o φ M = Frequency (rad/sec) Fig.12 Outer loop gain IV. EXPERIMENTAL RESULT T after the compensation To verify the effectiveness of the proposed control scheme, hardware experiments are performed. The experimental setup is the same as that of the previous simulation cases. Fig.13 shows an experimental result employing the conventional charge control scheme. Fig.14 Experimental wave forms with proposed charge control scheme, [25V/div], [.5s/div] Ch1, Ch2: input capacitor voltages of module #1, #2 Fig.14 shows an experimental result employing the proposed charge control scheme with the input voltage feed forward. The experimental condition is the same as that of Fig.13. In both the steady and transient states the perfect balance of the input capacitor voltages is achieved by the proposed control scheme. So the power balance between the two modules is accomplished by the proposed control scheme and the voltage stress is equally divided between the two modules. Fig.15 shows an expanded view of the input capacitor voltages and the inductor currents of the two modules during the input voltage step change. Fig.13 Experimental wave forms with conventional charge control scheme, [25V/div], [.5s/div] Ch1, Ch2: input capacitor voltage of module #1, #2 The input voltage steps up at 1.5s from 13V to 15V, steps down at 2.5s to 12V and steps up at 3.5s to 13V. The input capacitor of module #2 is 2% greater than that of module #1. The input voltage variation of module #1 during the transients, is greater than that of module #2 because of the smaller input capacitor. In the figure input voltage mismatch is observed not only in the steady state but also during the transients because Fig.15 Experimental wave forms with proposed charge control scheme, [25V/div], [5A/div], [5ms/div] Ch1, Ch2: input capacitor voltages of module #1, #2 Ch3, Ch4: inductor currents of module #1, #2

6 The input voltage steps up from 13V to 15V at 1ms. ecause the input capacitor of module #1 is smaller, the input capacitor voltage of module #1 goes higher than that of module #2. To balance the input capacitor voltage the proposed charge controller increases the input average current of module #1 and decreases the input average current of module #2.The current waveforms in Fig.15 verify the canceling effect for the output voltage control loop as discussed in section IV. In the figure the inductor currents are plotted instead of input average currents for the displaying convenience. There is about 2A difference between the inductor currents of the two modules to balance the input capacitor voltages. V. CONCLUSION In this paper, the charge control with the input voltage feed forward is proposed for the input seriesoutput parallel connected converter configuration for highvoltage power conversion applications. This control scheme accomplishes the output current sharing for the outputparallel connected modules as well as the input voltage sharing for the inputseries connected modules for all operating conditions including the transients. It also offers the robustness for the input voltage sharing control according to the component value mismatches among the modules. The small signal analysis shows that an equivalent single module system can be used for the control loop design process in spite of the input capacitor voltage feedback loop. The performance of the proposed scheme is verified through the experimental results. REFERENCES 1. Christian Gerster, Fast Highpower/Highvoltage Switch Using Seriesconnected IGTs with Active Gate Controlled Voltagebalancing, APEC 94 Proc., pp A. Consoli, S. Musumeci, G. Oriti and A. Testa, Active Voltage alancement of Series Connected IGTs, IAS 95 Proc., pp M.M.akran and M.Michel, A Learning Controller for Voltagealancing on GTOs in Series, IPEC 95 Proc., pp C. Gerster, P. Hofer and N. Karrer, Gatecontrol strategies for snubberless operation of series connected IGTs, PESC 96 Proc., pp N. H. Kutkut, G. Luckjiff and D. M. Divan, A Dual ridge High Current DCtoDC Converter with Soft Switching Capability, IAS 97 Proc., pp K. Siri, C. Q. Lee and T. F. Wu, Current Distribution Control for Parallel Connected Converters: Part 1, IEEE Trans. on Aerospace and Electronic Systems, Vol. 28, No. 3, July 1992, pp J. Masserant, E. W. eans and T. A. Stuart, A Study of Volume vs. Frequency for Soft Switching Converters, PESC 92 Proc. pp V. Vorperian, Simplified analysis of PWM converters using the model of the PWM switch:part I and II, IEEE Trans. on Aerospace and Electronic Systems, Vol 26, No.3, 199, pp Wei Tang, F.C.Lee, R..Ridley and I. Cohen, Charge control: modeling, analysis and design, IEEE Trans. on Power Electronics, Vol. 8, No.4, Oct. 1993, pp

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