Characteristic Value Units Drain-to-Source Voltage. 28 Continuous Drain Current (T C =100 C)
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1 $GYDQFHG 3RZHU 026)(7 IRL540A FEATURES Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area Lower Leakage Current: 10µA = 100 Lower R DS(ON) : 0.046Ω (Typ.) BS = 100 R DS(on) = 0.058Ω I D = 28 A TO Absolute Maximum Ratings 1.Gate 2. Drain 3. Source Symbol S I D I DM E AS I AR E AR dv/dt P D T J, T STG T L Characteristic alue Units Drain-to-Source oltage 100 Continuous Drain Current (T C =25 C) 28 Continuous Drain Current (T C =100 C) 19.8 A Drain Current-Pulsed Gate-to-Source oltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (T C =25 C) Linear Derating Factor Operating Junction and Storage Temperature Range (1) (2) (1) (1) (3) 98 ± to +175 A mj A mj /ns W W/ C Maximum Lead Temp. for Soldering C 300 Purposes, 1/8 from case for 5-seconds Thermal Resistance Symbol R θjc R θcs R θja Characteristic Typ. Max. Units Junction-to-Case Case-to-Sink Junction-to-Ambient C/W Rev. B 1999 Fairchild Semiconductor Corporation 1
2 IRL540A 1&+$11(/ Electrical Characteristics (T C =25 C unless otherwise specified) Symbol Characteristic Min. Typ. Max. Units Test Condition BS Drain-Source Breakdown oltage 100 =0,I D =250µA B/ T J Breakdown oltage Temp. Coeff. 0.1 / C I D =250µA See Fig 7 (th) Gate Threshold oltage =5,I D =250µA I GSS Gate-Source Leakage, Forward Gate-Source Leakage, Reverse na =20 =-20 I DSS Drain-to-Source Leakage Current µa =100 =80,T C =150 C R DS(on) Static Drain-Source On-State Resistance Ω =5,I D =14A (4) g fs Forward Transconductance 22 Ω =40,I D =14A (4) C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance pf =0, =25,f =1MHz See Fig 5 t d(on) t r t d(off) t f Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time ns =50,I D =28A, R G =4.6Ω See Fig 13 (4) (5) Q g Total Gate Charge =80, =5, Q gs Gate-Source Charge 6.2 nc I D =28A Q gd Gate-Drain ( Miller ) Charge 23.3 See Fig 6 & Fig 12 (4) (5) Source-Drain Diode Ratings and Characteristics Symbol Characteristic Min. Typ. Max. Units Test Condition I S I SM Continuous Source Current Pulsed-Source Current (1) A Integral reverse pn-diode in the MOSFET SD Diode Forward oltage (4) 1.5 T J =25 C,I S =28A, =0 t rr Reverse Recovery Time 132 ns T J =25 C,I F =28A Q rr Reverse Recovery Charge 0.63 µc di F /dt=100a/µs (4) Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature (2) L=1mH, I AS =28A, =25, R G =27Ω, Starting T J =25 C (3) I SD 28A, di/dt 400A/µs, BS, Starting T J =25 C (4) Pulse Test: Pulse Width = 250µs, Duty Cycle 2% (5) Essentially Independent of Operating Temperature 2
3 1&+$11(/ IRL540A I D, Drain Current [A] Top : Bottom : 3.0 Fig 1. Output Characteristics µs Pulse Test 2. T C = 25 o C , Drain-Source oltage [] I D, Drain Current [A] o C Fig 2. Transfer Characteristics 175 o C - 55 o C 1. = 0 2. = µs Pulse Test , Gate-Source oltage [] 0.08 Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward oltage R DS(on), [ Ω] Drain-Source On-Resistance = 5 = Note : T J = 25 o C I D, Drain Current [A] I DR, Reverse Drain Current [A] o C 25 o C 1. = µs Pulse Test SD, Source-Drain oltage [] Capacitance [pf] Fig 5. Capacitance vs. Drain-Source oltage C iss C oss C rss C iss = C gs + C gd ( C ds = shorted ) C oss = C ds + C gd C rss = C gd , Drain-Source oltage [] 1. = 0 2. f = 1 MHz, Gate-Source oltage [] Fig 6. Gate Charge vs. Gate-Source oltage = 20 = 50 = 80 I D = 28 A Q G, Total Gate Charge [nc]
4 IRL540A 1&+$11(/ 1.2 Fig 7. Breakdown oltage vs. Temperature 3.0 Fig 8. On-Resistance vs. Temperature BS, (Normalized) Drain-Source Breakdown oltage = 0 2. I D = 250 µa T J, Junction Temperature [ o C] R DS(on), (Normalized) Drain-Source On-Resistance = 5 2. I D = 14 A T J, Junction Temperature [ o C] I D, Drain Current [A] Fig 9. Max. Safe Operating Area Operation in This Area is Limited by R DS(on) 100 µs 1 ms 10 ms DC T C = 25 o C 2. T J = 175 o C 3. Single Pulse , Drain-Source oltage [] I D, Drain Current [A] Fig 10. Max. Drain Current vs. Case Temperature T, Case Temperature [ o C] c Fig 11. Thermal Response Z θjc (t), Thermal Response D= single pulse 1. Z θ JC (t)=1.24 o C/W Max. 2. Duty Factor, D=t 1 /t 2 3. T JM -T C =P DM *Z θ JC (t) P DM t 1 t t, Square Wave Pulse Duration [sec] 1
5 1&+$11(/ IRL540A Fig 12. Gate Charge Test Circuit & Waveform 12 Current Regulator 200nF 50kΩ 300nF Same Type as DUT 10 Q g Q gs Q gd 3mA Current Sampling (I G ) Resistor DUT R 1 R 2 Current Sampling (I D ) Resistor Charge Fig 13. Resistive Switching Test Circuit & Waveforms R L in out ( 0.5 rated ) out 90% R G 10 DUT in 10% t d(on) t r t d(off) tf t on t off Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms L L 1 E AS = 2 L L I 2 AS BS BS ary t p to obtain required peak I D ID BS I AS R G C I D (t) 5 DUT (t) t p t p Time 5
6 IRL540A 1&+$11(/ Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + I S L Driver RG Same Type as DUT dv/dt controlled by R G I S controlled by Duty Factor D ( Driver ) Gate Pulse Width D = Gate Pulse Period 10 I FM, Body Diode Forward Current I S ( DUT ) di/dt I RM Body Diode Reverse Current ( DUT ) Body Diode Recovery dv/dt f Body Diode Forward oltage Drop 6
7 TO-220 Package Dimensions TO-220 (FS PKG CODE AE) 9.90 ± ±0.20 (1.70) 1.30 ±0.10 (8.70) ø3.60 ± ± ± ±0.20 (1.46) (1.00) 1.27 ±0.10 (45 ) (3.00) (3.70) ± ± ± MAX. 2.54TYP [2.54 ±0.20] 0.80 ± TYP [2.54 ±0.20] ± ±0.20 Dimensions in Millimeters September 1999, Rev B
8 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. DISCLAIMER ACEx CoolFET CROSSOLT E 2 CMOS TM FACT FACT Quiet Series FAST FASTr GTO HiSeC ISOPLANAR MICROWIRE POP PowerTrench QFET QS Quiet Series SuperSOT -3 SuperSOT -6 SuperSOT -8 TinyLogic UHC CX FAIRCHILD SEMICONDUCTOR RESERES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
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