Engineer To Engineer Note

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1 Engineer To Engineer Note EE-68 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Using Third Overtone Crystls with the ADSP-8x DSP Contributed by Lrry Hurst August 8, 00 Introduction DSPs frequently require n input clock frequency (CLKIN) tht is over 35MHz. Unfortuntely fundmentl mode crystls over 35MHz re not populr nd tend to be expensive nd frgile. Pckged clock oscilltors cost considerbly more thn crystl so, for some pplictions, using 3 rd overtone (3 rd OT) crystl my be sensible choice. While the current trend is to incorporte PLL frequency multipliction into the DSP, using low frequency input clock to generte internl core clocks of severl hundred MHz, there re still occsions when it might be useful to consider using 3 rd OT crystl. This note discusses using redily vilble 3 rd overtone crystls, t frequencies over 35MHz, with the ADSP-8x fmily of DSPs. A design procedure is developed for clculting the optimum vlues for the support components. This procedure cn be extended to CODECs nd other pplictions requiring input clocks over 35MHz. Cutionry Note There re number of cutions tht should be noted when deciding to use 3 rd OT crystl oscilltor. First, 3 rd OT crystl normlly hs higher ESR, typiclly more thn twice tht of fundmentl mode crystl t the sme frequency. Second, 3 rd OT crystl hs lower ctivity, (i.e. requires higher minimum drive level to strt relibly). For these resons, extr cre should be tken when designing 3 rd OT crystl oscilltors nd creful testing should be performed over temperture, voltge nd with representtive btch of crystls to ensure tht ll prts operte relibly. Note tht there is often no indiction, mrked on the crystl pckge, to show tht crystl is intended for 3 rd OT opertion verses fundmentl mode opertion. Cre should be tken to determine this informtion. If crystl is used in trditionl (two cpcitor fundmentl mode circuit) ppers to be oscillting t pproximtely one third of the frequency mrked on it s pckge, it is very likely tht it is intended for 3 rd OT opertion. Design Method When 3 rd OT crystl is chosen, two dditionl circuit components must be dded to the trditionl prllel, or fundmentl mode circuit, to force oscilltion t the overtone frequency mrked on the crystl. The dded components consist of series inductor nd cpcitor s shown in Figure. If L nd C 3 re not dded to the circuit, the crystl will oscillte t its fundmentl frequency, which is pproximtely one third of the desired overtone frequency. Copyright 00, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding the technicl ccurcy nd topiclity of the content provided in ll Anlog Devices Engineer-to-Engineer Notes.

2 ADSP-8x-/L/M/N DSP V DDINT 8 GND 7 C 4-5V L3.3V M.5V N.8V GND C IN C FB CLKIN XTAL 3 4 C IS C IS, C FBS, C OS ARE STRAY CAPACITANCES Y R FB C FBS C OUT C OS L C C C 3 6 CLKOUT V DDEXT 5 GND 7 C 5 COMPONENTS ADDED FOR 3 RD OT OSCILLATOR -5V L3.3V M.5-3.3V N.8-3.3V Figure : Schemtic of 3rd Overtone Crystl Oscilltor Note tht the three cpcitors, C, C nd C 3, must be RF types with low loss dielectrics t the frequencies being used. Exmples of cpcitors with suitble dielectrics include silver mic, polystyrene nd cermic NP0. The inductor, L, must lso be chosen for low RF losses (i.e. high Q ). At these frequencies nd inductnce vlues this usully mens n ir core type, lthough there re some inductors tht use specil formultions of iron dust nd/or ferrites tht result in high Q. As guide, look for n inductor with Q greter thn 30, DC resistnce less thn.0ω nd selfresonnt frequency (SRF) greter thn 0MHz. The crystl s lod cpcitnce (C L ) is required to ensure the crystl opertes t the lbeled frequency nd will be specified by the crystl mnufcturer. This is usully stndrd vlue nd 8pF is very common. It is up to the engineer to choose the correct vlues for C, C, C 3 nd L in conjunction with the mplifier nd stry PCB cpcitnce, to provide the correct lod cpcitnce, C L. C nd C will usully be between 0pF nd 70pF. C 3 is only required for blocking DC current tht would otherwise lod the output of the oscilltor. Its vlue is not criticl nd vlue of nf NP0 should be stisfctory. The inductor, L, is chosen to resonte with C nd the stry output cpcitnce t frequency f R ⅔ of the 3 rd OT frequency, f OT. This provides the correct loding rectnce for the crystl nd closed loop phse reltionship to strt nd mintin oscilltion. In ddition, the prllel combintion of L nd C must provide n effective cpcitnce, C EFF t the 3 rd OT frequency, f OT, to correctly lod the crystl. We hve the following two equtions with two unknown vlues, L nd C f R f 3 OT X π X ( C + C + C OUT OS ) L Eqution C fot, XC Eqution EFF XC + X L πfotc EFF EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge of

3 where f R is the ctul resonnt frequency of L combined with the totl output cpcitnce, C, C OUT nd C OS. Note tht C is the ctul cpcitor vlue used while C EFF is the effective cpcitnce t f OT due to the prllel combintion of C nd L. The rectnce of C 3 is smll enough to be ignored. Similrly the contributions of the feedbck cpcitnces, C FB nd C FBS, re very smll nd cn be ignored in determining the required vlues of C nd L. With some simple rithmetic mnipultion we hve the resulting design equtions for C nd L C L 4ω 9C EFF OT Eqution 3 ( C + C ) OUT OS ( C + C + C ) EFF 5 OUT OS Exmple: Determining Externl Lod Cpcitors, C, C nd Inductor L Assume mnufcturer specifies 37.5MHz 3 rd OT crystl with lod cpcitnce, C L 8pF. For the ADSP-8xM/N oscilltor mplifier, typicl vlues re C IN 5pF, C OUT 7pF nd C FB pf. For the PCB stry cpcitnces, ssume C IS pf, C OS 3pF nd C FBS pf. These re ll resonble pproximtions nd, in prctice, couple of pf either wy will not mke much difference. To clculte the equivlent cpcitnce cross the crystl, first note tht the input nd output cpcitnces re effectively in series. C AT : Therefore, the mplifier totl cpcitnce, C AT C FB + C IN C OUT /(C IN + C OUT ) [+ 5 7/(5 + 7)] 4pF Eqution 4 For the PCB totl cpcitnce, C PCBT : where: ω OT πf OT C PCBT C FBS + C IS C OS /(C IS + C OS ) Summrizing, the crystl mnufcturer will specify totl lod cpcitnce for the crystl. This is the TOTAL vlue of cpcitnce tht must pper cross the two terminls of the crystl for the operting frequency to be within the specified tolernce of the vlue stmped on the pckge. The totl cpcitnce is usully clled the lod cpcitnce, C L, nd will consist of the mplifier input cpcitnce, C IN, feedbck cpcitnce, C FB nd output cpcitnce, C OUT. Added to these is the PCB stry cpcitnces, C IS, C FBS nd C OS. Finlly we hve to dd the externl cpcitors C nd the prllel combintion of C nd L. [ + 3/( + 3)] pf Therefore, totl Amplifier nd PCB stry cpcitnce, C ST : C ST C AT + C PCBT 6pF The totl lod cpcitnce is specified by the crystl mnufcturer. In this cse, C L 8pF. We hve 6pF provided by the mplifier in the DSP nd stry PCB cpcitnce, s noted bove. Hence we hve to dd nother pf in prllel to mke totl of 8pF. This cpcitnce is provided by C nd the combintion of C in prllel with L. EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 3 of

4 NOTE: It is most common to mke C nd C equl, nd, since they re in series cross the crystl, the resulting vlues for C nd C EFF will ech be 4pF, the series combintion mking the pf required to mke-up the specified totl lod cpcitnce. NOTE tht this sleight of hnd introduction of cpcitnce C EFF in plce of C which is the effective cpcitnce of the prllel combintion of C nd L required to mke 4pF t the 3 rd OT frequency. At this point we hve determined the vlue of C - in this exmple, C 4pF H L 66.nH Checking Clculted Vlues To check the effective cpcitnce of the C //L combintion t f OT, we cn use the expression; C EFF which simplifies to; + jωl jωc jω jωl jωc From the design equtions, 3 & 4, we cn determine the vlues of C & L, C EFF C ω L C C 9 EFF ( C + C ) OUT OS Substituting vlues; C [9*4 + 4(7+3)]/5 5.pF C EFF 5.pF /(π37.5e6) 66.E-9 C EFF 4pF C 5.pF Also, knowing the required crystl overtone frequency, ω OT πf OT π 37.5MHz; Also, to confirm the frequency of resonnce, from eqution ; f r /[π {(5.pF + 7pF + 5pF)66.nH}] f r 5.0MHz f OT /3 L 4ω OT ( C + C + C ) EFF 5 OUT L 5/[4(π37.5 0E6) (4+7+5)0E-] OS So ll the clcultions look good. Using preferred vlues, we cn complete our design s shown in Figure. (See Appendix A for detiled component list) EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 4 of

5 ADSP-8x DSP C FB 8 V DDINT +.5V 7 C GND 4 GND C IN CLKIN XTAL 3 4 C IS R FB C FBS C OUT C OS 6 CLKOUT 5 V DDEXT +3.3V 7 C GND 5 C pf Y 37.5MHz 3 RD OT C 56pF L 680nH C 3 nf Figure : 37.5MHz, 3rd Overtone Crystl Oscilltor Test Results A totl of 5, 37.5MHz 3rd OT crystls were tested from three different btches. A second test of three different btches of five, 40MHz 3 rd OT crystls were tested using the sme circuit component vlues s for the 37.5MHz crystls. Finlly, third test of three 34MHz 3 rd OT crystls were tested. All tests were performed on n ADSP-89M EZ-KIT LITE evlution bord. The results re tbulted in Appendix B. Note especilly tht ll crystls re oscillting within the ±50ppm (±875Hz for 37.5MHz) frequency tolernce specified by the crystl mnufcturer. The worst-cse devition is within 5ppm. The mnufcturer s test sheet shows the verge operting frequency is bove 37.5MHz by +9.8Hz. Checking the verge for our ppliction shows the frequency to be high by 9Hz. This error would normlly be considered insignificnt nd could be ignored. The difference between the mnufcturer s mesured verge frequency nd our ppliction is 6Hz. If it is desired to trim (reduce) the operting frequency, we could increse the lod cpcitnce using the Pullbility Eqution to estimte the dditionl lod cpcitnce required. where This eqution is given by CLC f f ( C + C ) Crystl Lod Cpcitnce 0 C L C 0, C Crystl Cpcitnce Prmeters Using the verge crystl prmeters from Appendix C, the verge pullbility of the 37.5MHz crystls is 30Hz/pF. Hence by incresing the lod cpcitnce C L by 6Hz/30Hz/pF 8.75pF, the men frequency should be close to the mnufcturer s quoted mesurements. No ttempt ws mde to verify this mesurement s the operting frequency ws L Hz EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 5 of

6 lredy well within the mnufcturer s specifictions for ll prts. A check of voltge t the input to the crystl network shows the drive voltge to be pproximtely.5vpp or just under Vrms. Lcking the instruments to mesure crystl current, Spice simultion ws run, using the typicl crystl prmeters t the operting frequency. This showed current through R (pproximting the crystl ESR) of pproximtely.ma. From the reltion I R, where the crystl resistnce is tken to be 65Ω, the crystl drive power is estimted to be greter thn 93µW, which is considered sufficient to ensure oscilltion. Strtup times for severl 37.5 nd 40MHz crystls were checked nd rnged from minimum of ms up to mximum of 35ms. Design Omissions At this point it is useful to consider wht hs been ignored. The most importnt design considertions, ignored up till now, re the loop gin nd the crystl drive level. The design process should im for n overll loop gin (t zero degrees) of t lest +0dB. While n mplifier gin of +30dB my seem sufficient, the crystl feedbck network (including the source resistnce of the mplifier) my hve n ttenution of more thn +0dB, thus reducing the gin mrgin. The loop gin is determined, in prt, by the internl mplifier nd is not something we hve control over. We cn minimize losses in the externl feedbck network by using high-q RF cpcitors nd inductors nd keeping ll led lengths nd PCB trces very short. Using crystls with the lowest possible equivlent series resistnce (ESR) is lso good ide. The crystl drive level is usully mesured in microwtts (µw) nd third overtone crystls require higher minimum drive level thn fundmentl mode crystls t the sme frequency. This is prmeter tht is difficult to mesure nd outside the scope of this pper. While the mnufcturer specifies the mximum crystl drive level, typiclly 500µW to mw, the minimum drive level is usully not mentioned. This is unfortunte s it is one of the resons why some 3 rd OT crystl oscilltors fil intermittently. Below certin minimum drive level, crystl my not strt, or will strt nd then stop intermittently. The problem hs been excerbted with the trend to lower operting voltges for the mplifier. At V DDEXT 3.3V, the vilble c signl is bout hlf the mplitude obtined with 5V supply. This reduces the crystl drive to level to 5% of 5V system. The crystl drive level should be mesured nd confirmed, if the fcility is vilble. If possible, crystls should be selected with n ESR less thn 50Ω. Extensive testing for strtup relibility should be done to ensure opertion for the limits of temperture, voltge nd production tolernces. Appliction Notes At RF frequencies, cre must be tken to bsolutely minimize trce nd led lengths. Also, ground plne is strongly recommended to ensure stbility nd reduce EMI. All DSP power pins should be bypssed to the ground plne with 0nF nd/or 00nF surfce mount cpcitors, right t the pins. Other oscilltors on the sme PCB should be physiclly seprted nd crefully decoupled to prevent mutul interction vi common power supply impednces. Filure to do this cn lso increse clock jitter. The ground connections for cpcitors C..5 should be connected to the ground plne with the shortest possible trces. The mplifier s ground pin(s) should be connected directly to the ground plne vi without trce. EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 6 of

7 The ctul frequency of oscilltion should be within the mnufcturer s specified tolernce of the frequency mrked on the crystl pckge. This is usully quoted by the mnufcturer, in ppm. Typicl tolernces re ±50 or ±00ppm. At 37.5MHz tolernce of ±50ppm is ±875Hz. If n ccurte frequency counter is vilble, this should be confirmed, however, llownce should be mde for the extr lod impednce of the counter probe, unless the DSP hs buffered mesurement point (e.g. CLKOUT). If the operting frequency were outside this tolernce bnd it would indicte tht the totl lod cpcitnce is in error or there is some other serious problem. Some crystl mnufcturers will quote figure clled the pullbility of the crystl, usully in ppm/pf or Hz/pF. A typicl figure is bout 30Hz/pF (see Appendix C, prmeter P ). This shows tht n error of few pf hs only smll effect on the operting frequency. It ws mentioned erlier tht the two externl lod cpcitors, C nd C EFF, re normlly equl vlues. It is possible to chnge the rtio of these two cpcitors while mintining the sme totl lod cpcitnce. This is sometimes done to increse or decrese the feedbck rtio nd chnge the behvior of the oscilltor. The objective might be to increse strt-up speed with low gin mplifier or improve stbility if the mplifier gin is too high. These re not common requirements nd re beyond the scope of this pper. 5 th nd Higher Overtone Crystls The sme principles described in this note pply to using 5 th overtone nd higher-order crystls. The prllel circuit consisting of C, L nd the stry output cpcitnce should be chosen to resonte hlfwy between the chosen overtone frequency nd the next lowest overtone. For 5 th OT crystl, this would require f R ⅘ of the 5 th OT frequency, f OT. It is still necessry to provide the mnufcturer s specified lod cpcitnce cross the crystl nd provide the correct network phse nd gin conditions to initite nd support oscilltion only t the chosen overtone. Note tht the circuit becomes more criticl of component tolernces s the overtone order increses, nd 5 th order opertion, nd higher, is not recommended for production pplictions. For clock frequencies up to 75MHz, it should not be necessry to use 5 th OT mode crystls. Appendix A Components for the Exmple 37.5MHz 3 rd Overtone Test Circuit Ref Designto r Description Pckge Mnufcture r Prt Number C pf, ±5%, 50V, NP0 SMD 0603 Pnsonic ECJ-VCH0J C 56pF, ±5%, 50V, NP0 SMD 0603 Pnsonic ECJ-VCH560J C3 nf, ±5%, 50V, NP0 SMD 0603 Pnsonic ECJ-VCH0J L 680nH, ±0%, Q min 40, DCR<0.6Ω, SRF min 75MHz SMD 008 API Delevn K Y 37.5MHz, 3rdOT Crystl Crdinl CSM-ABC D8-3 EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 7 of

8 Appendix B: 3 rd OT Crystl Test Results ADSP-89M EZ-KIT. 3rd OT Crystl Oscilltor Frequency Mesurements Tests on selection of 3rd OT Crystls Frequency Counter: HP Model 538A Approx min llowed for oscilltor frequency to stbilize (typiclly drifts up bout 00Hz) FL MHz Tolernce 50 ppm 875 Hz CL 8 pf FL Mesured Frequency Xtl ppm Hz CLKOUT(kHz) Xtl(kHz) Error-Hz CLP (ThruHole) CSM (SMD) CX (SMD) Avg FL MHz Tolernce 50 ppm 000 Hz CL 8 pf NOTE: Sme 3rd OT LC circuit vlues s used for 37.5MHz circuit. This crystl frequency over clocks the 89M DSP nd is not recommended FL Mesured Frequency (Hz) Xtl ppm Hz CLKOUT (khz) Xtl(kHz) Error-Hz CLP (ThruHole) CSM (SMD) CX (SMD) Avg FL MHz Tolernce 50 ppm 700 Hz CL 0 pf NOTE: Sme 3rd OT LC circuit vlues s used for 37.5MHz circuit. FL Mesured Frequency (Hz) Xtl ppm Hz CLKOUT Xtl (/) Error-Hz CLP (ThruHole) EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 8 of

9 Appendix C: Mnufcturer s Smple Crystl Prmeters Ref Freq MHz (3rd OT) CL 8 pf FL Ts Rs Fs C0 C L P Xtl ppm Hz ppm/pf Ohm ppm Hz pf ff mh Hz/pF CLP (ThruHole) CSM (SMD) CX (SMD) AVG Ref Freq MHz (3rd OT) CL 8 pf FL Ts Rs Fs C0 C L P Xtl ppm Hz ppm/pf Ohm ppm pf ff mh Hz/pF CLP (ThruHole) CSM (SMD) CX (SMD) AVG Ref Freq MHz (3rd OT) CL 0 pf FL Ts Rs Fs C0 C Q P Xtl ppm Hz ppm/pf Ohm ppm Hz pf ff k Hz/pF CLP (ThruHole) HC49/LP AVG EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 9 of

10 Acknowledgements Specil thnks to Dve Bbcock nd Mrlyn Thoms of Crdinl Components, for providing vriety of 3 rd OT crystls, test prmeters, ppliction dvice nd proof reding this note. Thnks lso to my collegues Steven Cox, Dvid Ktz, Greg Koker nd Glen Ouellette for suggestions nd proof reding. Regrettbly the uthor must ssume responsibility for ny remining errors. References Crdinl Components, Inc Wyne Interchnge Plz II 55 Route 46 West Wyne, NJ Tel: Oscilltor Design & Computer Simultion, nd Ed, Rndll W. Rhe, Noble Pub, 995, ISBN Crystl Oscilltor Circuits, Robert J. Mtthys, John Wiley & Sons, New York, ARRL Hndbook CD, Ver 4.0, 000. Printed version, 77 th Ed. ISBN: Published nd vilble from the ARRL, Newington, CT 06, USA 4. Oscilltors for Microcontrollers, Intel Appliction Note, AP-55, December HCMOS Crystl Oscilltors, Thoms B. Mills, Ntionl Semiconductor Appliction Note, AN-340, My CMOS Oscilltors, Mike Wtts, Ntionl Semiconductor Appliction Note, AN-8, October A Study of the Crystl Oscilltor for CMOS-COPS, Abdul Alef, Ntionl Semiconductor Appliction Note, AN-400, August Fundmentls of Qurtz Oscilltors, Hewlett-Pckrd Appliction Note, Some Chrcteristics & Design Notes for Crystl Feedbck Oscilltors, Motorol Applictions Engineering 0. Introduction to Qurtz Frequency Stndrds, John R. Vig, Army Reserch Lbortory, Fort Monmouth, NJ , USA. SLCET-TR-9-(Rev. ), October 99 (Reproduced by Oscilltek Inc.). Crystl Oscilltor of SAM V4., Infineon Technologies AG, Appliction Note.99, DS.. Applying Crystls, Mrtin Eccles, Electronics World + Wireless World, August Principles of Qurtz Crystl Opertion, Crdinl Components, Inc., Appliction Note 4. Qurtz Crystl Theory of Opertion, FOX Electronics Appliction Note EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge 0 of

11 5. One Pin Crystl Oscilltors, Hrln Ohr, Micro Liner Appliction Note, AN-8, Sept Oscilltor/Crystl Informtion for the 86 Fmily, Intel. Website informtion 7. Oscilltion Circuit Design Guide, Technicl Note, Seiko Epson Corp, A Technicl Tutoril on Digitl Signl Synthesis, Anlog Devices, White Pper, High Speed Digitl Design A Hndbook of Blck Mgic, Howrd W. Johnson, Mrtin Grhm, 993, Prentice-Hll, ISBN Refer Ch, 0. A New Discourse on Crystl Oscilltor Bsics, Witk P. Lee, Pge 69, RF Design, April Bsic Crystl Oscilltor Design Considertions, C. Tylor, D. Kenny, pge 75, RF Design, October 99.. Designing Crystl Oscilltors, Dvid Bbin, pge 93, Mchine Design, Mrch 7, Guidelines for Crystl Oscilltor Design, Dvid Bbin, pge 90, Mchine Design, April 5, Spice Techniques for Anlyzing Qurtz Crystl Oscilltors, T. Kien Truong, pge 6, RF Design, Sept Oscilltor Design Hndbook, A Collection from RF Design, 990, Crdiff Publishing Co 6. DSP IC s Clock Oscilltor Uses Inexpensive Crystls, Sergey Dickey, pge 7, EDN Mgzine, Mrch, Resontor Terminology nd Formuls, Appliction Note, Piezo Technology Inc. 8. Some Chrcteristics nd Design Notes for Crystl Feedbck Oscilltors, Motorol Appliction Engineering. 9. Frequency Synthesis Hndbook, nd Ed, A Collection from RFDesign, July 993, Crdiff Publishing Co, ISBN Crystls, Oscilltors & Clocks for DSPs, Lrry Hurst, Appliction Pper, 8-8-0, Anlog Devices Inc. EE-68: Using Third Overtone Crystls with the ADSP-8x DSP Pge of