TEA1731TS. 1. General description. 2. Features and benefits. GreenChip SMPS control IC

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1 Rev August 2012 Product data sheet 1. General description The is a low cost Switched Mode Power Supply (SMPS) controller IC intended for flyback topologies. The operates in peak current and frequency control mode. Frequency jitter has been implemented to reduce ElectroMagnetic Interference (EMI). Slope compensation is integrated for Continuous Conduction Mode (CCM) operation. The IC features OverPower Protection (OPP). The controller accepts an overpower situation for a limited amount of time. One pin is reserved for protection purposes. OverTemperature Protection (OTP) can be implemented with a minimal number of external components. At low-power levels, the primary peak current is set to 25 % of the maximum peak current. The switching frequency is reduced to limit the switching losses. The combination of fixed frequency operation at high output power and frequency reduction at low output power provides high efficiency over the total load range. The makes the design of low cost, highly efficient and reliable supplies for power requirements up to 75 W easier by requiring a minimum number of external components. 2. Features and benefits SMPS controller IC enabling low-cost applications Large input voltage range (12 V to 30 V) Integrated OverVoltage Protection (OVP) on VCC Very low supply current during start-up and restart (10 A typical) Low supply current during normal operation (0.58 ma typical without load) Internal overpower time-out Overpower or high/low line compensation (NXP patent: EP01) Fixed switching frequency with frequency jitter to reduce EMI Frequency reduction at medium power operation to maintain high efficiency Frequency reduction with fixed minimum peak current to maintain high efficiency at low output power levels Frequency increase at peak power operation Slope compensation for CCM operation Adjustable soft start Low and adjustable OverCurrent Protection (OCP) trip level

2 3. Applications 4. Ordering information Protection input (for external OTP and external OVP) IC overtemperature protection All applications that require an efficient and cost-effective power supply solution up to 75 W. Table 1. Ordering information Type number Package Name Description Version TSOP6 plastic surface-mounted package; 6 leads SOT Block diagram Fig 1. block diagram All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

3 6. Pinning information 6.1 Pinning Fig 2. pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VCC 1 supply voltage GND 2 ground PROTECT 3 general-purpose protection input CTRL 4 control input ISENSE 5 current sense input DRIVER 6 gate driver output All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

4 7. Functional description 7.1 General control The contains a controller for a flyback circuit. A typical configuration is shown in Figure 3. Fig 3. typical configuration 7.2 Start-up and UnderVoltage LockOut (UVLO) Initially, the capacitor on the VCC pin, C3, is charged from the high-voltage mains via resistor R1. As long as VCC is below V startup, the IC current consumption is low (10 A typical). When VCC reaches V startup, the IC first waits for the PROTECT pin to reach the V det(protect)(l) voltage. When V det(protect)(l) is reached, the IC charges the ISENSE pin to the V start(soft) level and then starts switching. In a typical application, the auxiliary winding of the transformer takes over the supply voltage. If a protection is triggered, the controller stops switching. Depending on the protection triggered, it either causes a restart or latches the converter to an off-state. A restart protection disables the switching of the IC. The supply voltage of the IC drops to the UVLO level. When the UVLO level is reached, the IC switches to Power-down mode, where it consumes a low supply current (10 A typical). The VCC capacitor is recharged via R1 until the VCC start-up level is reached. A delayed restart is performed to lower the input power during a fault condition. Depending on the cause of the restart protection, the restart sequence that discharges and recharges the VCC capacitor is performed once or repeated three times, before switching recommences (See Figure 4). When a latched protection is triggered, the immediately enters Power-down mode. The VCC pin is clamped to a voltage just above the latch protection reset voltage (V rst(latch) +0.9V). All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

5 Fig 4. Start-up sequence, normal operation and restart sequence When the voltage on pin VCC drops below the V th(uvlo) level during normal operation, the controller stops switching. The waits for the rectified mains to charge the VCC pin using resistor R Supply management All internal reference voltages are derived from a temperature compensated on-chip band gap circuit. Internal reference currents are derived from a trimmed and temperature compensated current reference circuit. 7.4 Overvoltage protection (pin VCC) An OverVoltage Protection (OVP) circuit is connected to the VCC pin. When the V CC exceeds V th(ovp) (30 V typical) for four consecutive switching cycles, the IC triggers the latched protection. When V CC drops below V th(ovp) before count = 4 is reached, the counter is reset to zero. If a lower over voltage protection level is needed, a Zener diode can be connected between pins VCC and PROTECT. 7.5 Protection input (pin PROTECT) Pin PROTECT is a general-purpose input pin, which can be used to switch off the converter (latched protection). The converter is stopped when the voltage on this pin is pulled above V det(h)(protect) (0.8 V typical) or below V det(l)(protect) (0.5 V typical) for four consecutive converter strokes. A current of 32 A (typical) flows out of the chip when the pin voltage is V det(l)(protect). A current of 107 A (typical.) flows into the chip when the pin voltage is V det(h)(protect). The PROTECT input can be used for creating an (additional) overvoltage detection and an external OverTemperature Protection (OTP) function. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

6 A small capacitor can be connected to the pin if the protections on this pin are not used. An internal clamp of 4.1 V (typical) protects this pin from excessive voltages. 7.6 Duty cycle control (pin CTRL) Pin CTRL regulates the output power of the converter. This pin is connected to an internal voltage source of 5.4 V via an internal resistor (typical resistance: 7 k). The CTRL pin voltage sets the peak current which is measured using the ISENSE pin (see Section 7.9). At low and medium output power the switching frequency is reduced (see Section 7.11). The maximum duty cycle is limited to 80 % (typical). After eight consecutive converter strokes at maximum duty cycle the restart protection is activated. In a restart, the VCC capacitor is quickly discharged to the V th(uvlo) level and recharged to the start-up level from the high-voltage mains, before switching recommences. This occurs when the mains input voltage is removed. 7.7 Slope compensation (pin CTRL) A slope compensation circuit is integrated for CCM. The slope compensation guarantees stable operation for duty cycles exceeding 50 %. 7.8 Overpower timer A temporary overload situation is allowed. If V ctrl(ipeak) (see Figure 1) set by pin CTRL exceeds 400 mv, an internal timer is started. If the overload situation continues to exist for more than 60 ms (typical), an OverPower Protection (OPP) is triggered (see Figure 5). Fig 5. Overpower delay The enters the overpower restart mode when the overload time-out is reached. In overpower restart mode, the VCC capacitor is discharged to UVLO level and then charged to the start-up level three times before the converter switches again. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

7 7.9 Current mode control (pin ISENSE) Current mode control is used because it ensures a good line regulation. Pin ISENSE senses the primary current across external resistor R6 and compares it with an internal control voltage. The internal control voltage is proportional to the CTRL pin voltage (see Figure 6). Fig 6. Peak current control Leading edge blanking prevents false triggering due to capacitive discharge when switching on the external power switch (see Figure 7). t leb V sense(max) V ISENSE t 014aaa932 Fig 7. Leading edge blanking 7.10 Soft start-up (pin ISENSE) A soft start is made to prevent audible noise during start-up or restart. Before the converter starts, soft start capacitor C4 on the ISENSE pin is charged. When the converter starts switching, the primary peak current slowly increases when the soft start capacitor discharges through the soft start resistor (R5, see Figure 3). The soft start capacitor (C4) and resistor (R5) values chosen set the soft start time constant. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

8 7.11 Peak power, high-power, medium power and low-power operation During high-power operation, with the converter running at a 65 khz (typical) fixed frequency, the power is controlled by varying the peak current. A peak power mode is implemented to supply a short overload situation. In peak power mode, both frequency and peak current are increased. At reduced power levels, the converter enters the medium power mode where the peak current is reduced. The switching losses are reduced by lowering the switching frequency to 27.5 khz (typical). When the power is further reduced to low power, a second frequency reduction is made. In low-power operation, the switching frequency of the converter is reduced while the peak current is set to 25 % of the maximum peak current (see Figure 6 and Figure 8). Fig 8. Frequency control 7.12 Overpower or high/low line compensation Overpower compensation is built in to compensate for high/low line. The maximum continuous output power and the maximum peak power are about constant over the full mains input voltage range (see Figure 9). The rectified mains input voltage is measured by sensing the slope of the primary current from pin ISENSE. The slope information is then used to adjust the primary current by subtracting an offset V (sense)offset from the internal control voltage V ctrl(ipeak) cycle-by-cycle (NXP patent: EP01). All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

9 Fig 9. Overpower compensation 7.13 Driver (pin DRIVER) The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically 300 ma and a current sink capability of typically 750 ma. This enables a fast turn-on and turn-off of the power MOSFET for efficient operation OverTemperature Protection (OTP) Integrated overtemperature protection ensures that the IC stops switching if the junction temperature exceeds the thermal shutdown limit. OTP is a latched protection. It can be reset by removing the voltage on pin VCC. All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

10 8. Limiting values 9. Thermal characteristics Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Voltages V CC supply voltage continuous V t < 100 ms - 35 V V PROTECT voltage on pin PROTECT current limited V V CTRL voltage on pin CTRL V V ISENSE voltage on pin ISENSE current limited V Currents I VCC current on pin VCC <10% A I I(PROTECT) input current on pin 1 +1 ma PROTECT I CTRL current on pin CTRL 3 0 ma I ISENSE current on pin ISENSE ma I DRIVER current on pin DRIVER <10% A General P tot total power dissipation T amb <75C W T stg storage temperature C T j junction temperature C ESD V ESD electrostatic discharge class 1 voltage human body [1] V model changed device model V [1] Equivalent to discharging a 100 pf capacitor through a 1.5 k series resistor. Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit R th(j-a) thermal resistance from junction to ambient in free air; single layer JEDEC test board 259 K/W R th(j-c) thermal resistance from junction to case in free air; JEDEC test board 152 K/W All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

11 10. Characteristics Table 5. Characteristics T amb =25C; V CC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply voltage management (pin VCC) V startup start-up voltage V V th(uvlo) undervoltage lockout V threshold voltage V th(ovp) overvoltage V protection threshold voltage N cy(ovp) number of overvoltage protection cycles V clamp(vcc) clamp voltage on pin activated during latched - V rst(latch) V VCC protection; I CC =100A activated during latched - - V rst(latch) +3.5 V protection, I CC =1mA I CC(restart) restart supply current ma V hys hysteresis voltage V startup -V th(uvlo) V I CC(startup) start-up supply current V CC <V startup A I CC(oper) operating supply current no-load on pin DRIVER; = 2 %; excluding optocurrent no-load on pin DRIVER; = 25 %, excluding optocurrent ma ma V rst(latch) latched reset voltage V Protection input (pin PROTECT) V det(l)(protect) LOW-level detection V voltage on pin PROTECT V det(h)(protect) HIGH-level detection V voltage on pin PROTECT I O(PROTECT) output current on pin V PROTECT =V low(protect ) A PROTECT V PROTECT =V high(protect) A V clamp(protect) clamp voltage on pin PROTECT I I(PROTECT) =200A [1] V Peak current control (pin CTRL) V CTRL voltage on pin CTRL for minimum flyback peak V current R int(ctrl) internal resistance on k pin CTRL I O(CTRL) output current on pin CTRL V CTRL =1.4V ma All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

12 Table 5. Characteristics continued T amb =25C; V CC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Pulse width modulator f osc oscillator frequency peak power khz high power khz medium power khz f mod modulation frequency Hz f mod modulation frequency high power khz variation max maximum duty cycle % N cy(dmax) number of switching cycles with maximum duty cycle V start(red)f frequency reduction pin CTRL dropping to low V start voltage power V (zero) zero duty cycle voltage pin CTRL V Overpower protection t to(opp) overpower protection time-out time ms Current sense and overpower compensation (pin ISENSE) V sense(max) maximum sense V/t = 0 V/s V voltage t PD(sense) sense propagation ns delay V th(sense)opp overpower protection sense threshold voltage mv V offset(opc) overpower compensation offset voltage V ISENSE /t slope compensation voltage on pin ISENSE t leb leading edge blanking time Soft start (pin ISENSE) V sense =400mV; mv V/t =115mV/s V sense =500mV; V/t =115mV/s mv high-power mode mv/s ns I start(soft) soft start current A V start(soft) soft start voltage V CTRL = 4 V; enable - V sense(max) - V voltage R start(soft) soft start resistance k All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

13 Table 5. Characteristics continued T amb =25C; V CC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Driver (pin DRIVER) I source(driver) source current on pin DRIVER I sink(driver) sink current on pin DRIVER V O(DRIVER)max maximum output voltage on pin DRIVER Temperature protection T pl(ic) IC protection level temperature V DRIVER =2V A V DRIVER = 2 V A V DRIVER =10V A V C [1] The clamp voltage on the PROTECT pin is lowered when the IC is in Power-down mode. (latched or restart protection) All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

14 11. Application information A power supply with the is a flyback converter operating in continuous conduction mode. See Figure 10. Capacitor C3 buffers the IC supply voltage, which is powered via resistor R1 for start-up and via the auxiliary winding during normal operation. Sense resistor R6 converts the current through MOSFET S1 into a voltage on pin ISENSE. The value of resistor R6 defines the maximum primary peak current through MOSFET S1. Resistor R7 reduces the peak current to capacitor C3. Resistor R5 and capacitor C4 define the soft start time. Resistor R3 is added to prevent that soft start capacitor C4 is charged during normal operation due to negative voltage spikes across current sense resistor R6. Capacitor C2 is added to reduce noise on the CTRL pin. Resistor R4 is required to limit the current spikes to pin DRIVER because of parasitic inductance of current sense resistor R6. Resistor R4 also dampens possible oscillations of MOSFET S1. Adding a bead on the gate pin of MOSFET S1 can be required to prevent local oscillations of the MOSFET. D1 C1 68 μf R4 S1 D3 C5 VCC 1 6 DRIVER 10 Ω R5 T1 R1 1 MΩ GND PROTECT 2 3 IC 5 4 ISENSE CTRL R3 1 kω O1 22 kω C4 220 nf Z1 O1 C3 4.7 μf R2 200 kω C2 1 nf R Ω D2 R7 10 Ω aaa Fig 10. application diagram All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

15 12. Package outline Plastic surface-mounted package (TSOP6); 6 leads SOT457 D B E A X y H E v M A Q pin 1 index A A 1 c L p e b p w M B detail X mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e H E Lp Q v w y mm OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT457 SC Fig 11. SOT457 (TSOP6) All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

16 13. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes v Product data sheet - v.2 Modifications: R4 value changed in Figure 10 application diagram has been updated. v Product data sheet - v.1 v Objective data sheet - - All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev August of 19

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19 16. Contents 1 General description Features and benefits Applications Ordering information Block diagram Pinning information Pinning Pin description Functional description General control Start-up and UnderVoltage LockOut (UVLO) Supply management Overvoltage protection (pin VCC) Protection input (pin PROTECT) Duty cycle control (pin CTRL) Slope compensation (pin CTRL) Overpower timer Current mode control (pin ISENSE) Soft start-up (pin ISENSE) Peak power, high-power, medium power and low-power operation Overpower or high/low line compensation Driver (pin DRIVER) OverTemperature Protection (OTP) Limiting values Thermal characteristics Characteristics Application information Package outline Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 16 August 2012 Document identifier: