MSTM-S3-T2 Stratum 3 Timing Module

Transcription

1 MSTM-S3-T2 Stratum 3 Timing Module 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: Application The Connor-Winfield MSTM-S3-T2 Simplified Control Timing Module acts as a complete system clock module for Stratum 3 timing applications in accordance with GR- 1244, Issue 2 and GR-253, Issue 3. Connor Winfield s Stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. Features 5V Miniature Timing Module Redundant 8kHz References 40 sec., Filtered, Hold Over History.37 ppm Hold Over During Initial 24 Hours 4.6 ppm Free Run Accuracy Hitless Reference Switching Bulletin TM053 Page 1 of 20 Revision 00 Date 14 MAY 03 Issued By MBatts

2 General Description The Connor-Winfield Stratum 3 Simplified Control Timing Module acts as a complete system clock module for general Stratum 3 timing applications. Full external control input allows for selection and monitoring of any of four possible operating states: 1) Holdover, 2) External Reference #1, 3) External Reference #2, and 4) Free Run. Table #1 illustrates the control signal inputs and corresponding operational states. In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=0, B=1) results in an output signal that is phase locked to External Reference Input #2. Holdover mode operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) lockedsignal input values and the holdover performance of the MSTM. Free Run mode operation (A=0, B=0) is a guaranteed output of 4.6 ppm of the nominal frequency. Alarm signals are generated at the Alarm Output during Holdover and Free Run operation. Alarm Signals are also generated by loss-of-lock, loss of Reference, and by a Tune-Limit indication from the PLL. A Tune-Limit alarm signal indicates that the OCXO tuning voltage is approaching within % the limits of its lock capability and that the External Reference Input may be erroneous. A high level indicates an alarm condition. Real-time indication of the operational mode is available at unique operating mode outputs on pins 1-4. Control loop 0.1 Hz filters effectively attenuate any reference jitter, smooth out phase transients, comply with wander transfer and jitter tolerances. Functional Block Diagram Figure 1 CNTL A CNTL B Ex Ref 1 Ex Ref 2 Mode Control Reference Select DAC Filters Tuning Voltage Monitor Free Run Ref 1 Ref 2 Holdover Phase Comparator DAC FIFO PLL TVL PLL TVL Free Run Holdover LOL/LOR Stratum 3 OCXO Stratum 3 TCXO Alarm Out SYNC_OUT CLK_OUT Table 1 Function Control Table CNTL CNTL Operational Ref 1 Ref 2 Hold Over Free Run PLL_TVL Alarm Out A B Mode 0 0 Free Run (Default Mode) External Normal Reference Tune Limit #1 LOR + LOL External Normal Reference Tune Limit #2 LOR + LOL Hold Over Absolute Maximum Rating Table 2 Symbol Parameter Minimum Nominal Maximum Units Notes V CC Power Supply Voltage Volts 1.0 V I Input Voltage -0.5 V CC Volts 1.0 T s Storage Temperature deg. C 1.0 Data Sheet #: TM053 Page 2 of 20 Rev: 00 Date: 5 / 14 / 03

3 Recommended Operating Conditions Table 3 Symbol Parameter Minimum Nominal Maximum Units Notes V cc Power supply voltage Volts V IH High level input voltage - TTL 2.0 V CC Volts V IL Low level input voltage - TTL Volts t IN Input signal transition - TTL 250 ns C IN Input capacitance 15 pf V OH High level output voltage, Volts 2.0 I OH = -4.0mA, V CC = min. V OL Low level output voltage, 0.4 Volts I OL = 12.0 ma, V CC = min. t TRANS Clock out transition time 4.0 ns t PULSE 8kHz input reference pulse 30 ns width( positive or negative) T OP Operating temperature 0 70 C Specifications Table 4 Parameter Specifications Notes Frequency Range (SYNC_OUT) 8 khz to 125 MHz Frequency Range (CLK_OUT) 8 khz to MHz Supply Current 250 ma typical, 400 ma during warm-up (Maximum) Timing Reference Inputs Dual 8 khz references 3.0 Jitter, Wander and Phase Transient Tolerances GR-1244-CORE , GR-253-CORE Wander Generation GR-1244-CORE 5.3, GR-253-CORE Wander Transfer GR-1244-CORE 5.4 Jitter Generation GR-1244-CORE 5.5, GR-253-CORE Jitter Transfer GR-1244-CORE 5.5, GR-253-CORE Phase Transients GR-1244-CORE 5.6, GR-253-CORE Free Run Accuracy 4.6 ppm over T OP Hold Over Stability ±0.37 ppm for initial 24 hrs 4.0 Initial Offset ±0.05 ppm Temperature ±0.28 ppm Drift ±0.04 ppm Maximum Hold Over History 40 seconds Pull-in/ Hold-in Range ±4.6 ppm minimum 5.0 Lock Time <0 sec. PLL_TVL Alarm Limit Extreme % ranges of Pull-in/Hold-in Range NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage to the device. Operation beyond Recommended Conditions is not implied. 2.0: Logic is 3.3V CMOS 3.0 GR-1244-CORE : Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE, : Pull-in Range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into synchronization with the reference Data Sheet #: TM053 Page 3 of 20 Rev: 00 Date: 5 / 14 / 03

4 Table 5 Pin # Connection Description Pin Description 1 HOLD OVER Indicator output. High output when Hold Over mode is selected by control pins. 2 REF 1 Indicator output. High output when Ref 1 mode is selected by control pins. 3 REF 2 Indicator output. High output when Ref 2 mode is selected by control pins. 4 FREE RUN Indicator output. High output when Free Run mode is selected by control pins. 5 GND Ground 6 ALARM _OUT Alarm output. High output if module is in Free Run, or Hold Over, or LOR, or LOL, or PLL_TVL mode. 7 CNTL A Mode control input 8 CNTL B Mode control input 9 PLL_TVL Tuning Voltage Limit alarm output. High output when Sync_Out is near the extreme % ranges of the Pull-in/Hold-in range. GND Ground 11 SYNC_OUT Primary timing output signal. Signal is synchronized to reference. 12 GND Ground 13 CLK_OUT Stratum 3 TCXO output (non-synchronized output, Frequency = SYNC_OUT) 14 GND Ground 15 EX_REF_2 External Input Reference #2 16 GND Ground 17 EX_REF_1 External Input Reference #1 18 V CC +5V dc supply Typical Application Figure 2 BITS System Signal Input Select #1 #N MUX Y Timing Card #1 CW s STM/MSTM module Line Card #1 CW s SCG 2500/4500 Clockout S RCV #1 #N MUX Y Timing Card #2 CW s STM/MSTM module Line Card #N CW s SCG 2500/4500 Clockout S RCV System Select Data Sheet #: TM053 Page 4 of 20 Rev: 00 Date: 5 / 14 / 03

5 1.0 E E-9.0 E E-9 1.0E E-9.0 E-9 1.0E -9 TDEV GR1244-Fig5.1 GR1244-Fig5-3 Sample MT IE Data for STM-S3/MSTM-S3 Sample Wander Generation (TDEV) for S T M/MS TM -S 3 Typic al respo ns e seco nd te st - Jit ter ap plied (2 Hz) re f da te A P R kdh T ypical resp on se seco nd test - J itte r applie d ( 2 H z) re f date APR kd h 0.0E-3 1.0E +0.0 E+0 0.0E+0 1.0E +3.0E+3 Observation Time (s) 0.0 E-12.0 E-3 0.0E-3 1.0E +0.0 E+0 0.0E+0 1.0E +3 Copyright Co nno r-w infie ld a lllrig h ts re s e rv e d Integ ration Time (se c) MTIE M as k (A ) M as k (B ) Mas k GR Copyright C o nno r- Winf ie ld a ll rig hts re s e rv e d Typical Module Test Setup Figure 3 Vcc Stratum 1 Reference 1 - Hold Over 5 Vdc Ref Ref Free Run Ext. Ref 1-17 Gnd - 16 Ext. Ref khz Stratum 1 Traceable Signal Vcc 5 - Gnd 6 - Alarm Out 7 - Cntl A 8 - Cntl B Gnd - 14 Clk_Out - 13 Gnd - 12 Sync_Out - 11 Probe Probe Oscilloscope Frequency Counter MHz 9 - PLL_TVL Gnd - Top View Probe Probe Oscilloscope Frequency Counter Typical System Test Setup Figure 4 This device supplies system time information. It can be thought of as supplying "absolute time" reference information GPS or LORAN Timing Source Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX MHz MTI E (s Target System Under Test External Reference Input MHz External Reference Input Arbitrary Waveform Generator Arbitrary Waveform Generator [Noise Source] DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 khz clock RZ with noise modulation Noise Modulation Input Clock or BITS logic level clock input (TTL, CMOS, etc.) Timing Card Line Card Timing Card OC-3 Line Card OC-12 Line Card OC-48 Line Card DS-1 Line Card TD EV (se c Standards Compliance Documents MTIE, TDEV, Wander Transfer, and Wander Generation Plots DS1 rate [1.544 MHz] BITS Bipolar MHz Time-stamped ensemble based on absolute time reference (MHz input) MHz Tektronix SJ300E DS-1, OC-3, OC-12 electrical or optical signals External Reference HP533A Input Modulation Analyzer / Time Interval Analyzer Phase Error data output External Reference Input TEKTRONIX SJ300E Wander Analyzer data (IEEE-488) IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer Data Sheet #: TM053 Page 5 of 20 Rev: 00 Date: 5 / 14 / 03

6 MSTM-S3-T2 Typical Current Draw Figure Current (Amps) Time (sec) MSTM-S3-T2 Typical Phase Noise Plot Figure 6 Data Sheet #: TM053 Page 6 of 20 Rev: 00 Date: 5 / 14 / 03

7 MSTM-S3-T2 Typical Phase Gain Figure Phase Gain (db) Reference Modulation Frequency (Hz) MSTM-S3-T2 Typical Hold Over Stability over Temperature Figure Frequency Offset (ppb) Temperature (C ) Data Sheet #: TM053 Page 7 of 20 Rev: 00 Date: 5 / 14 / 03

8 Typical Wander Generation MTIE Figure 9 00 GR1244, Fig 5-5 GR253, Fig 5-17 Jittered Reference Pristine Reference Temperature Stressed Reference 0 MTIE (ns) Observation Time (sec.) Typical Wander Generation TDEV Figure 0 GR1244, Fig 5-4 & GR253, Fig 5-18 Jittered Refe re nce Pristine Reference Temperature Stressed Reference TDEV (ns) Integration Time (sec.) Data Sheet #: TM053 Page 8 of 20 Rev: 00 Date: 5 / 14 / 03

9 Typical Calibrated Wander Transfer TDEV Figure TDEV (ns) 0 TDEV (ns) GR1244, Fig Integratio n T im e (S e c.) Typical Reference Switch MTIE Figure GR1244, Fig 5-7, Stratum 2/3E GR1244, Fig 5-7, Stratum 3/4E GR-253, Fig. 5-19, Requirement MTIE (ns) 00 MTIE (ns) Observation Time (sec) Data Sheet #: TM053 Page 9 of 20 Rev: 00 Date: 5 / 14 / 03

10 Typical Entry Into Hold Over MTIE Figure MT 0 GR-1244 Objective, Fig. 5-8 GR-1244 Requirement, Fig. 5-8 GR-253, Fig. 5-19, Requirement Typical MTIE Observation Time (seconds) Typical Return from Hold Over MTIE Figure M T IE (n 0 G R R equire m e n t, F ig. 5-7 G R -253, Fig. 5-19, R equirem ent TypicalM T IE O bservation Tim e (sec.) Data Sheet #: TM053 Page of 20 Rev: 00 Date: 5 / 14 / 03

11 Typical 1us Phase Transient TIE Figure TIE (ns) Time (sec) Typical Phase Transient MTIE Figure MT 0 GR-253, Fig. 5-19, Requirem ent MTIE (ns) Observation Time (sec) Data Sheet #: TM053 Page 11 of 20 Rev: 00 Date: 5 / 14 / 03

12 MSTM-S3-T2 Mode Indicator Delay Figure 17 Change in Operational Mode Operational Mode Indicator t m 40 µsec < t m < 0 µsec Tuning Voltage Limit Alarm Timing Diagram Figure 18 TVL Limit High Frequency Sync_Out (Nominal Frequency) TVL Limit Low Frequency TVL Alarm & Alarm Out t 0 < t < 1sec *The DAC is updated only when the output changes level. The maximum update rate is 8 khz Data Sheet #: TM053 Page 12 of 20 Rev: 00 Date: 5 / 14 / 03

13 Loss of Reference Timing Diagram Figure 19 External Reference Input Alarm ton A toff A 50 µsec < taon < 250 µsec 1 sec < t off < 2 sec A *Drawing is not to scale Solder Clearance Figure " MAX..020".030" PIN LAND ALL SOLDER AND/OR WIRE TAGS SHALL NOT EXTEND MORE THAN.020" BELOW PC BOARD BOTTOM SURFACE Data Sheet #: TM053 Page 13 of 20 Rev: 00 Date: 5 / 14 / 03

14 Data Sheet #: TM053 Page 14 of 20 Rev: 00 Date: 5 / 14 / 03

15 MECHANICAL OUTLINE: The mechanical outline of the MSTM-S3-IP is shown in Figure 23. The board space required is x (max). The pins are.040 in diameter and are.160 (max) in length. The unit is spaced off the PCB by.035 (max) shoulders on the pins. Due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked. PAD ARRAY AND PAD SPACING: The pins are arranged in a dual-in-line configuration as shown in Figure 16. There is.2 space between the pins in-line and each line is separated by 1.6. See Figures 21 & 23 and Table 6. PAD CONSTRUCTION: The recommended pad construction is shown in Figure 21. For the pin diameter of.040 a hole diameter of.055 is suggested for ease of insertion and rework. A pad diameter of.150 is also suggested for support. This leaves a spacing of.050 between the pads which is sufficient for most signal lines to pass through. SOLDER MASK: A solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. See Table 6 and Figure 22. VIA KEEP OUT AREA: It is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. It is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. See Figure 21. GROUND AND POWER SUPPLY LINES: Power specifications will vary depending primarily on the temperature range. At wider temperature ranges starting at 0 to 70 deg. C., an ovenized oscillator, OCXO, will be incorporated. The turn-on current for an OCXO requires a peak current of about.4a for about a minute. The steady state current will the vary from ma depending on the temperature. It is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. The other four ground pins, 12, 14, and 16 are intended for signal grounds. POWER SUPPLY REGULATION: Good power supply regulation is recommended for the MSTM-S3-T2 The internal oscillators are regulated to operate from volts. Large jumps within this range may still produce varying degrees of wander. If the host system is subject to large voltage jumps due to hot-swapping and the like, it is suggested that there be some form of external regulation such as a DC/DC converter. SOLDERING RECOMMENDATIONS: Due to the sensitive nature of this part, hand soldering of the pins is recommended after reflow processes. WASHING RECOMMENDATIONS: The MSTM-S3-T2 is not in a hermetic enclosure. It is recommended that the leads be hand cleaned after soldering. Do not completely immerse the module. MODULE BAKEOUT: Do not bakeout the MSTM-S3-T2 Data Sheet #: TM053 Page 15 of 20 Rev: 00 Date: 5 / 14 / 03

16 Recommended Footprint Dimensions Figure 21 Characteristic Measurements Table 6 Characteristic Item Measurement (inches) Pad to Pad Spacing Solder pad top O.D Solder pad top I.D Solder pad bottom O.D Solder pad bottom I.D Solder mask top dia Solder mask bottom dia Pin row to row spacing Side Assembly View Figure 22 TOP SIDE SOLDER RESIST (OVER PAD) PCB BOTTOM SIDE SOLDER RESIST (UP TO PAD) SIDE VIEW Data Sheet #: TM053 Page 16 of 20 Rev: 00 Date: 5 / 14 / 03

17 Package Dimensions Figure 23 J H "A-A" L M K F B DETAIL "A-A" D E C A PIN 1 G (16) A (MAX) B (MAX) C (MAX) D E F G H (MAX) J (MAX) K (MAX) L M (50.93) (50.93) (15.06) (40.64) (5.08 (5.08) (5.08) (4.06) (0.76) (3.18) (1.98) (1.02) DIMENSIONS IN PARENTHESIS ARE IN MILLIMETERS Data Sheet #: TM053 Page 17 of 20 Rev: 00 Date: 5 / 14 / 03

18 Data Sheet #: TM053 Page 18 of 20 Rev: 00 Date: 5 / 14 / 03

19 Data Sheet #: TM053 Page 19 of 20 Rev: 00 Date: 5 / 14 / 03

20 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: Revision Revision Date Note 00 5/14/03 Final Release