Analog Communication Laboratory Manual. Kavya Manohar

Transcription

1 Analog Communication Laboratory Manual Kavya Manohar March 19, 2018

2 2 2014, Kavya Manohar. This work is licensed under a Creative Commons Attribution-Share Alike 4.0 India License. See for more details. This is a laboratory manual for analog communication experiments. It mostly adheres to the syllabus of the University of Calicut. This project is hosted at: Contact: kavya.thottingal@gmail.com

3 Preface This laboratory manual has been prepared as a guideline to help students of undergraduate courses to carry out basic experiments in analog communication in the laboratory. This book is written in a way that a student with basic understanding on electronic circuit theory can learn the theory and experiment the basics of analog communication techniques. Along with circuit components, introductions, an appendix section which discuss the data sheet details of that component is provided. Every experiment is explained with associated circuit diagrams, which were drawn using geda schemetic editor. Signal waveforms associated with the experiments were simulated in octave and given along with the experiment. Data, documents or diagrams used in the book which were taken from external sources are linked to the original sources as footnotes. This is a work in progress version of the laboratory manual. Suggestions on improvement in conceptual clarity, diagrams, typography are most welcome. Share whatever you feel about the book- it is yours. Kavya Manohar 3

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5 Acknowledgements Thank you for going through this work. Thanks in advance for your valuable feedbacks that would help improve this book. Thanks a lot for the lectures and notes of Prof. Madhavan Nair, Retired Professor, College of Engineering Trivandrum, which helped me to draft this manual. Thanks to my colleagues at Aryanet Institute of Technology for their encouragement and support. Special thanks to Sathyan P. for being with me experimenting in the laboratory. Thanks to my students who helped me improve the contents with timely comments. Thanks to all free knowledge enthusiasts- especially to those who have created and shared electronics and communication engineering related contents to various public domain sources. Your efforts have helped a lot in the making of this book. Thanks Santhosh, for what you are to me. Kavya Manohar

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7 Contents 1 Introduction to Analog Communication 11 2 Tuned Amplifier using IFT 13 3 AM generation using IFT 17 4 AM Detection with Automatic Gain Control 21 5 PAM Generation and Demodulation 27 6 PWM Generation and Demodulation 33 7 PPM Generation and Demodulation 37 8 DSB-SC using multiplier IC AD AM generation and Demodulation using AD FM using Study of PLL IC CD FM - Modulation and Demodulation using PLL Mixer Circuit using BJT 69 A Quick Reference: Component Details 73 A.1 Intermediate Frequency Transformer A.2 BJT BF194/ A.3 BJT BC A.4 CD CMOS switching IC A.5 AD Multiplier IC A Timer IC A.7 CD PLL IC

8 8 CONTENTS

9 List of Figures 2.1 Circuit Diagram for IF Tuned Amplifier Circuit Diagram for AM generation using IFT Effect of modulation index on AM Detector circuit with Simple AGC AM with message envelope Intermediate stage of demodulation Output waveforms from demodulation circuit PAM modulation using transistor PAM modulation using switching IC PAM generation and demodulation circuuit PAM generation using CD PWM generation and demodulation circuuit PPM generation and demodulation circuuit DSB-SC signal in blue, original message shown in red Message and carrier signals AM(DSB-FC) and Demodulation stage-1 signals Circuit for DSB-SC generation and detection using AD633 multiplier IC Circuit for AM generation and detection using AD633 multiplier IC Message and carrier signals AM(DSB-FC) and Demodulation stage-1 signals Circuit to implement frequency modulation using Message, Carrier and frequency modulated waveforms Internal block Diagram of IC CD Circuit Diagram to determine lock range and capture range

10 12.1 Circuit for FM generation and detection using CD4046 PLL IC FM generation and detection waveforms Circuit Diagram for Mixer circuit using BJT A.1 Schematic diagram of intermediate frequency transformer A.2 Internal details of IF CAN A.3 Physical construction of IF CAN A.4 Pinout Diagram of 4016 switching IC A.5 Functional Block Diagram for AD633 multiplier IC A.6 Pin-out diagram of 555 IC A.7 Block diagram of a PLL A.8 Pinout diagram of CD4046 PLL IC

11 Chapter 1 Introduction to Analog Communication [1]Communication is the transfer of information from one place to another. Radio communication uses electrical energy to transmit information. The transmitted information is the intelligence signal or message signal. Message signals are in the Audio Frequency (AF) range of low frequencies from about 20 Hz to 20 khz. The Radio Frequency (RF) is the carrier signal. Carrier signals have high frequencies that range from 10 khz up to about 1000 GHz. A radio transmitter sends the low frequency message signal at the higher carrier signal frequency by combining the message signal with the carrier signal. Modulation is the process of changing a characteristic of the carrier signal with the message signal. In the transmitter, the message signal modulates the carrier signal. The modulated carrier signal is sent to the receiver where demodulation of the carrier occurs to recover the message signal. IMPORTANT TERMS Electromagnetic waves - the radiant energy produced by oscillation of an electric charge. Message signal - any signal that contains information; it is also called the intelligence signal. Audio Frequency (AF) - frequencies that a person can hear. AF signals range from about 20 Hz to 20 khz. Radio Frequency (RF) - the transmission frequency of electromagnetic (radio) signals. RF frequencies are from about 300 khz to the 1,000,000 khz range. Carrier signal - a single, high-frequency signal that can be modulated by a message signal and transmitted. 11

12 12 CHAPTER 1. INTRODUCTION TO ANALOG COMMUNICATION Modulation - the process of combining the message signal with the carrier signal that causes the message signal to vary a characteristic of the carrier signal. Demodulation - the process of recovering or detecting the message signal from the modulated carrier frequency. Amplitude Modulation (AM) - the process of combining the message signal with the carrier signal and the two sidebands: the lower sideband and the upper sideband. Frequency Modulation (FM) - the process of combining the message signal with the carrier signal that causes the message signal to vary the frequency of the carrier signal. Phase Modulation (PM) - the process of combining the message signal with the carrier signal that causes the message signal to vary the phase of the carrier signal. Angle modulation - the process of combining the message signal with the carrier signal that causes the message signal to vary the frequency and/or phase of the carrier signal. Balanced modulator - an amplitude modulator that can be adjusted to control the amount of modulation. Double-Sideband (DSB) - an amplitude modulated signal in which the carrier is suppressed, leaving only the two sidebands: the lower sideband and the upper sideband. Mixer- an electronic circuit that combines two frequencies. Phase detector - an electronic circuit whose output varies with the phase differential of the two input signals. Envelopes- the waveform of the amplitude variations of an amplitude modulated signal. Sidebands - the frequency bands on each side of the carrier frequency that are formed during modulation; the sideband frequencies contain the intelligence of the message signal. AM - an amplitude modulated signal that contains the carrier signal and the two sidebands: the lower sideband and the upper sideband. Bandwidth - the frequency range, in hertz (Hz), between the upper and lower frequency limits. Harmonics - signals with frequencies that are an integral multiple of the fundamental frequency.

13 Chapter 2 Tuned Amplifier using IFT Aim To design and implement a tuned frequency amplifier using BJT and IFT. Theory 2π LC Intermediate frequency amplifiers are tuned voltage amplifiers used to amplify a particular frequency. Its primary function is to amplify only the tuned frequency with maximum gain and reject all other frequencies above and below this frequency. This type of amplifiers are widely used in intermediate frequency amplifiers in AM super heterodyne receivers, where intermediate frequency is usually 455 khz. In common emitter voltage amplifier circuit (emitter bypassed), the voltage gain is A V = R C R L r e, where R C is the collector resistance in the circuit, R L is the load resistance and r e is the internal emitter resistance. In tuned voltage amplifier the collector resistance is replace by a tuned load upon which the gain is dependant. For a parallel resonating circuit cosisting of a capacitor, C and an inductor,l the impedance Z o is maximum at resonant frequency, 1 f o =. So an amplifier with tuned load will have maximum gain at resonant frequency. In practical tuned amplifier circuits, an intermediate frequency transformer(ift) is used as tuned load. IFT is tuned to standard 455 khz audio frequency, (See A.1). The quality factor of the circuit is given by Q = Design f o Bandwidth. Inorder to design a common emitter amplifier operating at high frequency, one can use a high frequency transistor like BF194, BF195, BF494, BF495 or 2N

14 14 CHAPTER 2. TUNED AMPLIFIER USING IFT Choose transistor BF 194/195. For its datasheet See A.2, Let V CC be 10% more than the required output amplitude, ie. 10V. V CC = 12 V (2.1) I c < 10% of I Cmax = 10% of 30 ma = 3mA (2.2) Let I c = 1mA. Let the stability factor of the circuit be, S = 10 (2.3) Under dc conditions, the primary dc resistance of the IFT is very small(< 5Ω). So dc voltage drop across collector circuit is very low, approximately zero. For class A mode of operation set, V CE = V CC 2 = 6V (2.4) Design of Emitter resistance The voltage across emitter resistance is, Hence Thus V RE = V CC V CE = 12V 6V = 6V (2.5) Choose standard value of R E = 5.6 kω. I E I C (2.6) I E = 1mA (2.7) R E = V RE = 6V = 6kΩ (2.8) I E 1mA Design of Potential divider biasing The Stability factor S=10. Assuming R B is the effective resistance at the base, S = 10 = 1 + R B R E (2.9) R B = 9R E = 50.4kΩ (2.10) R B = R 1 R 2 = R 1R 2 R 1 + R 2 = 50.4kΩ (2.11) The voltage at the base of the transistor is V B = V E + V BE = V RE + V BE = 6V + 0.6V = 6.6V (2.12) This is the voltage across R 1. V R1 = V CC R 2 R 1 + R 2 = 6.6V (2.13)

15 15 From equations 2.11 and 2.14, R 2 = 6.6V R 1 + R 2 12V = 0.55 (2.14) R 1 = 91.4 kω 82 kω and R 2 = 100 kω (2.15) Choose load resistor as R L = 100kΩ (2.16) Design of capacitors The capacitors C 1, C 2 and C E can be designed based on lower cut-off frequency at -3 db point. Since this frequency is much lower than 300 khz, Choose low values of capacitance like C 1 = C 2 = C E = 1 µf (2.17) Circuit Diagram See Figure 2.1 for circuit diagram. Figure 2.1: Circuit Diagram for IF Tuned Amplifier

16 16 CHAPTER 2. TUNED AMPLIFIER USING IFT Procedure Assemble the circuit as shown in the circuit diagram. Obtain output from output-1 or output-2 terminal as in the circuit diagram. Give input signal, which is a sinewave of frequency variable from 300 khz to 600 khz and amplitude 50 mv pp. Observe the output waveform on a CRO. Enter the details of input and output waveforms on the tabular column shown. Calculate gain A V by varying f in.(a V = Voutpp V inpp ) Plot frequency response characteristics with f in (khz) along x-axis and Gain db = 20 log A v along y-axis. Find the resonant frequency, 3-dB bandwidth and hence the Q-factor. Observation f in (khz) log 10 f in V outpp (V ) A v = Voutpp V inpp Gain db = 20 log A v Result A tuned amplifier was implemented using IFT. Its maximum gain= Resonant frequency, f 0 = Band-width, BW = Q-factor= f0 BW

17 Chapter 3 AM generation using IFT Aim To design and set-up an AM generator using BJT and IFT and measure the modulation index from the observed output waveform. Theory Any amplifier can be converted into a sinusoidal oscillator if Barkhausen conditions are satisfied. So tuned amplifier in chapter 2 can be converted ito a high frequency oscillator for generating carrier wave by providing a positive feedback after removing the input and the load resistor R L. Inorder to obtain the feedback signal to the base, the terminal-1 of the IFT primary coil is used. It is 180 out of phase with the signal at collector, ie. terminal-2 of IFT primary winding. The collector signal is already 180 out of phase with the input signal at base of BJT. Thus the feed back signal from terminal-1 of the IFT to the base of BJT is in phase with the signal at the base. The feedback capacitor is chosen to be low to avoid additional phase shift. The circuit now works as an oscillator generating a signal of frequency of around 455 khz. Its amplitude, E c can be adjusted by varying the potentiometer connected in series with the emitter resistance and frequency, f c by tuning the IFT. e c = E c sin(2πf c t) (3.1) The carrier thus generated can be modulated using an audio frequency message signal by connecting it at the emitter of the transistor. It can be of frequency varying from 1kHz to 5 khz. The amplitude can be varied in the rage of 1 V to 10 V which changes the modulation index. The modulation index can also be varied by adjusting the carrier amplitude with the potentiometer connected at the emitter. 17

18 18 CHAPTER 3. AM GENERATION USING IFT Figure 3.1: Circuit Diagram for AM generation using IFT The ratio of the maximum amplitude of the modulating signal voltage to that of the carrier voltage is termed as modulation index. This is represented as m = Em E c. For both carrier and message being sinusoidal, the modulation index will be m = Emax Emin E max+e min where E max and E min are respectively the maximum and minimum height of the positive side of modulated signal. Design The basic biasing of the transistor is as discussed in the chapter 2. To make the circuit an oscillator, remove input signal and the load. Positive feed back signal to base is taken from terminal-1 of IFT and given to base through a small capacitance of C 1 = 100pF. The emitter resistance can be raplaced with a fixed resistance of R E = 1kΩ in series with a potentiometer of R 3 = 5kΩ. The modulating signal is connected through a capacitor of C E = 10µF. Circuit Diagram The circuit diagram is shown in Fig. 3.1

19 19 Procedure 1. Set up the circuit after verifying the condition of components. 2. Feed AF modulating signal (say, f m = 1kHz and E m = 5mV ) using a function generator. 3. Adjust amplitude and frequencies of the AF and carrier signals and observe amplitude modulated waveform on the CRO. 4. Fix f m and f c. Note down E max and E min of the AM signal and calculate modulation index according to the formula, m = E max E min E max + E min. (3.2) Here E max is the maximum of the positive envelope of the carrier and E min is the minimum of the positive envelope of the carrier. 5. Repeat for different values of E m and E c. Observe the AM waveforms for different values of m. 6. Plot the waveforms on a graph sheet. 7. Fill in the observation column Observation Figure. 3.2 shows the effect of modulation index on the resultant AM wave 1 E min E max m = Emax Emin E max+e min Result Implemented the AM modulation circuit using BJT and IFT. Tabulated the modulation index by varying the amlitudes of message and the carrier. 1 Image source: Wave-hm-64.svg

20 20 CHAPTER 3. AM GENERATION USING IFT Figure 3.2: Effect of modulation index on AM

21 Chapter 4 AM Detection with Automatic Gain Control Aim To demodulate the message content from AM signal. Also detect the automatic gain control signal from the received AM signal. Theory A simple AM demodulator is a diode envelope detector. It can be implemented by a simple diode envelope detector to eliminate the negative half of the carrier envelope followed by a simple RC filter to remove the high frequency carrier. The result will be the low frequency envelope which is the demodulated message. A point contact diode with low junction capacitance is used in the circuit as it is has to rectify high frequency carrier. It offers low impedence at high frequency. The RC elements connected after the diode acts as a filter. It acts as a lowpass filter which eliminates high frequency carrier at the same time it retains the low frequency message signal. Thus the output of the filter contains the low fequency modulating signal with a dc offset. The dc offset voltage is proportional to the strength of the modulated signal received by the receiver in a transmission reception system, which inturn is proportional to the strength(amplitude) of the carrier. This dc value may be used for automatic gain control(agc) of intermediate frequency(if) amplifier stages. The Automatic gain control compensates for minor variations in the received RF signal level. The AGC circuit automatically increases the receiver gain for weak RF input levels and automatically decreases the receiver gain when strong RF signal is received 1. 1 For detailed explanation, refer to Chapter 5 of [3] 21

22 22 CHAPTER 4. AM DETECTION WITH AUTOMATIC GAIN CONTROL Simple AGC: It is implemented in the form of a circuit which extracts the dc offset voltage which is present along with the demodulated message. This volatge is fed as degenerative or negtive feedback to the control the gain of superheterodyne receivers. Delayed AGC: In simple AGC circuits even if the signal level received is low, the AGC circuit operates and the overall gain of the receiver gets reduced. To avoid this situation, a delayed AGC circuit is used. In this case AGC bias voltage is not applied to amplifiers, until signal strength has reached a predetermined level after which AGC bias is applied like simple AGC. Design After the positive envelope detector, a properly designed low pass filter is added to filter out the high frequency carrier and to retain the low frequency modulating signal. This signal contains a dc level also which can be used for automatic Gain Control (AGC) for the IF amplifier stages of a superhetrodyne receiver. Let the carrier frequency be f c = 455 khz and maximum modulating signal frequency be f m = 10 khz Inorder to design a lowpass filter with upper cutoff frequency 10 khz, f H = 1 2πR d C d (4.1) 1 10 khz = (4.2) 2πR d C d Select C d = 0.001µF. Then R d = 16.1kΩ. Choose R d = 15kΩ or 22kΩ standard resistor values. Make a π filter (for better performance) using these R d and C d values. This completes the envelope detector part. AGC Circuit: The AGC lowpass filter R a and C a is seected in such a way as to eliminate full ac from the output and get a pure dc AGC voltage. Hence assuming a cutoff frequency of 10 Hz to eliminte the fluctuations, 10Hz = 1 2πR a C a (4.3) Assuming C a = 1µF, we get R a = 22kΩ The actual modulating signal can be obtained by filtering out the dc components using a high value caacitance like 10µF. Circuit Diagram The detector circuit with simple AGC is shown in Figure. 4.1.

23 23 Figure 4.1: Detector circuit with Simple AGC Procedure 1. Connect the diode to the output of AM signal(see Figure. 4.2) as in the circuit diagram Fig Connect load resistance R L and observe the outputwaveform on a CRO and plot it. 3. Connect the π filter circuit of R d and C d and observe the output waveform on a CRO and plot it. 4. Obtain the demodulated output without dc offset by connecting capacitor C 3. Observe it on a CRO and plot it. 5. Connect the lowpass filter using C a and R a for obtaining AGC voltage level. Observe it on a CRO and plot it. 6. Vary the modulation index by changing carrier or modulating signal levels. Plot the simple AGC charateristics with modulation index on x-axis and AGC voltage level on y-axis. 7. Eliminte the dc offset and observe the modulating signal from the 10µF capacitor as shown in the circuit diagram.

24 24 CHAPTER 4. AM DETECTION WITH AUTOMATIC GAIN CONTROL Observation Figure 4.2: AM with message envelope The following are the observed results of the experiment. See Figure. 4.3 and Figure. 4.4 for the waveforms of intermediate and final stages. Result Demodulation circuit was designed and implemented with simple AGC.

25 25 Figure 4.3: Intermediate stage of demodulation Figure 4.4: Output waveforms from demodulation circuit

26 26 CHAPTER 4. AM DETECTION WITH AUTOMATIC GAIN CONTROL

27 Chapter 5 PAM Generation and Demodulation Aim To set-up and implement circuits to carry out pulse amplitude modulation. To design demodulationg circuits to detect the message from pulse amplitude modulated wave. Theory Pulse amplitude modulation is a kind of digital modulation technique in which analog message signal is sampled at constant frequency - carrier frequency. A pulse of specified duration is used to sample the message signal. When the pulse is on, the message is sampled and when it is off no message is sampled. This is a basic step in the digitization of analog message signals. The circuits to be implemented in this experiment does a kind of natural sampling. 1. Waveforms showing pulse carriers whose amplitude is modulated buy message is shown in Figure 5.1 and??. A simple way to implement this is to allow the message to be fed as the input to a switch and the switch ON/OFF time is controlled by the pulses at sampling frequency. The demodulation of PAM waveform can be implemented by using a lowpass filter which passes message signal frequenies but blocks the carrier signal. 1 For more on natural sampling, refer Digital Transmission [3] 27

28 28 CHAPTER 5. PAM GENERATION AND DEMODULATION Design Figure 5.1: PAM modulation using transistor PAM using transistor as a switch One technique to implement PAM is to use transistr in switching mode. The flow of current from collector to emitter in a bipolar junction transistor is controlled by the voltage at its base. Choose the transistor BC107. For more details on BC107 see A.3. Apply the sinusoidal message signal of frequency f m < 1 khz and amplitude E m < 10 V pp at the collector. Apply a carrier at the transistor base through a resistor 10kΩ. The carrier pulse amplitude is set as E c = 10 V pp and frequency f c = 10kHz. PAM using CMOS switching IC CD4016 CD 4016 is a quad bilateral CMOS switching IC. See A.4 for more deatails. The message signal is fed to any of the input terminals of the switch and the modulating pulse carrier is fed as the control signal for the switch. The PAM output will be available at the output terminal of the switch which is fed to the CRO across a load resistor of 10 kω. Keep the message signal frequency to be f m = 500 Hz and the switching pulse of 10 khz which is the carrier is to be fed from the TTL output from a function generator.

29 29 Figure 5.2: PAM modulation using switching IC Demodulation Demodulation is done using a π RC filter. Design the filter as per the equation for upper cut-off frequency of a low pass filter, f H = 1.5 khz = 1 2πR d C d (5.1) 1 2πR d C d (5.2) Select C d = 0.01µF. Then R d = 10kΩ. Choose R d = 10kΩ standard resistor value. Circuit Diagram Using transistor as a switch The PAM generation using transistor as a switch and demodulation circuit is shown in Figure. 5.3.

30 30 CHAPTER 5. PAM GENERATION AND DEMODULATION Figure 5.3: PAM generation and demodulation circuuit Using CMOS switching IC CD4016 The PAM generation using CD4016 is shown in Figure Demodulation can be done in the same way as shown in 5.3. Procedure Connect the PAM generating circuit as shown in the circuit diagram, Figure 5.3. Feed the modulating message signal and the carrier pulses from the function generator. Observe the output on a CRO and plot the graphs of the input and output waveforms. Make the demodulating circuit as shown in the circuit diagram, Figure 5.3. Repeat the PAM experiment using CD4016 IC. Make connections as shown in the circuit diagram Figure If IC is used for modulation make sure it is biased with V DD = 5V and is properly grounded. Observe the input and output waveforms from PAM generaton and demodulation circuits using CD4016 IC.

31 31 Observation Figure 5.4: PAM generation using CD4016 Plot the graphs of input and ou tput waveforms as observed on a CRO. Result Implemented the PAM generation and demodulation circuits using BJT as well as switching IC.

32 32 CHAPTER 5. PAM GENERATION AND DEMODULATION

33 Chapter 6 PWM Generation and Demodulation Aim To set-up and implement circuit to carry out pulse width modulation. To design demodulating circuit to detect the message from pulse width modulated wave. Theory In pulse width modulation method, the width of a constant amplitude constant frequency(constant period T) pulse is varied in accordance with the amplitude of analog modulating signal as shown. Before and after modulation, the amplitude and frequency of the carrier remain constant. Only the pulse width or duty cycle is varying. Waveforms showing pulse carriers whose width is modulated by message is shown in Figure 6.1. Modulation can be carried out using a 555 timer IC configured in monostable multivibrator mode. Normally in a mostable multivibrator the width of the pulse is determined by the time constant of the circuit and the period is determined by the trigger signal period. The width of the pulse is also influneced by the voltage at the control pin-5 of 555 timer IC. Applying the modulating message signal at pin-5 allows to vary the pulse width as per the modulating signal. The demodulation of PWM waveform can be implemented by using a lowpass filter which passes message signal frequenies but blocks the carrier signal. 33

34 34 CHAPTER 6. PWM GENERATION AND DEMODULATION Design Modulation One technique to implement PWM is to use 555 timer IC in monostable multivibrator mode. Without any input signal at control terminal pin-5, the output pulse width is determined by the equation t w = 1.1RC (6.1) This pulse width has to be less than the trigger signal period(t), for the output frequency to be same as the trigger signal frequency. For a PWM generator to have maximum swing of pulse width for a sinewave modulating signal at pin-5, keep t w = T 2. Select a sampling frequency = Carrier frequency =Trigger signal frequency =5 khz. ie., T = 0.2ms (6.2) Without modulating signal (V C = 0), the width of the pulse is t w = T 2. t w = 1.1RC = 0.1ms (6.3) Assume C = 0.01µF. Then R = 9kΩ 8.2kΩstd (You can use C = 0.02µF and R = 4.7kΩ as well for the same pulse width. ) The modulating signal given must have an amplitude 8V pp ( 2V CC 3 ). Demodulation Demodulation is done using a π RC filter. Design the filter as per the equation for upper cut-off frequency of a low pass filter, f H = 1 2πR d C d (6.4) Eliminate the high frequency carrier and obtain the low frequency modulating signal from PWM output. 1 khz = Select C d = 0.01µF. Then R d 15kΩ. 1 2πR d C d (6.5) Circuit Diagram The circuit diagram for implementing PWM modulator using 555 IC and demodulation using RC filter is shown.

35 35 Procedure Figure 6.1: PWM generation and demodulation circuuit Connect the PWM generating circuit as shown in the circuit diagram, Figure 6.1. Feed the carrier pulse (square wave of 5kHz, 12V P P ) from the function generator. Without applying the modulating signal, see the output waveform at pin- 3. It should have 50% duty cycle. Feed the modulating message signal(500hz, 8V pp ) at pin-5. Observe the output on a CRO and plot the graphs of the input and output waveforms. Make the demodulating circuit as shown in the circuit diagram, Figure 6.1. Observe the input and output waveforms from PWM demodulation circuit. Observation Plot the graphs of input and output waveforms as observed on a CRO.

36 36 CHAPTER 6. PWM GENERATION AND DEMODULATION Result Implemented the PWM generation and demodulation circuits and plotted the waveforms.

37 Chapter 7 PPM Generation and Demodulation Aim To set-up and implement circuit to carry out pulse position modulation. To design demodulating circuit to detect the message from pulse position modulated wave. Theory In pulse position modulation method, the position of a narrow pulse is varied within the period of the carrier in accordance with the amplitude of analog modulating signal as shown. Before and after modulation, the amplitude and frequency of the carrier remain constant. Only the pulse position is varying. Waveforms showing pulse carriers whose position is modulated by message is shown in Figure 7.1. Modulation can be carried out using a 555 timer IC configured in monostable multivibrator mode. The width of the pulse is set to be very narrow(10% duty cycle) by the time constant of the circuit. The monostable multivibrator is triggered by the output of a PWM signal (See the waveform). The result is PPM modulation. The demodulation of PPM waveform can be done by regenerating PWM waveform using 555 timer IC as a switch. A lowpass filter which passes message signal frequenies but blocks the carrier signal is used then to demodulate the message signal. 37

38 38 CHAPTER 7. PPM GENERATION AND DEMODULATION Design Modulation One technique to implement PPM is to use 555 timer IC in monostable multivibrator mode. Let the carrier frequency be 5 khz. Then T = 0.2ms. The pulse width is set to be 10 % of T. t w = 0.02ms (7.1) t w = 1.1RC (7.2) Assume C = 0.01µF. Then R 1.8kΩ The modulating signal given must have an amplitude 8V pp ( 2V CC 3 ). Demodulation The demodulation of PPM waveform can be done by regenerating PWM waveform using 555 timer IC as a switch. The reset terminal pin-4 of the IC and the trigger terminl-2 are used for this purpose. Reset signal-4 is the complement of PPM signal and the the trigger signal is the carrier(clock) fequency of the PWM. Then the output at pin-3 is the regenerated PWM from the PPM signal. Use a low pass filter to obtain the message signal. Demodulation is done using a π RC filter. Design the filter as per the equation for upper cut-off frequency of a low pass filter, f H = 1 2πR d C d (7.3) Eliminate the high frequency carrier and obtain the low frequency modulating signal from PWM output. 1 khz = Select C d = 0.01µF. Then R d 15kΩ. Circuit Diagram 1 2πR d C d (7.4) The circuit diagram for implementing PPM modulator using 555 IC and demodulation using RC filter is shown. Procedure Connect the PWM generating circuit followed by PPM generating circuit as shown in the diagram, Figure

39 Figure 7.1: PPM generation and demodulation circuuit 39

40 40 CHAPTER 7. PPM GENERATION AND DEMODULATION Feed the carrier pulse (square wave of 5kHz, 12V P P ) from the function generator. Feed the modulating message signal(500hz, 8V pp ) at pin-5 of PWM generator. Observe the outputof PWM and PPM on a CRO and plot the graphs of the input and output waveforms. Make the demodulating circuit as shown in the circuit diagram, Figure Observe the input and output waveforms from PWM demodulation circuit. Observation Plot the graphs of input and output waveforms as observed on a CRO. Result Implemented the PPM generation and demodulation circuits and plotted the waveforms.

41 Chapter 8 DSB-SC using multiplier IC AD633 Aim To set up a balanced modulator circuit for double side band suppressed carrier amplitude modulator.to implement a demodulator to obtain the message signal. Theory DSB-SC is a kind of amplitude modulation in which the carrier frequency component is absent. It is generated by multiplying the carrier and modulating signals. If e c is the carrier and e m is the message signal, where e c = E c sin 2πf c t (8.1) e m = E m sin 2πf m t (8.2) Multiplication is done using AD633 (See A.5) multiplier IC. Applying e m to X and e c to Y with Z grounded, W = e me c 10 = Emsin(2πf mt).ecsin(2πf c t) 10 (8.3) W = E me c [cos2π(f c f m )t cos2π(f c + f m )t] (8.4) 10 2 W = E me c [cos2π(f c f m )t] E me c [cos2π(f c + f m )t] (8.5) This wave contains both the sidebands at f c f m and f c + f m, but not the wave at carrier frequency 1. Hence the name double sideband suppressed carrier modulation(dsb-sc). 1 sin A. sin B = cos (A B) cos (A+B) 2 41

42 42 CHAPTER 8. DSB-SC USING MULTIPLIER IC AD633 The following figure 8.1 shows 2 the DSB-SC signal in blue and the original message is shown in red. (It is an indicative graph, not to scale as per the experimental set-up.) Figure 8.1: DSB-SC signal in blue, original message shown in red. Multiplying the DSB-SC with the carrier once again will result in the following output. W = 1 10 [E me c [cos(2π(f c f m )t)] 20 E me c [cos(2π(f c + f m )t)] ].E c sin(2πf c t) 20 (8.6) W = E m.e c sin(2π(2f c f m )t) E 2 m.e c sin(2π(2f c + f m )t) E 2 m.e c sin(2πf m t) 200 (8.7) Thus the signal consists of various frequencies of which, the smallest is the message frequency. It can be extracted by filtering using a low pass filter. Since the amplitude of the message frequency is very small, It may be amplified using a simple non-inverting amplifier using an opamp. Design To the X input of the IC, feed the message sinusoid of amplitude E m = 2.5 V (ie., peak to peak amplitude of 5 V) and frequency f m = 1 khz. To the Y input of the IC, feed the carrier sinusoid of amplitude E c = 2.5 V and frequency f c = 100 khz. Ground the Z input of the IC. 2 Image Courtesy: Serych at cs.wikipedia [Public domain], from Wikimedia Commons

43 43 Figure 8.2: Message and carrier signals Provide the supply voltage of +15 V to pin 8 of the IC and -15 V to pin 5 of the IC. The output signal will have a waveform as given by, W = e m.e c 10 = W = X.Y 10 + Z (8.8) (2.5).(2.5) [cos2π99kt cos2π101kt] 10 2 (8.9) This is the DSB-SC waveform. W = 6.25 [cos2π99kt cos2π101kt] (8.10) 20 Demodulation is by multiplying the DSB-SC signal once again with the carrier. This can be implemented by connecting another AD633 IC in cascade with the first one. The multiplication will result in the following output, as per the theory already explained.

44 44 CHAPTER 8. DSB-SC USING MULTIPLIER IC AD633 Figure 8.3: AM(DSB-FC) and Demodulation stage-1 signals W = sin(2π1kt) (8.11) sin(2π199kt) sin(2π201kt) This waveform is shown in Figure 8.3, which is the stage -1 in demodulation. The next step is to obtain the message signal. This is done by lowpass filtering the above signal at a cut-off frequency of 1.5 khz. To design an RC lowpass filter of cut-off frequency 1.5 khz, f c = Choose C 1 = 0.01 µf R 1 = 10 kω 1 2πR 1 C 1 = 1.5kHz (8.12) A non-inverting amplifier may be used to amplify this signal. Using a feedback resistor of R f = 100 Ω and an input resistance of R i = 10 kω will result in a gain of A v = 1 + R f R i = 11.

45 45 Circuit Diagram The circuit diagram for implementing DSBSC using multiplier IC is shown in figure 8.4. Procedure Make connections as shown in the circuit diagram, figure 8.4. Feed the message and carrier signals. Connect the pin number 7 of the IC to a CRO and observe the resultant waveform which is DSB-SC. Connect the pin number 7 of the second IC to a CRO and observe the resultant waveform which is the product of DSB-SC and the carrier.(named demodulation stage-1 signal) Observe the output from the filter, amplified by the opamp amplifier, which extracts the envelope -The 1kHz message signal- of the previous signal. Plot the signals observed on a graph sheet. Observation The input and output signals as observed on a CRO are shown in Figure 8.2 and 8.3. Result Implemented DSB-SC using multiplier IC AD 633 and observed the signal waveforms.

46 46 CHAPTER 8. DSB-SC USING MULTIPLIER IC AD633 Figure 8.4: Circuit for DSB-SC generation and detection using AD633 multiplier IC

47 Chapter 9 AM generation and Demodulation using AD 633 Aim To design and implement AM generation and demodulation using multiplier IC AD633. Theory DSB-SC using AD633 has already been discussed in chapter 8. DSB-SC is same as AM devoid of the carrier. Inorder to obtain the complete AM waveform which is double side band with carrier, add the carrier signal to the DSB-SC signal. This can be done using the 633 multiplier IC. For more details on IC, refer A.5. W = X.Y 10 + Z (9.1) W = Emsin(2πf mt).ecsin(2πf c t) + E c sin(2πf c t) (9.2) 10 W = E me c [cos(2π(f c f m )t)] E me c [cos(2π(f c + f m )t)] + E c sin(2πf c t) (9.3) The resultant AM can be demodulated in two ways, 1. Using Diode envelope detector. 2. Using another AD633 in cascade with AM generating circuit for multiplying the AM with the carrier. 47

48 48CHAPTER 9. AM GENERATION AND DEMODULATION USING AD 633 Multiplying the AM with the carrier once again will result in the following output. W = 1 10 [E me c [cos(2π(f c f m )t)] E me c [cos(2π(f c E c sin(2πf c t)].e c sin(2πf c t) + f m )t)] (9.4) W = E c E 2 m.e c sin(2πf m t) 200 E c 2 20 cos(2π(2f m)t) + E m.e c sin(2π(2f c f m )t) E 2 m.e c sin(2π(2f c + f m )t) 400 (9.5) Thus the signal consists of various frequencies of which, the smallest is the message frequency. It can be extracted by filtering using a low pass filter. Since the amplitude of the message frequency is very small, It may be amplified using a simple non-inverting amplifier using an opamp. Design Provide the supply voltage of +15 V to pin 8 of the IC and -15 V to pin 5 of the IC. To the Y and Z inputs of the IC, feed the carrier sinusoid of amplitude E c = 2.5 V and frequency f c = 100 khz. To the X input of the IC, feed the message sinusoid of amplitude E m = 2.5 V and frequency f m = 1 khz. The output AM signal will have a waveform as given by, W = X.Y 10 + Z (9.6) W = e m.e c 10 + e c (9.7) W = 6.25 [cos2π99kt cos2π101kt] + 2.5sin(2π100kt) (9.8) 20 Thus it contains two sidebands and the carrier, ie Double sideband - Full Carrier AM. Demodulation: Detection may be done using a diode envelope detector as already discussed in chapter 4. An alternate method of demodulation is by multiplying the AM signal once again with the carrier. This can be implemented by connecting another AD633 IC in cascade with the first one.

49 49 The multiplication will result in the following output, as per the theory already explained. W = sin(2π1kt) (9.9) cos(2π2kt) + sin(2π199kt) sin(2π201kt) This waveform is shown in Figure 9.3, which is the stage -1 in demodulation. The next step is to obtain the message signal. This is done by lowpass filtering the above signal at a cut-off frequency of 1.5 khz. To design an RC lowpass filter of cut-off frequency 1.5 khz, 1 f c = = 1.5kHz (9.10) 2πR 1 C 1 Choose C 1 = 0.01 µf R 1 = 10 kω A non-inverting amplifier may be used to amplify this signal. Using a feedback resistor of R f = 100 kω and an input resistance of R i = 10 kω will result in a gain of A v = 1 + R f R i = 11. Circuit Diagram The circuit diagram for generating AM(DSB-FC) and demodulating it using AD633 multiplier IC as shown in Figure Procedure Make connections as shown in the circuit diagram, figure 9.1. Feed the message and carrier signals. Connect the pin number 7 of the first IC to a CRO and observe the resultant waveform which is AM(DSB-FC). Connect the pin number 7 of the second IC to a CRO and observe the resultant waveform which is the product of DSB-FC and the carrier.(named demodulation stage-1 signal) Observe the output from the filter, amplified by the opamp amplifier, which extracts the envelope of the signal-the 1kHz message signal. Plot the signals observed on a graph sheet. Observation The input and output signals as observed on a CRO are shown in Figure 9.2and 9.3.

50 50CHAPTER 9. AM GENERATION AND DEMODULATION USING AD 633 Result Implented the AM generation and demodulation circuit using multiplier IC and opamps. The resultant waveforms were plotted.

51 Figure 9.1: Circuit for AM generation and detection using AD633 multiplier IC 51

52 52CHAPTER 9. AM GENERATION AND DEMODULATION USING AD 633 Figure 9.2: Message and carrier signals

53 Figure 9.3: AM(DSB-FC) and Demodulation stage-1 signals 53

54 54CHAPTER 9. AM GENERATION AND DEMODULATION USING AD 633

55 Chapter 10 FM using 555 Aim To design and set up a frequency modulating circuit using 555. Theory Frequency modulation is an analog modulation technique in which the frequency of the carrier is varied in accordance with the message signal amplitude. Modulation index for FM is m = δf f requency deviation = f m modulating signal f requency (10.1) 555 is an IC which can be used to to set up an astable multivibrator of 50% duty cyle whose frequency is determined by externally connected RC load. (See Appendix A.6) The standard design equation for an astable mutivibrator using 555 timer IC is defined by the following equation for its time period. Thus its frequency of oscillation is T = 1.38 RC (10.2) f 0 = 0.72 RC (10.3) This frequency of oscillation remains constant as long as the pin-5 is supplied with a constant voltage. If the voltage at pin-5 is varying the frequency of oscillation of the astable multivibrator also changes along with it. Thus astable multivibrator using 555 can be used as a carrier pulse generator. The frequency of the carrier can be varied by feeding the pin-5 with message signal. 55

56 56 CHAPTER 10. FM USING 555 Design Figure 10.1: Circuit to implement frequency modulation using 555 Let the carrier frequency be given by f c = 10kHz f c = 0.72 RC (10.4) Let C = 0.01µF R = 0.72 (10)(10 3 )(0.01X10 = 6.8kΩ (10.5) 6) The amplitude of the modulationg signal should be limited by 2 3 V cc. This is needed to avoid over modulation. The message signal should have a frequency less than 1 khz. The dc supply voltage of the IC, V cc = 12V (10.6) V mpp = 2 X12V = 8V (10.7) 3 Circuit Diagram The circuit to implement frequency modulation using 555 is shown in Figure 10.1.

57 57 Figure 10.2: Message, Carrier and frequency modulated waveforms Procedure Make connections as per the circuit diagram. Feed the message signal of peak-to-peak amplitude of 5V and frequency 1kHz. Observe the FM output at pin number-3. Plot the observations on a graph sheet. Observations Observe the input and output waveforms on a CRO and plot the same on a graph sheet. See Figure Result Implemented frequency modulation of pulse carrier by sinusoidal messaage using 555 timer IC.

58 58 CHAPTER 10. FM USING 555

59 Chapter 11 Study of PLL IC CD4046 AIM To study the characteristics of PLL IC CD4046 and find its lock range and capture range. THEORY PLL is basically a closed loop electronic circuit designed to lock or synchronize the output frequency and phase to the frequency and phase of the input signal for a given range. Internal block diagram of the IC CD4046 is given in the figure It consists of a linear voltage controlled oscilator (VCO) and two phase comparators. The two phase comparators have a common signal input terminal and a common comparator input terminals. The signal input terminal can be directly coupled for large input signal( upto V CC ) or capacitively coupled for small input signals (less than V CC 2 ). PC1 uses an XOR gate internally. Within the capture range, the output pulse width vary with the frequency difference between the signal input and the comparator input frequencies. Output amplitude is V CC. PC1 gives a digital error signal tye pulse width of which depends on the phase difference between inputs. Between the signal input frequency and the comparator input frequency, it may synchronise on to the signal frequencies that are close to VCo central frequency, f 0 or its harmonics. PC2 is an edge triggered flip-flop circuit and its output is also proportional to the phase difference between two input frequencies. The linear VCO produces an output frequency (pulses) whose amplitude depends on V CC only, and the frequency depends on the the control voltage V C 59

60 60 CHAPTER 11. STUDY OF PLL IC CD4046 Figure 11.1: Internal block Diagram of IC CD4046 to be given to the VCO input terminal (VCOin) and resistors R 1 and R 2 and the capacitor C to be connected externally. This signal is obtained at VCOout terminal of the IC. The VCO sensitivity 1 is determined by R 1 and C and offset frequency 2 is determined by R 1 and C. A voltage follower is internally connected to the to the VCO input, the output of which is givena s demodulated output terminal of the IC. A pull down resistor (greater than 10 kω) must be connected from the demodulated output terminal to the ground. The output is taken across this resistor. For proper operation of the IC, the INHIBIT(/STROBE/ENABLE) terminal must be grounded. The free running frequency f 0 is given by f V CO = 0.16 ( V CC 2 ) + 1 R 1.C R 2.C (11.1) Capture Range and Lock Range There are two range of frequencies that can be defined for a PLL for which the PLL output frequency can maintain synchronization with a range of input fequencies. Within the capture range f c of PLL the output frequency will always maintain synchronization with the input signal frequency unconditionally whether the input frequency is increasing or decreasing. Within the lock range (f L ) of PLL the output frequency 1 oscillating voltage proportional to control voltage 2 Frequency output at V C =0

61 61 maintains synchronization with the input signal frequency with some condition. Within the lock range, towards the lower range the output mantains synchronization only when the frequency is increasing and towards the upper range of input frequencies output maintains synchronization only when the frequency is decreasing. DESIGN CD 4046 can be used either as a VCo or as a phase comparator. To get the PLL operation the input signal must be given to the signal input terminal, the phase comparator input must be given from the VCOout terminal and the VCO input from the phase comparator 1 or 2 throgh a powpass filter. Select centre frequency =4 khz and offset frequency =1 khz. Select, f 0 = 0.16( V CC 2 ) = 4kHz (11.2) R 1 C C = 0.01µF, R 1 = 10kΩ (11.3) Select, f 0 = 1 R 2 C = 1kHz (11.4) C = 0.01µF, R 2 = 100kΩ (11.5) Select a lowpass filter with R f = 10kΩ and C f = 1µF. CIRCUIT DIAGRAM The circuit diagram as per the above design is shown in Figure PROCEDURE 1. GND the input terminal (pin-14) 2. Connect a CRO at the output (pin-4). The VCO output frequency will be around 5 khz. 3. Then remove the GND and give the input signal from the function generator throgh a capacitor and vary the input frequency at constsnt amplitude 2.5V pp. 4. Find the frequencies f 1, f 2, f 3 and f 4. Find f 1 and f 2 while increaing the frequency and f 3 and f 4 while the frequency is deareasing. 5. Capture range f c = f 3 f 1 and Lock range f L = f 2 f 4

62 62 CHAPTER 11. STUDY OF PLL IC CD4046 Figure 11.2: Circuit Diagram to determine lock range and capture range RESULTS Studied the characteristics of PLL IC. Determined its lock range and capture range. f c 1.1khz and f L 7khz

63 Chapter 12 FM - Modulation and Demodulation using PLL Aim To implement FM modulation and demodulation circuits using PLL IC CD4046 Theory CD 4046 is an analog Phase Locked Loop IC, whose characteristics and features are discussed in Appendix A.7. This IC can be used for FM modulation and demodulation. FM Modulation The VCO part of the PLL may be used for the frequency modulation of the carrier. In a VCO, the output frequency is proportional to the control volatge input. In the absance of control voltage, the free running frequency is determined by the supply voltage V CC, the externally connected resistances R 1 and R 2 and the capacitance C. The free running frequency f 0 is given by f 0 = 0.16 X V CC 2 R 1.C + 1 R 2.C (12.1) The VCO in free running mode is the carrier generator. The carrier frequency is f 0. The control input of the VCO is clamped at a voltage Vcc 2. The modulating signal voltage which is less than Vcc 2 is applied at this pin through a capacitor. This results in variation in the frequency of oscillation of the VCO, which is the frequency modulated signal. 63

64 64CHAPTER 12. FM - MODULATION AND DEMODULATION USING PLL FM Demodulation Another PLL IC has to be used for FM demodulation. The VCO part of this IC is configured for the same free running frequency as that of the modulator IC. One of the phase detector input is fed with the modulated FM signal and the other input of the phase detector is fed with the VCO output after filtering out high frequency componens. The phase variation between the two will be corresponding to the message which was used for modulation. The PD output is passed through an emitter follower internally to the demodulated output pin. The output from this pin may contain high frequency ripples which may be eliminated by proper filtering to obtain the actual message. Design Supply V CC = 5V at pin-16 and ground pin-8 of both PLL ICs. Modulation Use a voltage divider network of two resistors with R = 10 kω for clamping the control voltage input (pin-9) at Vcc 2 = 2.5V. Give a message signal of frequency 1kHz and amplitude 1 V pp at control voltage input (pin-9) throgh a capacitor of C 1 = 1µF. Select R 1 = 10 kω (pin-11), R 2 = 100 kω (pin-12) and C = 0.002µF (between pin-6 and pin-7) so that free running frequency as per equation 12.1 is given by, f 0 = (0.16).(2.5V ) (10kΩ).(0.002µF ) + 1 = 20kHz + 5kHz = 25kHz (100kΩ).(0.002µF ) (12.2) The FM output is obtaned from V CO out (pin-4) of first PLL IC. Demodulation Use the same R 1, R 2 and C for the second PLL IC so that the free running frequency remains the same as that of the modulating IC. Feed the signal input pin of phase detector (pin-14) of the second IC with the FM signal. The other input of phase detector (pin-3) is fed with VCO output (pin-4). The output from phase detector(pin-2) is fed back to VCO input (pin-9) through a low-pass filter with R 3 = 10 kω and C 1 = µF. The demodulated output is obtained from the pin-10 by pulling down using a resistor R p = 10 kω. It is then low pass filtered at fc = 1.5kHz to eliminate higher order ripples. f c = Choose C f = 0.01 µf. R f = 10 kω. 1 2πR f C f = 1.5kHz (12.3)

65 65 Circuit Diagram The circuit diagram for FM modulation and demodulation are shown in figure Procedure Make connections as per the circuit digram. Provide dc supply and ground to the ICs. Observe the FM modulation and demodulation waveforms. Plot it on a graph sheet. Observation Plot the message, carrier, modulated and demodulated waves on a graph sheet. See Figure Result Implemented FM modulation and demodulation using PLL IC CD 4046.

66 66CHAPTER 12. FM - MODULATION AND DEMODULATION USING PLL C uf Vmsg 1 Vpp, 1kHz 5V Vcc R 10 kω R 10 kω 4046 PLL-1 14 PCain 3 PCbin 9 VCOin 5 Inh PC1out PC2out LD VCOout R1 R2 C1a C1b SFout Zener FM Output R1 10 kω R uF C 100 kω 4046 PLL-2 14 PCain 3 PCbin 9 VCOin 5 Inh PC1out PC2out LD VCOout R1 R2 C1a C1b SFout Zener R3 10 kω C1 0.01uF R1 10 kω C 0.002uF Rp 10 kω R2 100 kω Rf 10 kω Figure 12.1: Circuit for FM generation and detection using CD4046 PLL IC Cf 0.01uF Rf Demodulated Output 10 kω Cf 0.01uF

67 Figure 12.2: FM generation and detection waveforms 67

68 68CHAPTER 12. FM - MODULATION AND DEMODULATION USING PLL

69 Chapter 13 Mixer (Frequency Converter) Circuit using BJT Aim To design and set up a frequency converter circuit to produce an output frequency (f 0 ) which is the difference frequency between the two input frequency, (f 1 f 2 ). Theory A mixer or frequency mixer is a nonlinear electrical circuit that creates new frequencies from two signals applied to it. In its most common application, two signals at frequencies f 1 and f 2 are applied to a mixer, and it produces new signals at the sum f 1 + f 2 and difference f 1 f 2 of the original frequencies. Other frequency components (like f 1 ± 2f 2 may also be produced in a practical frequency mixer. 1 The most important application of mixers are in superhetrodyne receivers where the very high carrier frequency is down converted to an intermediate frequency. This is done by mixing the carrier frequency with a locally generated oscillator frequency to get an output frequency which is the difference between local oscillator frequency and incoming signal frequency, ie the intermediate frequency. In widely used AM receivers the local oscillator frequency is so chosen with respect to carrier frequency such that their difference is a constsnt intermediate frequency of 455kHz

70 70 CHAPTER 13. MIXER CIRCUIT USING BJT f IF = f oscillator f carrier = 455kHz The mixer output which contains all image frequencies of f 1 ± nf 2 is filtered to obtain the required difference frequency f 1 f 2. Design Let the input at the base be 10kHz(f 1 ) signal and at the emitter be 9 khz(f 2 ) signal such that the output contains their sum and difference frequencies. The output can be low pass filtered to obtain the difference frequency f 1 f 2 = 1 KHz. Choose Transistor BC107. See A.3 for its datasheet details. Take V CC = 12V and I C = 2mA under dc biasing conditions. For Class A mode of operation, let Design of Emitter and Collector Resistors V CE = 50% ofv CC = 6V (13.1) V RC = 40% ofv CC = 4.8V (13.2) V RE = 10% ofv CC = 1.2V (13.3) R C = V RC = 4.8V = 2.4kΩ. 2.2kΩ( standard resistor value) (13.4) I C 2mA R E = V RE = 1.2V = 600Ω. 560Ω( standard resistor value) (13.5) I E 2mA (Since I C I E = 2mA) Design of Potential divider resistors R 1 and R 2 At dc bias point, I B = I C = 2mA 20µA (13.6) h femin 110 Let the current through R 1 be 10I B and that through R 2 be 9I B such that I B flows through the base of BC107. Voltage across resistor R 2 is, I R1 = 10I B = 200µA (13.7) I R2 = 9I B = 180µA (13.8) V R2 = V RE + V BEactive = 1.2V + 0.6V = 1.8V (13.9) R 2 = V R2 = 1.8V = 100kΩ (13.10) I 2 180µA

71 71 Voltage across resistor R 1 is, V R1 = V CC + V R2 = 12V 1.8V = 10.2V (13.11) R 1 = V R1 = 10.2V = 51kΩ 47kΩ( standard resistor value) (13.12) I 1 200µA Design of coupling capaciors C 1 = 1µF and C E = 0.1µF Design of Filter Circuit Inorder to lowpass filter the output signal choose the upper cut-off frequency be f o =1.5kHz so that the required output 1 khz appears in the pass band. The cut-off frequency of lowpass filter is, f o = where R f and C f are the passive filter components. Choose R f = 10kΩ C f = Choose π filter configuration for better performance. Circuit Diagram See Figure 13.1 for circuit diagram. Procedure 1. Make connections as per the circuit diagram. 1 2πR f C f = 1.5 khz (13.13) 1 2πR f f o 0.01µF. (13.14) 2. Feed f 1 and f 2 with amplitudes as shown in the circuit diagram and frequencies 10 khz and 9 khz respectively. 3. Observe the filtered output frequency on a CRO. 4. Repeat with frequencies changed to 20 khz and 19kHz (50 khz and 49 khz)and observe it in CRO. Verify that the circuit gives the difference frequency of 1 khz at the output. 5. Plot the input and output signals on a graph sheet. Observation From the graph find the frequency of the output signal.

72 72 CHAPTER 13. MIXER CIRCUIT USING BJT Result Figure 13.1: Circuit Diagram for Mixer circuit using BJT The mixer circuit using BJT was set up and output was verified from signals observed on a CRO.

73 Appendix A Quick Reference: Component Details A.1 Intermediate Frequency Transformer Figure A.1: Schematic diagram of intermediate frequency transformer Intermediate Frequency Transformers come as specially designed tuned circuits in groundable metal packages called IF cans. The primary winding has an inducance of L eq = 450µH and it comes with a shunt capacitor of capacitance C = 270 pf. Its resonant frequency is thus f = 1 2π L eqc 455kHz. This frequecy is adjustable by a factor of ±10%. IFT has a tapped primary winding as shown in the schematic diagram, Figure A.1. The ferrite core between primary and secondary windings is tunable with a non-metallic screw driver or tuning tool. It changes the mutual inductance and thus control the Q-factor of the collector circuit of connected transistor[3]. Its internal details are shown in Figure A.2 and physical consruction is shown in Figure A.3 [4]. 1 pdf 1 Images are taken from: 73

74 74 APPENDIX A. QUICK REFERENCE: COMPONENT DETAILS A.2 BJT BF194/195 Figure A.2: Internal details of IF CAN BF194/195 is a high frequency transistor with the following characteristics. Type Designator: BF194/BF195 Material of transistor: Si Polarity: NPN Maximum collector power dissipation (P c), W: 0.25 Maximum collector-base voltage V cb, V: 30 Maximum collector-emitter voltage V ce, V: 20 Maximum emitter-base voltage V eb, V: 5 Maximum collector current I cmax, ma: 30 Forward current transfer ratio (hfe), min: 67 A.3 BJT BC107 Type Designator: BC107 Material of transistor: Si Polarity: NPN Maximum collector power dissipation (P c ), W: 0.3 Maximum collector-base voltage V cb, V: 50 Maximum collector-emitter voltage V ce, V: 45 Maximum emitter-base voltage V eb, V: 6 Maximum collector current I cmax, A: 0.1 Forward current transfer ratio (h F E ), min: 110 Package of BC107 transistor: TO18

75 A.4. CD CMOS SWITCHING IC 75 Figure A.3: Physical construction of IF CAN A.4 CD CMOS switching IC The 4016 contains 4 analogue bilateral switches, each with an active-high enable input (A) and two input/outputs (X and Y). When the enable input is asseted (high), the X and Y terminals are connected by a low impedance; this is the on condition. When the enable is low, there is a high impedance path between X and Y, and the switch is off. The pinout diagram of 4016 switching IC is shown in Figure. A.4 2. A.5 AD Multiplier IC Multiplier ICs: Analog multipliers are complex arrangements of Opamps and other circuit elements in the form of IC. It can be used for different applications like multiplication, division, squarer, modulator, demodulator, filter etc. There are two inputs X and Y to which the signals to be multiplied are given. There are two input terminals X and Y to which the signals to be multiplied are given. The output W is the product of instantaneous values of input signals reduced by a scale factor k. k is usually less than 1. For practical ICs k = W = kxy (A.1) AD633 is functionally a complete four quadrant analog multilier IC. The functional block diagram is shown in Fig. A.5. This IC uses Gilbert s transconducatnce multiplier module in four quadrants. On chip circuit provides a scale 2 Image courtesy:inductiveload (Own work) [Public domain]via Wikimedia Commons

76 76 APPENDIX A. QUICK REFERENCE: COMPONENT DETAILS Figure A.4: Pinout Diagram of 4016 switching IC factor of k = If X, Y and Z inputs are given we get W = XY 10 + Z (A.2) Here Z is the input to the summing amplifier. input is grounded, then output W = XY 10 If the summing amplifier (A.3) Specifications as in AD633 data sheet is, Dual power supply: V cc = ± 8V to ± 18V Input impedance > 5MΩ Output impedance < 75Ω Maximum operating frequency (Bandwidth) = 1M Ω A Timer IC The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse generation, and oscillator applications. The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element. All these circuit variats are achieved by connecting proper values of resistors and capacitors externally. The pinout 3. of 555 timer IC are shown below. 3 Image courtesy:inductiveload (Own work) [Public domain]via Wikimedia Commons

77 A.7. CD PLL IC 77 Figure A.5: Functional Block Diagram for AD633 multiplier IC The functions of various pins of 555 are shown in Table A.1. 4 Please refer to 555 Timer IC for more detailed working of the IC pins when it is configured as multivibrators or oscillators. A.7 CD PLL IC A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal from an oscillator which is synchronized in phase and frequency with its input signal. It is an electronic circuit consisting of a voltage controlled variable frequency oscillator(vco), a phase detector and a lowpass filter. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal. Proportional to the phase difference a voltage waveform is generated. It is lowpass filtered to obtain a dc volatge which is proportional to the phase difference. This voltage is fed back to the VCO to control and adjust the oscillator to keep the phases matched. For more details refer [5]. Specifically PLL synchronizes its VCO phase and frequency with the input for a given range of frequencies. The block diagramatic representation of a PLL is shown in Figure. A.7. The range of input frequencies(f i = f min to f i = f max ) for which the the PLL remains in this locked condition is called lock range of the PLL. If PLL is initially locked and the input fequency f i becomes less than f min or if f i exceeds f max, PLL becomes unlocked. When PLL is unlocked, VCO oscillates at free running frequency or centre 4

78 78 APPENDIX A. QUICK REFERENCE: COMPONENT DETAILS Figure A.6: Pin-out diagram of 555 IC Figure A.7: Block diagram of a PLL frequency, f 0. The lock can be re-established if f i becomes sufficiently close to f 0. The range of frequencies around f 0 (ie, f 0 f cap to f 0 + f cap ) which when applied as input captures a PLL into lock is called capture range of the PLL. CD4046 is a PLL IC. It has a linear voltage controlled oscillator(vco) and two phase comparators(p C 1 and P C 2 )-Any of which can be used for PLL operation. The periodic signal generated by the VCO is the output signal which is synchronized with the input signal. The amplitude of VCO output depends on V cc and its free running frequency is determined by V cc as well as the value of externally connected resistors and capacitors R 1, R 2 and C. The pinout diagram is shown in the Figure. A.8.