N-channel TrenchMOS transistor

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1 IRF53N FEATURES SYMBOL QUICK REFERENCE DATA Trench technology Low on-state resistance Fast switching Low thermal resistance g d s V DSS = V I D = 7 A R DS(ON) mω GENERAL DESCRIPTION PINNING SOT78 (TOAB) N-channel enhancement mode PIN DESCRIPTION field-effect power transistor in a plastic envelope using trench gate technology. drain Applications:- d.c. to d.c. converters 3 source switched mode power supplies tab drain The IRF53N is supplied in the SOT78 (TOAB) conventional leaded package. tab drain 3 gate source drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 3) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 5 C to 75 C - V V DGR Drain-gate voltage T j = 5 C to 75 C; R GS = kω - V V GS Gate-source voltage - ± V I D Continuous drain current T mb = 5 C; V GS = V - 7 A T mb = C; V GS = V - A I DM Pulsed drain current T mb = 5 C - 68 A P D Total power dissipation T mb = 5 C - 79 W T j, T stg Operating junction and C storage temperature AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 3) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT E AS Non-repetitive avalanche Unclamped inductive load, I AS = 7.8 A; - 5 mj energy t p = 3 µs; T j prior to avalanche = 5 C; V DD 5 V; R GS = 5 Ω; V GS = V; refer to fig: I AS Peak non-repetitive - 7 A avalanche current August 999 Rev.

2 IRF53N THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air K/W to ambient ELECTRICAL CHARACTERISTICS T j = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D =.5 ma; - - V voltage T j = -55 C V V GS(TO) Gate threshold voltage V DS = V GS ; I D = ma 3 V T j = 75 C - - V T j = -55 C - 6 V R DS(ON) Drain-source on-state V GS = V; I D = 9 A - 8 mω resistance T j = 75 C mω g fs Forward transconductance V DS = 5 V; I D = 9 A 6. - S I GSS Gate source leakage current V GS = ± V; V DS = V - na I DSS Zero gate voltage drain V DS = V; V GS = V -.5 µa current V DS = 8 V; V GS = V; T j = 75 C µa Q g(tot) Total gate charge I D = 9 A; V DD = 8 V; V GS = V - - nc Q gs Gate-source charge nc Q gd Gate-drain (Miller) charge nc t d on Turn-on delay time V DD = 5 V; R D =.7 Ω; ns t r Turn-on rise time V GS = V; R G = 5.6 Ω ns t d off Turn-off delay time Resistive load ns t f Turn-off fall time - - ns L d Internal drain inductance Measured tab to centre of die nh L d Internal drain inductance Measured from drain lead to centre of die nh (SOT78 package only) L s Internal source inductance Measured from source lead to source nh bond pad C iss Input capacitance V GS = V; V DS = 5 V; f = MHz pf C oss Output capacitance pf C rss Feedback capacitance pf REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I S Continuous source current A (body diode) I SM Pulsed source current (body A diode) V SD Diode forward voltage I F = 7 A; V GS = V -.9. V t rr Reverse recovery time I F = 7 A; -di F /dt = A/µs; ns Q rr Reverse recovery charge V GS = V; V R = 5 V nc August 999 Rev.

3 IRF53N Normalised Power Derating, PD (%) Mounting Base temperature, Tmb (C) Fig.. Normalised power dissipation. PD% = P D /P D 5 C = f(t mb ). Transient thermal impedance, Zth j-mb (K/W) D = single pulse T. E-6 E-5 E- E-3 E- E- E+ Pulse width, tp (s) P D Fig.. Transient thermal impedance. Z th j-mb = f(t); parameter D = t p /T tp D = tp/t Normalised Current Derating, ID (%) Mounting Base temperature, Tmb (C) Fig.. Normalised continuous drain current. ID% = I D /I D 5 C = f(t mb ); conditions: V GS V Drain Current, ID (A) Tj = 5 C VGS = V.6 V 5. V.8 V Drain-Source Voltage, VDS (V) Fig.5. Typical output characteristics, T j = 5 C. I D = f(v DS ) 8 V 5. V 6 V 5 V. V. Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID D.C. tp = us us ms ms ms Drain-Source Voltage, VDS (V) Fig.3. Safe operating area. T mb = 5 C I D & I DM = f(v DS ); I DM single pulse; parameter t p Drain-Source On Resistance, RDS(on) (Ohms)..8V 5. V.8.6V 5 V.6 5. V Tj = 5 C VGS = V Drain Current, ID (A) Fig.6. Typical on-state resistance, T j = 5 C. R DS(ON) = f(i D ) 6V 8 V August Rev.

4 IRF53N Drain current, ID (A) VDS > ID X RDS(ON) C 6 Tj = 5 C Gate-source voltage, VGS (V) Fig.7. Typical transfer characteristics. I D = f(v GS ) Threshold Voltage, VGS(TO) (V) typical minimum maximum Junction Temperature, Tj (C) Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 5 C 75 C Drain current, ID (A) Fig.8. Typical transconductance, T j = 5 C. g fs = f(i D ).E-.E-.E-3.E-.E-5.E-6 Drain current, ID (A) minimum typical maximum Gate-source voltage, VGS (V) Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = 5 C; V DS = V GS Normalised On-state Resistance Junction temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. R DS(ON) /R DS(ON)5 C = f(t j ) Capacitances, Ciss, Coss, Crss (pf) Ciss Coss Crss. Drain-Source Voltage, VDS (V) Fig.. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = MHz August 999 Rev.

5 IRF53N Source-Drain Diode Current, IF (A) VGS = V C 8 Tj = 5 C Source-Drain Voltage, VSDS (V) Fig.3. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j Maximum Avalanche Current, I AS (A) Tj prior to avalanche = 5 C 5 C.... Avalanche time, t AV (ms) Fig.. Maximum permissible non-repetitive avalanche current (I AS ) versus avalanche time (t AV ); unclamped inductive load August Rev.

6 IRF53N MECHANICAL DATA Plastic single-ended package; heatsink mounted; mounting hole; 3-lead TO- SOT78 E P A A q D D L () L Q L b 3 b c e e 5 mm scale DIMENSIONS (mm are the original dimensions) () UNIT A A b b c D D E e L L L P max mm q 3..7 Q.6. Note. Terminals in this zone are not tinned. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT78 TO Fig.5. SOT78 (TOAB); pin connected to mounting base (Net mass:g) Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.. Refer to mounting instructions for SOT78 (TOAB) package. 3. Epoxy meets UL9 V at /8". August Rev.

7 IRF53N DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 3). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August Rev.

8 This datasheet has been download from: Datasheets for electronics components.

FEATURES SYMBOL QUICK REFERENCE DATA

FEATURES SYMBOL QUICK REFERENCE DATA FEATURES SYMBOL QUICK REFERENCE DATA Trench technology Very low on-state resistance Fast switching Low thermal resistance V DSS = 5 V I D = 75 A R DS(ON) 4.3 mω (V GS = V) R DS(ON) 5 mω (V GS = 5 V) GENERAL

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