3D Integration of MEMS and CMOS via Cu-Cu Bonding with Simultaneous Formation of Electrical, Mechanical and Hermetic Bonds

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1 3D Integration of MEMS and CMOS via Cu-Cu Bonding with Simultaneous Formation of Electrical, Mechanical and Hermetic Bonds R. Nadipalli 1, J. Fan 1, K. H. Li 2,3, K. W. Wee 3, H. Yu 1, and C. S. Tan 1 1 School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore Temasek Laboratories@NTU, Research Techno Plaza, 50 Nanyang Drive, Singapore DSO National Laboratories, 20 Science Park Drive, Singapore Phone: ; *tancs@ntu.edu.sg (J. Fan and R. Nadipalli contributed equally to this work) Abstract- A silicon-on-insulator (SOI) micro-electromechanical system (MEMS) accelerometer, complementary Metal oxide semiconductor (CMOS) readout circuit and simultaneous hermetic encapsulation using low temperature Cu-Cu bonding are investigated for 3D heterogeneous integration of MEMS and CMOS. The MEMS accelerometer is fabricated using bulk micromachining technology. A CMOS-based readout circuit is designed in AMS 0.35μm (2P4M) process. Consequently, hermetic encapsulation by low temperature Cu-Cu thermo-compression bonding has been investigated. According to MIL-STD 883E standard, excellent hermeticity is obtained. A TSV-less stacking method is proposed. Compared with the common integration technologies such as through silicon via (TSV) and wire bonding, this method forms the electrical contact, mechanical support and hermetic seal simultaneously via Cu-Cu thermo-compression bonding. I. INTRODUCTION Compared with two-dimensional semiconductor integration technology which has been developed over the past three decades [1], three-dimensional (3D) integration technology has been widely recognized as the next generation of manufacturing technology for integrated microsystems with ultra-small form factor [2, 3]. This technology can be used to integrate multiple layers of functional electronic blocks into a given chip area. The outstanding advantage of this technology is the possibility of heterogeneous integration [4] which allows building a circuit by stacking active device layers with different fabrication process. In order to miniaturize the integrated microsystems and to achieve the best performance, integration of the MEMS device with the CMOS circuit has become increasingly important in recent years. The SOI technology has been developed to realize several MEMS devices. It has become a very important fabrication technology with its benefit in high aspect ratio, precise control of geometry and potential for integration with CMOS circuits via bonding. Bonding technology is a very common packaging and integration method for 3D integration. Compared with other bonding technologies, metal thermocompression bonding (or diffusion bonding) presents competitive advantages in 3D integration as it allows formation of hermetic sealing, mechanical, and electrical contact in one step. Furthermore, the selection of metal such as copper (Cu) enables bonding at CMOS compatible temperature with better electrical conductivity, mechanical strength, electro-migration resistance and low cost [5]. In this work, one 3D integration technology for MEMS and CMOS process via Cu-Cu bonding is investigated. This MEMS/CMOS integration leads to a simultaneous formation of electrical, mechanical, and hermetic bonds, and hence presents competitive advantages over package-based or monolithic solutions as summarized in Table I. In order to provide a proper operation, the delicate structures should be protected from oxygen corrosion and water vapor content [6] for the internal micro- and nano-scale devices. Therefore, hermetic packaging is absolutely essential in 3D integration. In this approach, a hermetic seal ring is formed during stacking and hence eliminates the need for post-processing to obtain hermetic encapsulation. A SOI-based MEMS accelerometer is designed and fabricated by deep reactive-ion etch (DRIE). A CMOS readout circuit is designed and implemented in AMS 0.35μm (2P4M) process. Consequently, simultaneous hermetic sealing and electrical contact by low temperature Cu-Cu thermo-compression bonding has been investigated for the 3D stacking. A TSV-less 3D integration method which uses routing in CMOS metal layers for the I/O pads is proposed for process simplicity. TABLE I COMPETITIVE ADVANTAGES OF 3D INTEGRATION OF MEMS/CMOS 3D Package/ Monolithic Integration Hybrid Cost Performance Power Functionality Time to market Security Hermetic seal Dedicated Inherent Dedicated

2 (a) (c) (d) Figure 1. Process flow for fabrication of SOI MEMS. (a) SOI wafer preparation (Si 20μm/SiO2 1μm). (b) Deposition of photo-resist. (c) Photoresist patterning and Si device layer etching. (d) SiO 2 etching and photo-resist removal. (b) II. MEMS, CMOS AND VERTICAL STACKING A. SOI MEMS accelerometer The MEMS accelerometer fabrication process flow is outlined in Fig. 1. It starts with a Si/SiO 2 (20μm/1μm) SOI wafer (Fig. 1a) onto which photo-resist 1813 is deposited (Fig. 1b). The DRIE etching windows are patterned photolithographically and the sacrificial layer releasing channels are etched (Fig. 1c). The 20μm structural device layer is released by etching away the 1μm SiO 2 buried oxide in HF (Fig. 1d). The released structure is a comb-drive accelerometer. B. CMOS Readout Circuit A capacitive MEMS readout circuit has been implemented in AMS 0.35µm 2P4M process. The technique of chopper stabilization [7] has been adopted for low noise readout. The system block diagram and the chip micrograph are shown in Fig. 2 and Fig. 3, respectively. The major building blocks are: (1) Low Noise, Band-Pass Gain Stage; (2) Synchronous Demodulator; and (3) Low-Pass Filter. The MEMS is excited using a high frequency sinusoidal signal. The MEMS amplitude-modulates this carrier signal in response to the acceleration experienced. The output of the MEMS goes to a low-noise amplifier, which improves the signal-to-noise ratio. The amplified signal is synchronously demodulated to bring the modulated acceleration signal to base-band. This is followed by an on-chip 2 nd order Sallen-Key low pass filter to remove the high frequency carrier and noise components. C. Vertical Stacking For vertical stacking, both wafer-to-wafer and die-to-wafer are possible. A die-to-wafer approach is chosen as it offers flexibility in the chip size and this is accomplished by bonding the CMOS readout circuit die to the MEMS sensor wafer. Although it is commonly known that the quality of thermocompression bonding can usually be ameliorated when the bonding temperature increases, practical packaging/integration should be achieved at adequately low temperature (typically 300 C or below) for devices that are sensitive to high temperature processing owing to thermal budget limitation and the post-bonding thermo-mechanical stress control. In this work, the bonding medium consists of Cu (300 nm) bonding layer and Ti (50 nm) barrier layer. Cu-Cu can be bonded by thermo-compression method via parallel application of heat and pressure. III. RESULTS AND DISCUSSION A. MEMS Accelerometer Performance The SEM micrograph of the MEMS accelerometer is shown in Fig.4. The structure is properly etched and fully released. The top view of the mass in the center and the comb finger is included in the inset at lower left. In order to ameliorate the releasing rate of the sacrificial layer, holes are etched in the center mass. The suspended structure at the edge of the upper mass is included in the inset at lower right. The resonant frequency of SOI MEMS is measured by a laser vibrometer. The laser vibrometer measures the physical displacement without surface contact. Fig. 5 shows the measured response of the displacement magnitude for the SOI MEMS accelerometer. The response in narrow band with the largest displacement magnitude of 785 nm at its resonant frequency (136 KHz) is shown in Fig. 5a. The response in large band is shown in Fig. 5b. The first mode (fundamental mode) is clearly at 136 KHz and the harmonic modes appear periodically after the fundamental mode. Figure 2. System block diagram. Figure 3. Chip micrograph of the readout circuit.

3 Figure 4. SEM micrograph of the suspended MEMS accelerometer. C. Hermetic Test The cross-sectional SEM image of two bonded nonfunctional chips is shown in Fig. 8. A close-up view showing the bonding of the seal ring and the capping wafer is included in the SEM image at lower right. This structure is used to study the properties of Cu-Cu hermetic seal ring. The bonding interface is clearly marked with an arrow and no void is observed. A high resolution transmission electron microscopy (TEM) image is included in the inset at the lower left. As can be seen from the TEM image, the two Cu layers have fused together during bonding resulting in a homogeneous and seamless interface. The original bonding interface has disappeared and a zig-zag interface is obtained as a result of Cu inter-diffusion and grain growth. In addition, Peng et al. [14] in our research group has recently shown an excellent electrical contact and an outstanding mechanical support for high density 3D interconnect of Cu-Cu contacts. Based on the results presented in this work, Cu-Cu thermo-compression bonding can also simultaneously provide excellent hermetic encapsulation. This is very attractive for packaging the devices which need high hermeticity and for heterogeneous integration of MEMS and CMOS. For example, one can use the CMOS layer as an active cap to protect the sensitive MEMS structure [15] using Cu-Cu seal bonding at low temperature. (a) (b) Figure 5. MEMS response during excitation with laser vibrometer. (a) Response in narrow band. (b) Response in large band. Figure 6. MEMS-like signal input to the readout circuit. B. CMOS Readout Circuit Performance The readout circuit is excited with a MEMS-like signal (Fig.6) using an Arbitrary Waveform Generator. As chopperstabilization has been employed, the input signal will look like an AM-modulated signal with the baseband representing the response to acceleration and the carrier frequency representing the actual chopping carrier at 100 khz. The readout circuit successfully amplifies, demodulates, low-pass filters and recovers the 111 Hz sinusoidal acceleration signal (Fig. 7). The readout has a sensitivity of 5.1mV/g with a ± 30g measurement range. Figure 7. Recovered 111 Hz sinusoidal acceleration signal.

4 TABLE II HELIUM LEAK RATE OF CU THERMO-COMPRESSION BONDING AT 300 C Seal ring size (μm) Helium leak rate (atm.cm 3 /sec) x Figure 8. SEM image of cavity sealed with Cu-Cu bonding. (Lower right inset) SEM image shows the close-up view of the bonding interface. (Lower left inset) TEM images of the bonded Cu-Cu layer and the grain structure. Fig. 9 shows a cross-sectional view of TSV-less stacking method proposed for MEMS and CMOS 3D integration. The seal ring is trenched in SOI MEMS wafer during the device layer DRIE etching. The electrode pad of MEMS is bonded to a connection pad on the CMOS die and will be routed to external by using lower metal layers in the CMOS chip. Metallization process can be realized during the SOI MEMS fabrication. Therefore, the 3D stacking can be achieved as a die to wafer bonding process which needs alignment and follows a similar process to that of the Cu thermo-compression bonding mentioned above. IV. SUMMARY AND CONCLUSION SOI MEMS accelerometer, CMOS read out circuit and Cu- Cu thermo-compression bonding have been tested and verified with reasonable results for 3D integration of MEMS and CMOS. Bulk micromachining technology is used for the SOI MEMS accelerometer fabrication. The resonant frequency of this accelerometer is measured by a Laser Vibrometer. The response in large band indicates the resonant frequency at 136 KHz. A CMOS readout circuit has been designed in a 0.35µm CMOS process employing chopper stabilization. It has a sensitivity of 5.1mV/g. Helium leak test demonstrates that the samples encapsulated (bonding between non-functional cavity wafer and cap wafer) achieve a superior helium leak rate below atm.cm 3 /sec, which is at least one order of magnitude smaller than the reject limit of atm.cm 3 /sec defined by the MILSTD-883E standard. A TSV-less I/O routing 3D integration method is proposed for future integration of CMOS and MEMS. Since Cu-Cu thermocompression bonding can provide electrical, mechanical and hermetic bonds in one step, this TSV-less 3D integration method will simplify the fabrication process and improves yield. Figure 9. 3D stacking of MEMS and CMOS ACKNOWLEDGMENT This work is supported by Defence Science and Technology Agency (DSTA), Singapore. Partial funding is also provided by Nanyang Assistant Professorship supported by Nanyang Technological University (NTU). Authors are grateful for support provided by the management and technical staff in the Nanyang Nano-Fabrication Center at NTU. REFERENCES [1] M. Motoyoshi, "Through-Silicon Via (TSV)," P. IEEE., vol. 97, pp , [2] C. T. Ko and K. N. Chen, "Wafer-level Bonding/stacking Technology for 3D Integration," Microelectron. Reliab., vol. 50, pp , [3] C. S. Tan, J. Fan, D. F. Lim, G. Y. Chong, and K. H. Li, "Low Temperature Wafer-level Bonding for Hermetic Packaging of 3D Microsystems," J. Micromech. Microeng., vol. 21, p , [4] C. S. Tan, "Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack," Microelectron. Eng., vol. 87, pp , [5] J. Fan, D. F. Lim, L. Peng, K. H. Li, and C. S. Tan, "Low Temperature Cu-to-Cu Bonding for Wafer-Level Hermetic Encapsulation of 3D Microsystems," Electrochem. Solid-State Lett., vol. 14, pp. H470-H474, [6] S. H. Lee, J. Mitchell, W. Welch, S. Lee, and K. Najafi, "Wafer-level Vacuum/hermetic Packaging Technologies for MEMS," Reliability, Packaging, Testing, and Characterization of Mems/Moems and Nanodevices Ix, 2010, p [7] Sherman, S.J.; Tsang, W.K.; Core, T.A.; Quinn, D.E.;, "A low cost monolithic accelerometer," VLSI Circuits, Digest of Technical Papers., 1992 Symposium on, vol., no., pp.34-35, 4-6 Jun 1992 [8] "MIL-STD-883E, 1995 method ," ed. [9] Y. Tao and A. P. Malshe, "Theoretical Investigation on Hermeticity Testing of MEMS Packages Based on MIL-STD-883E," Microelectron. Reliab., vol. 45, pp , 2005.

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