Taking advantage of SiC s high switching speeds with optimizations in measurement, layout, and design

Transcription

1 Taking advantage of SiC s high switching speeds with optimizations in measurement, layout, and design Dr. Kevin M. Speer Global Manager of Technology Strategy Power Semiconductors Power Electronics Conference Tuesday 5 December 2017, Munich, Germany 1

2 Outline SiC s benefits over the IGBT Common challenges and best practices Accurate test & measurement Optimized power loop layout Proper gate drive design & integration Summary

3 Outline SiC s benefits over the IGBT Common challenges and best practices Accurate test & measurement Optimized power loop layout Proper gate drive design & integration Summary

4 SiC MOSFETs vs Si IGBTs root cause Si GaN 4H-SiC Diamond* Band gap (ev) Breakdown field (MV/cm) 0.3 ~5 3 to 5 1 to 10 Carrier mobility (cm 2 /V-s) n: 1450 p: 370 n: 900 p: 200 n: 948 p: 99 n: 2000 p: 2100 Saturation velocity ( 10 7 cm/s) Thermal conductivity (W/cm-K) *The ionization energies of diamond are impractically large. For example, SiC s shallow donors are < 100 mev, while diamond s shallow donors are > 1700 mev. 4

5 SiC MOSFETs vs Si IGBTs the compromise To block high voltage, the drift layer of a Si device must be ~10x thicker than for SiC, leading to: enormous conduction losses, since the drift layer is lightly doped, and hence necessity to use of bipolar device architecture for high-voltage silicon Source SiC channel region SiC drift region (1200 V uses ~12 μm) SiC wafer Source Si channel region Si drift region (1200 V needs ~120 μm) Si wafer Drain Drain 5

6 SiC MOSFETs vs Si IGBTs the penalty Yet there are drawbacks to silicon bipolar devices: Minority carriers injected across pn junctions in ON state When switched OFF, they must recombine or be swept out Both processes take time, leading to what is commonly known as reverse recovery Limits switching frequency and presents reliability concerns due to IGBT overstress With SiC, we can make high-voltage devices using a unipolar structure, giving: Reduced switching losses, PLUS Capability to switch at higher speeds 6

7 SiC new possibilities and problems Standard doublepulse test circuit D3 I L V ds (V) I ds (A) x V gs (V) I ds (A) L d Common source, L CSI Power loop, L pwr Gate, L g V g R g L g L CSI L s L pwr V dc Coupled inductance between the gate and power circuit Limits switching speed and increases switching losses Parasitic inductance of the circuit flowing through the power device(s) and load Major influence on voltage spikes during turn-off transient Inductance at the gate which can be part of the package or part of drive circuit High-amplitude, MHz-range oscillations at turnon, creating EMC issues 7

8 Littelfuse device-maker + design assistant We are dealing with high voltages and high currents, and SiC can switch very fast Problems that once went unnoticed with IGBTs have become design roadblocks These design roadblocks then become commercial roadblocks Littelfuse Philosophy As the designer/supplier of revolutionary technology, the responsibility to help knock down design roadblocks rests with us. And everyone wins. 8

9 Outline SiC s benefits over the IGBT Common challenges and best practices Accurate test & measurement Optimized power loop layout Proper gate drive design & integration Summary

10 Measurement challenges It is only through accurate, precise measurement that we can: Fully appreciate the potential benefits of SiC Identify problems at the prototype stage to prevent them at production Typical switching speeds of Si IGBT and SiC MOSFET Si IGBT SiC MOSFET If we don t know it s broken, how can we fix it? dv/dt (V/ns) di/dt (A/ns) Switching time (ns) > 100 < 30 With these switching speeds, high-performance probes are needed to capture finer details of dynamic behavior 10

11 Measurement best practices, Voltage Method Pros Cons Differential probes Voltage divider Passive probes Galvanic isolation High bandwidth High bandwidth Limited bandwidth Requires large resistive load Non-galvanic isolation Requires a common ground Recommendation Despite requiring dedicated isolation and a common ground, passive probes offer the necessary bandwidth to capture ultrafast dynamic nuances without the added bulk and parasitics insertion of a voltage divider. 11

12 Measurement best practices, Current Method Pros Cons Current probe Galvanic isolation Limited bandwidth Recommendation Current transformer Rogowski coil High bandwidth Galvanic isolation Galvanic isolation Flexible tip Saturates at large currents Not suitable for dc Limited bandwidth Not suitable for dc For characterization and evaluation purposes only, the coaxial shunt is an excellent choice due to its bandwidth and accuracy. Coaxial shunt High bandwidth High accuracy Non-galvanic isolation 12

13 Outline SiC s benefits over the IGBT Common challenges and best practices Accurate test & measurement Optimized power loop layout Proper gate drive design & integration Summary

14 System loops concept introduction Consider V DC /2 HS Drive S1 At a high level, the power system has two major loops LOAD Gate-source loops V DC /2 LS Drive S2 14

15 System loops concept introduction Consider V DC /2 HS Drive S1 At a high level, the power system has two major loops LOAD Gate-source loops V DC /2 LS Drive S2 Power loops 15

16 System loops concept introduction Consider V DC /2 HS Drive S1 At a high level, the power system has two major loops LOAD Gate-source loops V DC /2 LS Drive S2 Power loops Common paths 16

17 System loops focus on L pwr Power loops V DC /2 HS Drive S1 LOAD Components L pwr can include: the package (L D and L S ) the overall parasitic inductance of the remaining power loop V DC /2 LS Drive S2 17

18 Power loop layout challenges Problem 1 Voltage overshoot Problem 2 Switching oscillations V ds (V) Caused by combination of parasitic inductance and fast switching speeds (di/dt) Even at small values of L pwr, can exceed typical design margins Generates electromagnetic interference Radiative or conductive coupling into nearby circuits I ds (A) L pwr = 2 nh L pwr = 10 nh User must either slow down switching speed (which negates a benefit of SiC), or select higher-voltage components at higher costs, or resort to more complicated, multi-level topologies Malfunctions in gate drive, protection, etc. Non-compliance with electromagnetic compatibility (EMC) mandates

19 Power loop layout more on overshoot Maximum V DS vs Parasitic inductance 75 V = 12.5% Lpwr Ld Lcsi Lg Ls 125 V = 20.8% Simulations using V DC = 600 V, I L = 20 A, di/dt = 2.5 A/ns, and R g = 5 Ω. (P/N: SIC1MO120E0080) BEWARE! L pwr has substantial effect on overshoot voltage, easily exceeding design margins for modest values of L pwr. Note: Just one pin on a standard TO-247-3L has a parasitic inductance of 7 nh! 19

20 Power loop layout best practices If one bases each design choice around the following best practices, you ll be well on your way to minimizing the effects of power loop inductance! Recommendations 1. Emphasize compactness and simplicity. Board traces should be as short and/or wide as possible to minimize path inductance. 2. Overlap dc+ and dc-. To the greatest degree possible, overlap the dc+ and dc- traces in order to further reduce inductance of power loop. 3. Decoupling capacitor. Connect across dc rails as close as possible to power switches to mask high-frequency noise generated by the power devices from bleeding into the power loop. (results shown in appendix) 20

21 Outline SiC s benefits over the IGBT Common challenges and best practices Accurate test & measurement Optimized power loop layout Proper gate drive design & integration Summary

22 System loops focus on Gate-source, Common Gate-source loops V DC /2 V DC /2 HS Drive LS Drive S1 S2 LOAD Common paths Components Can include: the package (L G and L S ) the overall parasitic inductance of the remaining gate-source loop Also introduced is the common source inductance, L csi 22

23 Gate drive & integration challenges The gate drive circuit has two purposes: 1. Turn on/off the power switches in a stable and well-controlled manner 2. Incorporate intelligent protection when necessary V gs (V) I ds (A) Problem 1 V G overshoot (high L G, L S ) Caused by combination of parasitic inductance and fast switching speeds (di/dt) Can lead to inadvertent turnon and catastrophic shootthrough Excessive oxide fields can also induce device damage and limit lifetime Problem 2 High L csi Resists fast changes in current and slows down switching speed Unnecessarily increases switching losses V ds (V) I ds (A) x

24 Gate drive & integration challenges Problem 1 V G overshoot (high L G, L S ) Caused by combination of parasitic inductance and fast switching speeds (di/dt) Can lead to inadvertent turnon and catastrophic shootthrough Excessive oxide fields can also induce device damage and limit lifetime V gs (V) I ds (A) Even low values of L G result in V GS oscillations well above V th Oscillations in V GS naturally lead to ringing in I DS, which can give rise to EMC issues L G = 2 nh, L G = 10 nh Simulations using V DC = 600 V, I L = 20 A, di/dt = 2.5 A/ns, and R g = 5 Ω. (P/N: LFSIC1MO120E0080). 24

25 Gate drive & integration challenges Problem 2 High L csi Resists fast changes in current and slows down switching speed Unnecessarily increases switching losses E on (uj) vs L csi Here we see how higher values of L csi lead to higher switching losses and undercut a key benefit of SiC E tot (μj) 5 nh 20 nh E off (uj) vs L csi L csi (nh) 25

26 Power loop layout best practices If one bases each design choice around the following best practices, you ll be well on your way to optimizing the design and integration of your gate drive! 1. Reduce length of gate loop as much as possible. This will reduce magnitude of V GS oscillations. 2. Decouple gate loop from power loop. To reduce capacitive coupling and minimize parasitic inductance. This can be done, for instance, using TO-247-4L or TO-263-7L with Kelvin source connections. Recommendations 3. Orthogonal thinking. If possible, put the plane of the gate-source loop perpendicular to the plane of the power loop to reduce inductive coupling. 26

27 Summary Because of its material properties, SiC is poised to disrupt the power electronics community like the IGBT did 30 years ago Due to its high switching speed, new challenges are encountered that we must identify and resolve Measurement Power loop design Gate drive design and integration We have outlined a number of fundamentals and best practices to help designers get off to the right start 27

28 Thank you for your attention!

29 EXTRA SLIDES 29

30 Impact of decoupling capacitors 100ns/di v Gate voltage V gs (20V/div) Drain-source voltage V ds (100V/div) Device current I ds (4A/div) No on-board decoupling cap. 130% V shoot F res =13.2 MHz 20ns/div Gate voltage V gs (20V/div) Drain-source voltage V ds (50V/div) Device current I ds (8A/div) With on-board decoupling cap. 20% V shoot F res =93 MHz 30

31 Device placement to reduce commutation loop Through hole devices: Horizontal power loop Dec. Cap. on board Placement for smallest commutation loop - 25 nh L com Surface mount devices: Vertical power loop Dec. Cap. placed on bottom Minimized commutation loop - 7nH L com 31

32 Copper planes to help simplify routing Reduce voltage drop, maintain the same voltage potential (for digital circuits) Reduce loop inductance and loop resistance, reduce radiated noise (dc bus) High frequency mirror current control (EMI noise reduction) Increase capacitive coupling with other circuits Adding copper plane is not always good, only add plane when necessary 32

33 Mirror current control Current only propagates through lowest impedance path For high frequency current, current return through its mirror current path Copper plane HF LF Stitching capacitor HF signal line through split copper planes HF signal line through vias Trace routing with mirror current control 33

34 There are some basic guidelines Discrete packaging Adding Kelvin source to alleviate L CSI Advanced interconnect methodologies to optimize L S and L G Layout support Assist with board design and layout to optimize L pwr and decouple L S and L G Ground plane design and mirror current control for EMI reduction Module packaging Simplify customer integration of high-current components Advanced attach and interconnect methodologies to optimize R th and L s Design tools Tailored support using decades of device and applications expertise Evaluation kits, reference designs, and demo boards 34