NCP Current-Mode PWM Controller for Off-line Power Supplies

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1 NCP11 Curren-Mode PWM Conroller for Off-line Power Supplies The NCP11 is a highly inegraed PWM conroller capable of delivering a rugged and high performance offline power supply in a iny TSOP 6 package. Wih a volage supply range up o 35 V, he conroller hoss a jiered 65 khz or 1 khz swiching circuiry operaed in peak curren mode conrol. When he power on he secondary side sars decreasing, he conroller auomaically folds back is swiching frequency down o a minimum level of 26 khz. As he power furher goes down, he par eners skip cycle while limiing he peak curren. Over Power Proecion (OPP) is a difficul exercise especially when no load sandby requiremens drive he converer specificaions. The ON Semiconducor proprieary inegraed OPP allows harness he maximum delivered power wihou affecing he sandby performance simply via wo exernal resisors. An Over Volage Proecion (OVP) inpu is also combined on he same pin and proecs he whole circuiry in case of opocoupler desrucion or adverse open loop operaion. Finally, a imer based shor circui proecion offers he bes proecion scheme, allowing precisely selec he proecion rip poin wihou caring of a loose coupling beween he auxiliary and he power windings. NCP11 is improved and pin compaible conroller based on very popular flyback conroller NCP1. Feaures Fixed Frequency 65 khz or 1 khz Curren Mode Conrol Operaion Frequency Foldback Down o 26 khz and Skip Cycle in Ligh Load Condiions Frequency Jiering in Normal and Frequency Foldback Modes Inernal and Adjusable Over Power Proecion (OPP) Circui Auo Recovery Over Volage Proecion (OVP) on he VCC Pin Inernal and Adjusable Slope Compensaion Inernal Fixed 4 ms Sof Sar Auo Recovery or Lached Shor Circui Proecion Pre Shor Ready for Lached OCP Version OVP/OTP Lach Inpu for Improved Robusness 3 ma/ 5 ma Source/Sink Drive Capabiliy Improved Consumpion Improved Rese Time in Lach Sae High Robusness and High ESD Capabiliies GND FB EPS 2. Complian This is a Pb Free Device 1 TSOP 6 (SOT23 6) SN SUFFIX CASE 318G STYLE 13 PIN CONNECTIONS 1 2 DRV OPP/Lach 3 4 CS (Top View) Typical Applicaions Ac dc Converers for TVs, Se op Boxes and DVD Players Offline Adapers for Noebooks and Nebooks 6 5 V CC MARKING DIAGRAM 5DxAYW 1 5Dx = Specific Device Code x = A, 2, C, J, or K A = Assembly Locaion Y = Year W = Work Week = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering, marking and shipping informaion on page 2 of his daa shee. Semiconducor Componens Indusries, LLC, 216 November, 217 Rev. 3 1 Publicaion Order Number: NCP11/D

2 NCP11 Figure 1. Typical Applicaion Example Table 1. PIN DESCRIPTION Pin No Pin Name Funcion Pin Descripion 1 GND The conroller ground. 2 FB Feedback pin Hooking an opocoupler collecor o his pin will allow regulaion. 3 OPP/Lach Adjus he Over Power Proecion Laches off he par 4 CS Curren sense slope compensaion A resisive divider from he auxiliary winding o his pin ses he OPP compensaion level during he on ime. When he volage exceeds a cerain level a urn off, he par is fully lached off. This pin moniors he primary peak curren bu also offers a means o inroduce slope compensaion. 5 V CC Supplies he conroller proecs he IC This pin is conneced o an exernal auxiliary volage. When he V CC exceeds a cerain level, he par eners an auo recovery hiccup. 6 DRV Driver oupu The driver oupu o an exernal MOSFET gae. Table 2. DEVICE OPTIONS AND ORDERING INFORMATION Conroller (Noe 1) Package Marking OCP Proecion OVP/OTP Proecion NCP11ASN65T1G 5DA Lached Lached 65 khz NCP11BSN65T1G 5D2 Auo recovery Lached 65 khz NCP11CSN65T1G 5DC Auo recovery Auo recovery 65 khz NCP11ASN1T1G 5DJ Lached Lached 1 khz NCP11BSN1T1G 5DK Auo recovery Lached 1 khz Swiching Frequency Package Shipping TSOP 6 (Pb Free) 3 / Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD811/D. 1. Oher opions available upon cusomer reques. 2

3 NCP11 OPP/ Lach V OPP V CC(OVP) _ Vlach lach(del) RST Up Couner o 4 DRV sop Lach / Auorecovery mode Lach / Auo-revery managemen Noe: depend on IC opion V CC(min) OVP/OTP Lach OCP Faul Pre-shor lach(blank) OVP/OTP Lach DRV pulse IC sar IC sop IC rese V CC and logic managemen Lach / Auorecovery mode Pre-shor logic available only for lached OCP version Armed flag V CC(on) Inernal supply V CC(OVP) OVP(del) _ VCC 1 s DRV pulse during IC sar S Q Pre-shor V OVP IC in regulaion R Q V CC(min) Clamp DRV pulse DRV pulse R ramp Jiering Frequency foldback 65 / 1 khz Oscillaor D max S Q DRV R Q IC sop _ DRV pulse DRV sop V FB(open) Vskip IC in regulaion R eq K raio FB _ Up couner o 8 peak curren freeze Sof-sar RST Error flag CS LEB V OPP V limi V OPP _ R S Q Q RST Faul imer OCP Faul V limi GND Figure 2. Inernal Circui Archiecure 3

4 NCP11 Table 3. MAXIMUM RATINGS TABLE Symbol Raing Value Uni V CC Power Supply volage, VCC pin, coninuous volage.3 o 35 V V DRV(ran) Maximum DRV pin volage when DRV in H sae, ransien volage (Noe 1).3 o V CC.3 V V CS, V FB, V OPP Maximum volage on low power pins CS, FB and OPP (Noe 2).3 o 5.5 V V OPP(ran) Maximum negaive ransien volage on OPP pin (Noe 2) 1 V I source,max Maximum sourced curren, pulsed widh < 8 ns.6 A I sink,max Maximum sinked curren, pulse widh < 8 ns 1. A I OPP Maximum injeced negaive curren ino he OPP pin (pin 3) 2 ma R θj A Thermal Resisance Juncion o Air 36 C/W T J,max Maximum Juncion Temperaure 15 C Sorage Temperaure Range 6 o 15 C HBM Human Body Model ESD Capabiliy per JEDEC JESD22 A114F (All pins) 4 kv CDM Charged Device Model ESD Capabiliy per JEDEC JESD22 C11E V Sresses exceeding hose lised in he Maximum Raings able may damage he device. If any of hese limis are exceeded, device funcionaliy should no be assumed, damage may occur and reliabiliy may be affeced. 1. The ransien volage is a volage spike injeced o DRV pin being in high sae. Maximum ransien duraion is 1 ns. 2. See he Figure 3 for deailed specificaion of ransien volage. 3. This device conains lach up proecion and exceeds 1 ma per JEDEC Sandard JESD78. V on-ime 5 ns Max curren during overshoo can ' exceed 3 ma V OPP () V CS V FB V OPP 7.5 V Max ransien volage cycle-by-cycle V OPP -1 V V OPP, max V OPP,max = -. V, T j =- C V OPP,max = -.65 V, T j = C V OPP,max =-.3V,T j =1 C Wors case V OPP mus say beween V and.3 V for a linear OPP operaion SOA 5.5 V Max DC volage 5 ns V Figure 3. Negaive Pulse for OPP Pin during On ime and Posiive Pulse for All Low Power Pins 4

5 NCP11 Table 4. ELECTRICAL CHARACTERISTICS (For ypical values T J = C, for min/max values T J = 4 C o 1 C, V CC = 12 V unless oherwise noed) Symbol Raing Pin Min Typ Max Uni SUPPLY SECTION V CC(on) V CC increasing level a which driving pulses are auhorized V V CC(min) V CC decreasing level a which driving pulses are sopped V V CC(hys) Hyseresis V CC(on) V CC(min) V V CC(rese) Lached sae rese volage V V CC(rese_ hys) Defined hyseresis beween minimum and rese volage V CC(min) V V CC(rese) V CC(lach_hys) Defined hyseresis for hiccupping beween wo volage levels in lach mode 5.55 V I CC1 Sar up curren (V CC(on) 1 mv) A I CC2 Inernal IC consumpion wih V FB = 3.2 V, f SW = 65 khz and C L = nf ma Inernal IC consumpion wih V FB = 3.2 V, f SW = 1 khz and C L = nf I CC3 Inernal IC consumpion wih V FB = 3.2 V, f SW = 65 khz and C L = 1 nf Inernal IC consumpion wih V FB = 3.2 V, f SW = 1 khz and C L = 1 nf I CC(no load) Inernal consumpion in skip mode non swiching, V FB = V 5 3 A I CC(faul) Inernal consumpion in faul mode during going down V CC cycle, V FB = 4 V I CC(sandby) Inernal IC consumpion in skip mode for 65 khz version (V CC = 14 V, driving a ypical 7 A/6 V MOSFET, includes opo curren) (Noe 4) ma 5 37 A 5 42 A DRIVE OUTPUT r Oupu volage rise C L = 1 nf, 1 9% of oupu signal 6 4 ns f Oupu volage fall C L = 1 nf, 1 9% of oupu signal 6 3 ns R OH Source resisance, V CC = 12 V, I DRV = 1 ma 6 28 R OL Sink resisance, V CC = 12 V, I DRV = 1 ma 6 7 I source Peak source curren, V GS = V 6 3 ma I sink Peak sink curren, V GS = 12 V 6 5 ma V DRV(low) DRV pin level a V CC = V CC(min) 1 mv wih a 33 k resisor o GND 6 8 V V DRV(high) DRV pin level a V CC = V OVP 1 mv (DRV unloaded) V CURRENT COMPARATOR V limi Maximum inernal curren se poin T J = C pin 3 grounded Maximum inernal curren se poin T J = 4 C o 1 C pin 3 grounded V CS(fold) Inernal volage sepoin for frequency foldback rip poin 59% of V limi 4 4 mv V CS(freeze) Inernal peak curren sepoin freeze ( 31% of V limi ) 4 mv DEL Propagaion delay from CS pin o DRV oupu ns LEB Leading Edge Blanking Duraion 4 3 ns SS Inernal sof sar duraion acivaed upon sarup or auo recovery 4 4 ms I OPPs Se poin decrease for pin 3 grounded 3 % I OPPo Se poin decrease for pin 3 biased o mv % I OOPv Volage se poin for pin 3 biased o mv, T J = C V Volage se poin for pin 3 biased o mv, T J = 4 o 1 C INTERNAL OSCILLATOR f OSC(nom) Oscillaion frequency (65 khz version) Oscillaion frequency (1 khz version) D max Maximum duy raio % f jier Frequency jiering in percenage of f OSC jier is kep even in foldback ±5 % mode 4. Applicaion parameer for informaion only M resisor is conneced from pin 4 o he ground for he measuremen V khz 5

6 NCP11 Table 4. ELECTRICAL CHARACTERISTICS (For ypical values T J = C, for min/max values T J = 4 C o 1 C, V CC = 12 V unless oherwise noed) Symbol Raing Pin Min INTERNAL OSCILLATOR f swing Swing frequency 24 Hz FEEDBACK SECTION R eq Inernal equivalen feedback resisance 2 29 k K raio FB pin o curren se poin division raio 4 V FB(freeze) Feedback volage below which he peak curren is frozen V V FB(limi) Feedback volage corresponding wih maximum inernal curren se poin V V FB(open) Inernal pull up volage on FB pin 2 4 V FREQUENCY FOLDBACK V fold(sar) Frequency foldback level on he FB pin 59% of maximum peak curren 1.9 V f rans Minimum operaing frequency khz V fold(end) End of frequency foldback feedback level, f sw = f rans 1.5 V V skip Skip cycle level volage on he feedback pin.8 V V skip(hys) Hyseresis on he skip comparaor 5 mv INTERNAL SLOPE COMPENSATION V ramp Inernal ramp C (Noe 5) V R ramp Inernal ramp resisance o CS pin 4 2 k PROTECTIONS V lach Laching level inpu on OPP/Lach pin V lach(blank) Blanking ime afer Drive oupu urn off 3 1 s lach(coun) Number of clock cycles before lach is confirmed 3 4 lach(del) OVP/OTP delay ime consan before lach is confirmed 3 6 ns V OVP Over volage proecion on he VCC pin V OVP(del) Delay ime consan before OVP on VCC is confirmed 5 2 s faul Inernal faul imer duraion ms 4. Applicaion parameer for informaion only M resisor is conneced from pin 4 o he ground for he measuremen. Typ Max Uni 6

7 NCP11 TYPICAL CHARACTERISTICS V CC(on) (V) V CC(rese) (V) Figure 4. Figure V CC(min) (V) V CC(rese_hys) (mv) Figure 6. Figure V CC(hys) (V) V CC(lach_hys) (V) Figure 8. Figure 9. 7

8 NCP11 TYPICAL CHARACTERISTICS I CC1 ( A) I CC(no load) ( A) Figure 1. Figure I CC2 (ma) khz 1 1 I CC(faul) ( A) Figure 12. Figure I CC3 (ma) khz 1 1 I CC (ma) V IN = 12 Vac ADAPTER OUTPUT CURRENT (A) Figure 14. Figure 15. 8

9 NCP11 TYPICAL CHARACTERISTICS 65 5 r (ns) R OH ( ) Figure 16. Figure f (ns) V DRV(low) (V) Figure 18. Figure R OL ( ) V DRV(high) (V) Figure 2. Figure 21. 9

10 NCP11 TYPICAL CHARACTERISTICS V limi (V) DEL (ns) Figure 22. Figure V CS(fold) (mv) 5 45 LEB (ns) Figure 24. Figure V CS(freeze) (mv) SS (ms) Figure 26. Figure 27. 1

11 NCP11 TYPICAL CHARACTERISTICS khz I OPPv (V) f OSC(nom) (khz) Figure 28. Figure I OPPo (%) 35 3 D max (%) Figure 3. Figure f OSC(nom) (khz) khz f swing (Hz) Figure 32. Figure

12 NCP11 TYPICAL CHARACTERISTICS R eq (k ) V fold(sar) (V) Figure 34. Figure K raio ( ) V fold(end) (V) Figure 36. Figure V FB(freeze) (V) V skip (V) Figure 38. Figure

13 NCP11 TYPICAL CHARACTERISTICS V skip(hys) (mv) V OVP (V) Figure 4. Figure f rans (khz) faul (ms) Figure 42. Figure V lach (V) Figure

14 NCP11 APPLICATION INFORMATION Inroducion NCP11 implemens a sandard curren mode archiecure where he swich off even is dicaed by he peak curren se poin. This componen represens he ideal candidae where low par coun and cos effeciveness are he key parameers, paricularly in low cos ac dc adapers, open frame power supplies ec. Updaed conroller, he NCP11 packs all he necessary componens normally needed in oday modern power supply designs, bringing several enhancemens such as a non dissipaive OPP, OVP/OTP implemenaion, shor circui proecion wih pre shor ready for lached version and improved consumpion, robusness and ESD capabiliies. Curren mode operaion wih inernal slope compensaion: implemening peak curren mode conrol a a 65 or 1 khz swiching frequency, he NCP11 offers an inernal slope compensaion signal ha can easily by summed up o he sensed curren. Sub harmonic oscillaions can hus be fough via he inclusion of a simple resisor in series wih he curren sense informaion. Inernal OPP: by rouing a porion of he negaive volage presen during he on ime on he auxiliary winding o he dedicaed OPP pin (pin 3), he user has a simple and non dissipaive means o aler he maximum peak curren se poin as he bulk volage increases. If he pin is grounded, no OPP compensaion occurs. If he pin receives a negaive volage, hen a peak curren is reduced down. Low sarup and sandby curren: reaching a low no load sandby power always represens a difficul exercise when he conroller draws a significan amoun of curren during sarup. The NCP11 brings improved consumpion o easing he design of low sandby power adapers. EMI jiering: an inernal low frequency modulaion signal varies he pace a which he oscillaor frequency is modulaed. This helps spreading ou energy in conduced noise analysis. To improve he EMI signaure a low power levels, he jiering is kep in frequency foldback mode (ligh load condiions). Frequency foldback capabiliy: a coninuous flow of pulses is no compaible wih no load/ligh load sandby power requiremens. To excel in his domain, he conroller observes he feedback pin and when i reaches a level of V fold(sar), i sars reduce swiching frequency. When he feedback level reaches V fold(end), he frequency his is lower sop a f rans. When he feedback pin goes furher down and reaches V FB(freeze), he peak curren sepoin is inernally frozen. Below his poin, if power coninues o drop, he conroller eners classical skip cycle mode, as boh frequency and peak curren are frozen. Inernal sof sar: a sof sar precludes he main power swich from being sressed upon sar up. The sof sar duraion is inernally fixed for ime SS and i is acivaed during new sarup sequence or during recovering afer auo recovery double hiccup. Lach inpu: he conroller includes a lach inpu (pin 3) ha can be used o sense an over volage or an over emperaure even on he adaper. If his pin is brough higher han he inernal reference volage V lach for four consecuive cycles, hen he circui is lached off V CC hiccups from V CC(min) volage level wih hyseresis V CC(lach_hys) = 55 mv ypically, unil a rese occurs. The lach rese occurs when he user disconnecs he adaper from he mains and les he V CC falls below he V CC(rese) level. For he C version, despie an OVP/OTP deecion, he circui auorecovers and never laches. Auo recovery OVP on V CC : an OVP proecs he circui agains V CC runaways. If he faul is presen a leas for ime OVP(del) hen he OVP is validaed and he conroller eners double hiccup mode. When he V CC reurns o a nominal level, he conroller resumes operaion. Shor circui proecion: shor circui and especially overload proecions are difficul o implemen when a srong leakage inducance beween auxiliary and power windings affecs he ransformer (he aux winding level does no properly collapse in presence of an oupu shor). In his conroller, every ime he inernal maximum peak curren limi V limi is acivaed (or less when OPP is used), an error flag is assered and a ime period sars hanks o an inernal imer. When he imer has elapsed while a faul is sill presen, he conroller is lached or eners an auo recovery mode, depending on he seleced OCP opion. Please noe ha wih acive Pre shor opion (could be acive only for lached OCP version), he par becomes sensiive o he firs UVLO even during he sar up sequence. Any oher UVLO evens are ignored aferwards auo recovery operaion. Wih he firs drive pulse is generaed armed flag. Armed flag is rese afer he firs successful sar up sequence (he conroller ges ino regulaion). This is o pass he pre shor es a power up:). 1. if he inernal armed flag is acive and an UVLO even is sensed, he par is immediaely lached. 2. if an UVLO signal is deeced bu he armed flag is no assered, double hiccup auo recovery occurs. 3. if he conroller ges ino regulaion, he armed flag is rese. Then UVLO even is sensed, he par is in auo recovery operaion. 14

15 NCP11 Sar up Sequence The NCP11 sar up volage is made purposely high o permi large energy sorage in a small V CC capacior value. This helps operae wih a small sar up curren which, ogeher wih a small V CC capacior, will no hamper he sar up ime. To furher reduce he sandby power, he sar up curren of he conroller is exremely low, below 1 A. The sar up resisor can herefore be conneced o he bulk capacior or direcly o he mains inpu volage o furher reduce he power dissipaion. R sar-up Inpu mains C bulk VCC C VCC aux. winding Figure 45. The sarup resisor can be conneced o he inpu mains for furher power dissipaion reducion. The firs sep sars wih he calculaion of he needed VCC capacior which will supply he conroller which i operaes unil he auxiliary winding akes i over. Experience shows ha his ime 1 can be beween 5 and 2 ms. If we consider we need a leas an energy reservoir for a 1 ime of 1 ms, he VCC capacior mus be larger han: C VCC I CC 1 V CC(on) V CC(min) 1.7 m 1 m F (eq. 1) Le us selec a 2.2 F capacior a firs and experimens in he laboraory will le us know if we were oo opimisic for he ime 1. The VCC capacior being known, we can now evaluae he charging curren we need o bring he V CC volage from V o he V CC(on) of he IC. This curren has o be seleced o ensure a sar up a he lowes mains (85 V rms ) o be less han 3 s (2.5 s for design margin): V CC(on) C VCC I charge 16 A (eq. 2) sar up 2.5 If we accoun for he 1 A (maximum) ha will flow o he conroller, hen he oal charging curren delivered by he sar up resisor mus be 26 A. If we connec he sar up nework o he mains (half wave connecion hen), we know ha he average curren flowing ino his sar up resisor will be he smalles when V CC reaches he V CC(on) of he conroller: I CVCC,min V ac,rms 2 V CC(on) (eq. 3) R sar up To make sure his curren is always greaer han 26 A, hen, he minimum value for R sar up can be exraced: R sar up V ac,rms 2 V CC(on) I CVCC(min) k (eq. 4) This calculaion is purely heoreical, considering a consan charging curren. In realiy, he ake over ime can be shorer (or longer!) and i can lead o a reducion of he VCC capacior. Thus, a decrease in charging curren and an increase of he sar up resisor can be experimenally esed, for he benefi of sandby power. Laboraory experimens on he prooype are hus mandaory o fine une he converer. If we chose he k resisor as suggesed by Equaion 4, he dissipaed power a high line amouns o: V 2 ac,peak P Rsar up,max 4 R sar up k 35 mw (eq. 5) Now ha he firs VCC capacior has been seleced, we mus ensure ha he self supply does no disappear when in no load condiions. In his mode, he skip cycle can be so deep ha refreshing pulses are likely o be widely spaced, inducing a large ripple on he VCC capacior. If his ripple is oo large, chances exis o ouch he V CC(min) and rese he conroller ino a new sar up sequence. A soluion is o grow his capacior bu i will obviously be derimenal o he sar up ime. The opion offered in Figure 45 eleganly solves his poenial issue by adding an exra capacior on he auxiliary winding. However, his componen is separaed 15

16 NCP11 from he VCC pin via a simple diode. You herefore have he abiliy o grow his capacior as you need o ensure he self supply of he conroller wihou affecing he sar up ime and sandby power. Inernal Over Power Proecion There are several known ways o implemen Over Power Proecion (OPP), all suffering from paricular problems. These problems range from he added consumpion burden on he converer or he skip cycle disurbance brough by he curren sense offse. A way o reduce he power capabiliy a high line is o capialize on he negaive volage swing presen on he auxiliary diode anode. During he urn on ime, his poin dips o N 2 V bulk, where N 2 being he urns raio beween he primary winding and he auxiliary winding. The negaive plaeau observed on Figure 46 will have ampliude depending on he inpu volage. The idea implemened in his chip is o sum a porion of his negaive swing wih he inernal volage reference V limi =.8 V. For insance, if he volage swings down o 15 mv during he on ime, hen he inernal peak curren se poin will be fixed o he value.8 V.15 V = 65 mv. The adoped principle appears in Figure 47 and shows how he final peak curren se poin is consruced. Le s assume we need o reduce he peak curren from 2.5 A a low line, o 2 A a high line. This corresponds o a 2% reducion or a se poin volage of 64 mv. To reach his level, hen he negaive volage developed on he OPP pin mus reach: V OPP.8 V limi V limi mv (eq. 6) 1 v(24) N 1 (V ou V f ) off ime 1 Plo1 v(24) in vols 2. N 2 V bulk 4. on ime 464u 472u 48u 488u 496u ime in seconds Figure 46. The signal obained on he auxiliary winding swings negaive during he on ime. 16

17 NCP11 R OPPU This poin will be adjused o reduce he ref a hi line o he desired level V CC aux. winding swings o: N 1 V ou during off -N 2 V in during on I OPP OPP K1 K2 SUM ref =.8V V OPP (V OPP is negaive) ref _ driver rese R OPPL V limi =.8V ±7% CS R sense Figure 47. The OPP circuiry affecs he maximum peak curren se poin by summing a negaive volage o he inernal volage reference. Le us assume ha we have he following converer characerisics: V ou = 19 V V in = 85 o 265 V rms N 1 = N p :N s = 1:. N 2 = N p :N aux = 1:.18 Given he urns raio beween he primary and he auxiliary windings, he on ime volage a high line (265 V rms ) on he auxiliary winding swings down o: V aux N 2 V in,max V (eq. 7) To obain a level as imposed by Equaion 7, we need o insall a divider feauring he following raio: Div V OPP m (eq. 8) V aux 67.5 If we arbirarily fix he pull down resisor R OPPL o 1 k, hen he upper resisor can be obained by: R OPPU V aux V OPP V OPP R OPPL k (eq. 9).16 1k If we now plo he peak curren se poin obained by implemening he recommended resisor values, we obain he following curve, as shown in Figure 48. Peak curren sepoin 1% 8% 3 V Figure 48. The peak curren regularly reduces down o 8% a 3 Vdc. V bulk 17

18 NCP11 The OPP pin is surrounded by Zener diodes sacked o proec he pin agains ESD pulses. These diodes accep some peak curren in he avalanche mode and are designed o susain a cerain amoun of energy. On he oher side, negaive injecion ino hese diodes (or forward bias) can cause subsrae injecion which can lead o an erraic circui behavior. To avoid his problem, he pin is inernal clamped slighly below 3 mv which means ha if more curren is injeced before reaching he ESD forward drop, hen he maximum peak reducion is kep o 4%. If he volage finally forward biases he inernal zener diode, hen care mus be aken o avoid injecing a curren beyond 2 ma. Given he value of R OPPU, here is no risk in he presen example. Finally, please noe ha anoher comparaor inernally fixes he maximum peak curren se poin o value V limi even if he OPP pin is adversely biased above V. Frequency f SW Frequency Foldback The reducion of no load sandby power associaed wih he need for improving he efficiency, requires a change in he radiional fixed frequency ype of operaion. This conroller implemens a swiching frequency foldback when he feedback volage passes below a cerain level, V fold(sar). A his poin, he oscillaor urns ino a Volage Conrolled Oscillaor (VCO) and reduces swiching frequency down o f rans value, ill o feedback volage reaches he level V fold(end). Below his level V fold(end), he frequency is fixed and canno go furher down. The peak curren sepoin is following he feedback pin unil is level reaches V FB(freeze). Below his value, he peak curren sepoin is frozen o V CS(freeze) value or 31% of he maximum V limi sepoin. The only way o furher reduce he ransmied power is o ener skip cycle, which is se when he feedback volage reaches he level V skip. Skip cycle offers he bes noise free performance in no load condiions. Figure 49 and depics he adoped scheme for he par. Peak curren sepoin V CS V limi max FB f OSC(nom) V CS(fold) f rans V CS(freeze) min V skip V fold(end) V fold(sar) V FB(open) V FB(limi) V FB V skip V FB(freeze) V fold(sar) V FB(limi) V FB Figure 49. By observing he volage on he feedback pin, he conroller reduces is swiching frequency for an improved performance a ligh load. V FB [V] V FB(open) V FB(limi) V fold(sar) V fold(end) f SW is fixed o f OSC(nom) f SW is changing Open loop f OSC(nom) f rans I peak, max Peak curren is clamped Peak curren is changing V FB(freeze ) V skip Skip mode I peak, min Peak curren is frozen Figure 5. Anoher look a he relaionship beween feedback and curren sepoin while in frequency reducion mode. 18

19 NCP11 Auo Recovery Shor Circui Proecion In case of oupu shor circui or if he power supply experiences a severe overloading siuaion, an inernal error flag is raised and he faul imer sars coundown. If he UVLO has come (see Figure 51 Shor circui case I.) or he error flag is assered hroughou he faul ime (see Figure 51 Shor circui case II.) i.e. he faul imer has elapsed, he driving pulses are sopped and he V CC falls down as he auxiliary volage are missing. When he supply volage V CC ouches he V CC(min) level, he conroller consumpion is down o a few A and he V CC slowly builds up again hanks o he resisive sarup nework. When V CC reaches V CC(on), he conroller purposely ignores he re sar and wais for anoher V CC cycle: his is he so called double hiccup auo recovery mode. Illusraion of such principle appears in Figure 51. Please noe ha sof sar is acivaed upon every re sar aemp. V CC () V CC(on) Shor-circui case I. -> Error flag raised -> UVLO -> auo-recovery Shor-circui case II. -> Error flag raised -> Faul imer elapsed -> auo-recovery V CC(min) V DRV () Error flag V CS () SS Faul imer has elapsed Faul imer has elapsed V limi Figure 51. An auo recovery double hiccup mode is enered in case a fauly even longer han programmable faul imer value is acknowledged by he conroller. Lached Shor Circui Proecion wih Pre Shor In some applicaions, he conroller mus be fully lached in case of an oupu shor circui presence. In ha case, you would selec a conroller wih an OCP lached opion in he Opions able. When he error flag is assered, meaning he conroller is asked o deliver is full peak curren, he conroller laches off afer he elapse of faul imer i.e. he pulses are immediaely sopped and V CC hiccups beween wo volage levels, given by a V CC(min) level and added hyseresis V CC(lach_hys), unil a rese occurs (V CC falls down below V CC(rese) ). However, in presence of damaged or old VCC capacior, i can very well be he case where he sored energy does no give enough ime o le he imer elapse before V CC ouches he UVLO level. When his happens, he lach is no acknowledged since he imer coundown has been premaurely abored. To avoid his siuaion, he NCP11 is equipped wih Pre shor logic for OCP lached opion, i.e. he Pre shor canno be used for auo recovery OCP opion. The Pre shor logic combines he armed flag asserion ogeher wih he UVLO even o confirm a pre shor siuaion: upon sar up wih firs drive pulse, he armed flag is raised unil regulaion is me. If during he ime he flag is raised an UVLO even is deeced, he par laches off immediaely. When IC is lached, V CC eners hiccup mode. In normal operaion, if an UVLO even is deeced for any reason, he conroller will naurally resume operaions. Deails of his behavior are given in Figure 52. Pre shor logic is acive during he sar up sequence, i.e. he firs sarup of power supply or afer recovering from double hiccup mode. The armed flag is assered wih he firs drive pulse. If an UVLO even occurs when he armed flag is assered, he par immediaely laches off. If no UVLO occurs, once he oupu volage has reached regulaion in 8 consecuive cycles, he inernal armed flag is rese (pre shor logic is no acive anymore unil new sarup of power supply) and any new UVLO evens will auo recovery. Pre shor logic is available only on cusomer reques. I is no acive in sandard devices. 19

20 NCP11 V CC () lached new sequence resumed resumed lached V CC(on) V CC(lach_hys) V CC(min) V CC(rese) V DRV () AND armed flag glich UVLO afer regulaion NO armed flag AND armed flag Armed flag 1 1 V CS () 8 cycles 8 cycles V limi Figure 52. Full lach occurs in case he up is deeced while he armed flag is assered V CC () lached resar lached V CC(on) V CC(lach_hys) The V CC hyseresis in lach mode significanly improves he rese ime. V CC(min) V CC(rese) V DRV () Armed flag Error flag V CS () 1 8 cycles Faul imer has elapsed When he IC is lached, he user have o unplugged and plugged he adaper o he oule Armed flag Error flag SS AND armed flag V limi Figure 53. Full lach occurs in case he faul imer has elapsed or up is deeced wih assered armed flag. 2

21 NCP11 Operaion wih Grounded Feedback Pin The NCP11 offers he operaion mode when he NCP11 could be conrolled by Maser sysem via Feedback pin (pin 2). When FB pin is grounded, he conroller driver pulses are sopped. This is he same siuaion, when he conroller is in skip mode, bu wih he difference ha FB pin could be forced o ground by Maser sysem anyime during operaion, even a sar up sequence. When he V CC ouches V CC(on) level, he conroller inernal logic sars and hus, firs DRV pulse is auhorized afer he safey period of 2 s passes. Bu he las DRV pulse can comes jus before V CC(min) level. Therefore, here are exended rules o generaion and cancellaion he armed flag o avoid he false pre shor condiion if he conroller can sar properly because of he grounded FB pin. V FB () lached new sequence lached new sequence lached gnd V CC () V CC(on) V CC(lach_hys) V CC(min) V CC(rese) V DRV () Armed flag V CS () 1 AND armed flag Grounded CC(on) No Armed flag 1 AND armed flag Grounded goingdown V CC cycle Double hiccup swiching allowed every odd V CC(on) 1 UVLO AND Armed flag V limi Figure 54. The conroller sar up sequence wih grounded FB pin and Pre shor condiion. V FB () V CC () gnd auo-recovery gnd auo-recovery new sequence gnd auo-recovery gnd V CC(on) V CC(min) V CC(rese) V DRV () UVLO and NO armed flag UVLO UVLO and NO armed flag Armed flag V CS () V limi cycles cycles Figure 55. The conroller behaviour during sar up sequence ineruped by grounded FB pin. 21

22 NCP11 The armed flag is generaed wih firs DRV pulse, bu only if he firs DRV pulse is synchronized wih V CC(on) even. If he FB pin is forced o ground during he V CC(on) even and i is released aferwards, he armed flag is no generaed. The Figure 54 shows he cases of grounded FB pin a he beginning of sar up sequence. If he armed flag isn acive and UVLO comes, he conroller newly sars afer double hiccup auo recovery sequence. Then, if UVLO comes again, he conroller is lached off. DRV pulses are auhorized during he whole firs V CC going down cycle. If any DRV pulse doesn come during his ime, he double hiccup auo recovery sequence is coming. The armed flag could be canceled by wo condiions. When he conroller ges ino regulaion afer sar up sequence, i.e. during he eigh consecuive swiching cycles is curren sepoin volage under V limi, he armed flag is called off his is he firs armed flag cancelaion condiion. When he sar up sequence isn complee and is inerruped by grounded FB pin, he armed flag is called off his is he second armed flag cancelaion condiion. The Figure 55 shows he cases of inerruped sar up sequence by grounded FB pin. If he sar up sequence is inerruped by grounded FB pin, he armed flag is canceled. Then, if UVLO comes, he conroller newly sars afer double hiccup auo recovery sequence. Then, if UVLO comes again, he conroller is lached off. The Figure 56 shows he case of operaion, when he conroller can operae under some maser sysem wih superordinae funcion. Then, he FB pin is used for auhorizaion or denial DRV pulses. If he normal operaion sae is inerruped for a long ime and aferwards he sof sar is demanded for proper sar up of power supply, he V CC have o be pulled down below V CC(rese) level. Then, if he FB isn grounded, he new sar up sequence are iniialized when V CC ouches V CC(on) level 2 s safey period. During his new sar up sequence is generaed he armed flag. V FB () new sequence gnd gnd gnd V CC () V CC(on) V CC(min) V CC(rese) V DRV () Supply volage V CC is conrolled by Maser Sysem Sop DRV pulses by Maser Syem The IC mus be rese o ensure he sof-sar afer release he FB Armed flag V CS () 1 8 cycles Grounded CC(on) No Armed flag 8 cycles 1 8 cycles V limi Figure 56. The Maser sysem driving he conroller by forcing he FB pin o ground. Slope Compensaion The NCP11 includes an inernal slope compensaion signal. This is he buffered oscillaor clock delivered during he on ime only. Is ampliude is around 2.5 V a he maximum duy raio. Slope compensaion is a known means used o cure sub harmonic oscillaions in CCM operaed curren mode converers. These oscillaions ake place a half he swiching frequency and occur only during Coninuous Conducion Mode (CCM) wih a duy raio greaer han 5%. To lower he curren loop gain, one usually injecs beween 5 and 1% of he primary inducance downslope. Figure 57 depics how he ramp is generaed inernally. Please noe ha he ramp signal will be disconneced from he CS pin during he off ime. 22

23 NCP V D max T SW V Driver rese ON ime R ramp 2 kω LEB _ CS R comp R sense From FB Figure 57. Insering a resisor in series wih he curren sense informaion brings slope compensaion and sabilizes he converer in CCM operaion. In he NCP11 conroller, he oscillaor ramp feaures a 2.5 V swing. If he clock operaes a a 65 khz frequency, hen he available oscillaor slope corresponds o: S ramp V ramp,peak mv s (eq. 1) D max T SW.8 15 In our flyback design, le s assume ha our primary inducance L p is 77 H, and he SMPS delivers 19 V wih a N p :N s raio of 1:.. The off ime primary curren slope S p is hus given by: S p Vou V f N s N p L p (19.7) 4 12 ma s 77 (eq. 11) Given a sense resisor of 33 m, he above curren ramp urns ino a volage ramp of he following ampliude: S sense S p R sense 12 m mv s (eq. 12) If we selec 5% of he downslope as he required amoun of slope compensaion, hen we shall injec a ramp whose slope is 17 mv/ s. Our inernal compensaion being of 28 mv/ s, he divider raio (divraio) beween R comp and he inernal R ramp = 2 k resisor is: divraio.5 S sense S ramp.82 (eq. 13) The series compensaion resisor value is hus: R comp R ramp divraio 2 k k (eq. 14) A resisor of he calculaed value will hen be insered from he sense resisor o he curren sense pin. We recommend adding a small capacior of 1 pf, from he curren sense pin o he conroller ground for an improved immuniy o he noise. Please make sure boh componens are locaed very close o he conroller. Laching Off he Conroller The OPP pin no only allows a reducion of he peak curren se poin in relaionship o he line volage, i also offers a means o permanenly lach off he par. When he par is lached off, all pulses are immediaely sopped and V CC hiccups from V CC(min) volage level wih hyseresis V CC(lach_hys) unil a rese occurs (V CC falls down below level V CCrese ), e.g. by un plugging he converer from he mains oule. The V CC lach hyseresis helps significanly reduce he rese ime, because when he user unplugged he adaper from he oule in he less favorable ime (V CC is in is maximum), he V CC has o fall down from volage level given by 55 mv 3 mv ypically o rese level. The lach deecion is made by observing he OPP pin by a comparaor feauring a V lach reference volage. However, for noise reasons and in paricular o avoid he leakage inducance conribuion a urn off, a blanking delay lach blank is inroduced before he oupu of he OVP comparaor is checked. Then, he OVP comparaor oupu is validaed only if is high sae duraion lass for a minimum ime lach del. Below his value, he even is ignored. Then, a couner ensures ha only 4 successive OVP evens have occurred before acually laching he par. There are several possible implemenaions, depending on he needed precision and he parameers you wan o conrol. The firs and easies soluion is he addiional resisive divider on op of he OPP one. This soluion is simple and inexpensive bu requires he inserion of a diode o preven disurbing he OPP divider during he on ime. 23

24 NCP11 V lach () The IC is lached afer he faul is confirmed for 4 consecuive DRV cycles V lach The user unplugged and plugged he adaper o he oule V CC () V CC(on) V CC(lach_hys) V CC(min) V CC(rese) V DRV () The ime needs for IC rese is significanly shorer due o he V CC hyseresis used in lach mode. Figure 58. Laching off he conroller and resuming operaion. R OVP R OPPU D 1 V CC C 1 1p R OPPL OPP/ Lach _ Vlach OVP OPP aux. winding Figure 59. A simple resisive divider brings he OPP pin above 3 V in case of a V CC volage runaway above 18 V. Firs, calculae he OPP nework wih he above equaions. Then, suppose we wan o lach off our conroller when V ou exceeds V. On he auxiliary winding, he plaeau reflecs he oupu volage by he urns raio beween he power and he auxiliary winding. In case of volage runaway for our 19 V adaper, he plaeau will go up o: V aux,ovp V ou N s V (eq. 15) N aux. Since our OVP comparaor rips a level V lach = 3 V, across he 1 k seleced OPP pull down resisor, i implies a 3 ma curren. From 3 V o go up o 18 V, we need an addiional 15 V. Under 3 ma and neglecing he series diode forward drop, i requires a series resisor of: R OVP V ou V aux,ovp V lach V OVP R OPPL k 3 1k (eq. 16) In nominal condiions, he plaeau esablishes o around 14 V. Given he divide by 6 raio, he OPP pin will swing o 14/6 = 2.3 V during normal condiions, leaving 7 mv for he noise immuniy. A 1 pf capacior can be added o improve i and avoid erraic rips in presence of exernal surges. Do no increase his capacior oo much oherwise he OPP signal will be affeced by he inegraing ime consan. A second soluion for he OVP deecion alone is o use a Zener diode wired as recommended by Figure V R OPPU D 1 V CC C 1 22p R OPPL OPP / Lach _ Vlach OVP OPP aux. winding Figure 6. A Zener diode in series wih a diode helps o improve he noise immuniy of he sysem. 24

25 NCP11 In his case, o sill rip a 18 V level, we have seleced a 15 V Zener diode. In nominal condiions, he volage on he OPP pin is almos V during he off ime as he Zener is fully blocked. This echnique clearly improves he noise immuniy of he sysem compared o ha obained from a resisive sring as in Figure 59. Please noe he reducion of he capacior on he OPP pin o 1 22 pf. This is because of he poenial spike going hrough he Zener parasiic capacior and he possible auxiliary level shorly exceeding is breakdown volage during he leakage inducance rese period (hence he inernal blanking delay lach blank a urn off). This spike despie is very shor ime is energeic enough o charge he added capacior C 1 and given he ime consan, could make i discharge slower, poenially disurbing he blanking circui. When implemening he Zener opion, i is imporan o carefully observe he OPP pin volage (shor probe connecions!) and check ha enough margin exiss o ha respec. Over Temperaure Proecion In a lo of designs, he adaper mus be proeced agains hermal runaways, e.g. when he emperaure inside he adaper box increases a cerain value. Figure 61 shows how o implemen a simple OTP using an exernal NTC and a series diode. The principle remains he same: make sure he OPP nework is no bohered by he addiional NTC hence he presence of his diode. NTC D 1 R OPPU V CC R OPPL OPP/ Lach _ Vlach OVP OPP aux. winding Figure 61. The inernal circuiry hooked o OPP/Lach pin can be used o implemen over emperaure proecion (OTP). When he NTC resisor will diminish as he emperaure increases, he volage on he OPP pin during he off ime will slowly increase and, once i passes V lach level for 4 consecuive clock cycles, he conroller will permanenly lach off. Back o our 19 V adaper, we have found ha he plaeau volage on he auxiliary diode was 14 V in nominal condiions. We have seleced an NTC which offers a 47 k resisance a C and drops o 8.8 k a 11 C. If our auxiliary winding plaeau is 14 V and we consider a.7 V forward drop for he diode, hen he volage across he NTC in faul mode mus be: V NTC V aux V lach V F V (eq. 17) Based on he 8.8 k NTC resisor a 11 C, he curren inside he device mus be: I NTC V NTC R NTC(11) k 1.2 ma (eq. 18) As such, he boom resisor R OPPL, can easily be calculaed: R OPPL V lach I NTC 2.5 k (eq. 19) Now he pull down OPP resisor is known, we can calculae he upper resisor value R OPPU o adjus he power limi a he chosen oupu power level. Suppose we need a 2 mv decrease from he V limi sepoin and he on ime swing on he auxiliary anode is 67.5 V, hen we need o drop over R OPPU a volage of: V ROPPU V aux V OPP V (eq. 2) The curren circulaing he pull down resisor R OPPL in his condiion will be: I ROPPL V OPP.2 8 A (eq. 21) R OPPL 2.5 k The R OPPU value is herefore easily derived: R OPPU V ROPPU I ROPPU k (eq. 22) Combining OVP and OTP The OTP and Zener based OVP can be combined ogeher as illusraed by Figure 62. In nominal V CC /oupu condiions, when he Zener is no acivaed, he NTC can drive he OPP pin and rigger he adaper in case of a faul. On he conrary, in nominal emperaure condiions, if he loop is broken, he volage runaway will be deeced and acknowledged by he conroller. In case he OPP pin is no used for eiher OPP or OVP, i can simply be grounded.

26 NCP11 15 V D 1 NTC R OPPU V CC R OPPL OPP / Lach _ Vlach OVP OPP aux. winding Figure 62. Wih he NTC back in place, he circui nicely combines OVP, OTP and OPP on he same pin. Filering he Spikes The auxiliary winding is he sea of spikes ha can couple o he OPP pin via he parasiic capaciances exhibied by he Zener diode and he series diode. To preven an adverse riggering of he Over Volage Proecion circuiry, we recommend he insallaion of a small RC filer before he deecion nework as illusraed by Figure 63. The values of resisance and capaciance mus be seleced o provide he adequae filering funcion wihou degrading he sand by power by an excessive curren circulaion. 15 V D 1 Addiional filer NTC R OPPU R 1 C 1 V CC R OPPL OPP/ Lach _ Vlach OVP OPP aux. winding Figure 63. A small RC filer prevens he fas rising spikes from reaching he proecion pin OPP/lach in presence of energeic perurbaions superimposed on he inpu line. 26

27 NCP11 PACKAGE DIMENSIONS TSOP 6 CASE 318G 2 ISSUE V E1 NOTE 5 e.5 A1 6 1 D b E A c L H M DETAIL Z DETAIL Z L2 GAUGE PLANE C SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. MILLIMETERS DIM MIN NOM MAX A A b c D E E e L L2. BSC M 1 RECOMMENDED SOLDERING FOOTPRINT* 6X.6 STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN X PITCH DIMENSIONS: MILLIMETERS *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. ON Semiconducor and are rademarks of Semiconducor Componens Indusries, LLC dba ON Semiconducor or is subsidiaries in he Unied Saes and/or oher counries. ON Semiconducor owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of ON Semiconducor s produc/paen coverage may be accessed a /sie/pdf/paen Marking.pdf. ON Semiconducor reserves he righ o make changes wihou furher noice o any producs herein. ON Semiconducor makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does ON Semiconducor assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Buyer is responsible for is producs and applicaions using ON Semiconducor producs, including compliance wih all laws, regulaions and safey requiremens or sandards, regardless of any suppor or applicaions informaion provided by ON Semiconducor. Typical parameers which may be provided in ON Semiconducor daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. ON Semiconducor does no convey any license under is paen righs nor he righs of ohers. ON Semiconducor producs are no designed, inended, or auhorized for use as a criical componen in life suppor sysems or any FDA Class 3 medical devices or medical devices wih a same or similar classificaion in a foreign jurisdicion or any devices inended for implanaion in he human body. Should Buyer purchase or use ON Semiconducor producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold ON Semiconducor and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha ON Semiconducor was negligen regarding he design or manufacure of he par. ON Semiconducor is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor E. 32nd Pkwy, Aurora, Colorado 811 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semiconducor Websie: Order Lieraure: hp:///orderli For addiional informaion, please conac your local Sales Represenaive NCP11/D

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