TIME-BASED ANALOG-TO-DIGITAL CONVERTERS

Transcription

1 TIME-BASED ANALOG-TO-DIGITAL CONVERTERS By DAZHI WEI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005

2 Copyright 2005 by Dazhi Wei

3 To my family.

4 ACKNOWLEDGMENTS First, I wish to express my sincere gratitude to my advisor, Dr. John Harris, for the things he taught me over the years, his support and encouragement. Without his patience and guidance this work would have been impossible. I would like to thank Dr. José C. Principe, Dr. Robert M. Fox, and Dr. Timothy Davis for being on my committee and their frequent helpful advice. I would also like to thank Dr. José A.B. Fortes for his support in the bio-nano computing project. I also appreciate the helpful discussions from people in the Computational Neuroengineering Lab. I am deeply grateful to my parents, brother and sister for their support and love. Thanks are also extended to my dear son, Frank, for his coming to this world and making this work more meaningful. Last, I would like to thank my darling wife, Xiaoyan Zhang, for her love and belief in me. iv

5 TABLE OF CONTENTS page ACKNOWLEDGMENTS iv LIST OF TABLES viii LIST OF FIGURES ix ABSTRACT xii ChAPTER INTRODUCTION Background Motivation Dissertation Structure TIME-BASED ANALOG-TO-DIGITAL CONVERTERS Introduction Signal Representation Conventional Analog-to-digital Converters (C-ADCs) Time-based Analog-to-digital Converters (TB-ADCs) Comparison Between the C-ADC and the TB-ADC SPIKING NEURON SIGNAL REPRESENTATION Introduction Biological Neuron Integrate-and-fire Neuron Models Integrate-and-fire Neuron Model Leaky Integrate-and-fire Neuron with Refractory Period Model Integrate-and-fire Neuron with Threshold Adaptation Summary v

6 4 RECONSTRUCTION FROM SPIKING NEURON MODELS Introduction Direct Low-pass Filtering Reconstruction Method WLPK Reconstruction Method Reconstruction from the IF neuron Reconstruction from LIF neuron with refractory period Reconstruction from the IF neuron with threshold adaptation Discussion of Other Reconstruction Methods PRACTICAL ISSUES RELATED TO SPIKING NEURON TB-ADC IMPLEMENTATION Introduction Implementation of Spiking Neuron TB-ADC Practical Issues Related to Signal Encoding in Spiking Neuron Models Frequency Aliasing of the Input Signal Leaky Integration of the Integrator Thermal Noise of the Spiking Neuron Signal Dependent Reference Variation of the Comparator Practical Issues Related to Reconstruction from Spiking Neuron Models Timing Jitter of the Time Quantizer Kernel Selection of the DSP Reconstruction Algorithm Discussion IMPLEMENTATION AND TEST OF AN SPIKING NEURON CHIP Introduction Circuit Implementation of the Transconductor Circuit Implementation of the IF Neuron Neuron chip layout Neuron chip Test Results parameter Sine Wave Fitting Test Sine Wave Histogram Test Discussion IMPLEMENTATION AND TEST OF AN ASYNCHRONOUS DELTA SIGMA CONVERTER vi

7 7. Introduction Asynchronous Delta Sigma Converter Architecture Signal Reconstruction Algorithm Circuit Implementation Integrator Schmitt Trigger and -bit DAC Chip Layout Chip Test Results Circuit Implementation Integrator and -bit DAC Schmitt Trigger Chip Layout Chip Test Results TIME-BASED ADC VARIATIONS Introduction Clocked Neuron Models Globally Clocked Neuron Locally Clocked Neuron Level-Mode Time-based ADCs Level Crossing Sampling TB-ADC Sawtooth Wave Crossing Sampling TB-ADC Discussion CONCLUSIONS REFERENCES BIOGRAPHICAL SKETCH vii

8 Table LIST OF TABLES page 2 Characteristics of the C-ADC and the TB-ADC Performance comparison of the reconstruction using truncated Gaussian kernel and truncated Sinc kernel Performance comparison of the reconstruction using truncated Gaussian kernel and truncated Sinc kernel for 4 khz average firing rate spike train Signal to noise ratio due to different noise sources The transistor sizes for the transconductance amplifier The transistor sizes for the IF neuron Neuron chip performance metric The asynchronous delta sigma converter chip performance metric Input and output transition table of the Schmitt trigger (V in rises from below V rl to above V rh, and then drops below V rl ) The asynchronous delta sigma converter chip 2 performance metric.. 05 viii

9 Figure LIST OF FIGURES page 2 Signal representations. (a) Analog signal. (b) Sample and hold signal. (c)asynchronous digital signal. (d)digital signal Block diagram of the conventional ADC Block diagram of the time-based ADC Structure of a typical biological neuron Structure of the IF neuron Shapes of the V mem and the spike of the IF neuron Shapes of the V mem and the spike waveform of the LIF neuron Shapes of the V mem, S(t) and the spike waveform of the IF neuron with threshold adaptation Spectrum of the spike train from the IF neuron Reconstruction results from the IF neuron. (a) The spike train. (b) The original and reconstructed signals. (c) The error between the original and the reconstructed signals Block diagram of the spiking neuron TB-ADC Plot of SNR vs. aliasing frequency Schematic of the leaky integrator SNR vs. output resistance SNR vs. Sine wave amplitude SNR vs. Sine wave frequency Noise model of the spiking neuron SNR vs. thermal noise current power spectral density Signal dependent reference voltage variation of the comparator. High and low slew rate are shown as solid or dashed respectively Plots of coefficients C and C2 for signal dependent threshold variation 52 ix

10 5 SNR vs. comparator time constant Plot of SNR vs. clock period used in reconstruction Plot of Sinc kernel vs. kernel length Plot of SNR using the truncated Sinc kernel vs. signal length used in the reconstruction Plot of Gaussian kernel vs. kernel length Plot of SNR using the truncated Gaussian kernel vs. signal length used in the reconstruction Plots of the row vector of the matrix C using Sinc and Gaussian kernels. (a) 20th row. (b) 80th row Windowing scheme of the DSP reconstruction algorithm Schematic of the transconductance amplifier Latches with a positive feedback. (a) Capacitive feedback latch. (b) Current feedback latch Schematic of the neuron circuit Layout of the neuron chip Plot of the SNR vs. sine wave amplitude of the spiking neuron chip Plot of the SNR vs. sine wave frequency of the spiking neuron chip Plots of the DNL and INL from the sine wave histogram test of the spiking neuron chip Architecture of the asynchronous delta sigma converter Circuit implementation of the Schmitt trigger (M0-3) and the -bit DAC (M4-5) Layout of the asynchronous delta sigma converter chip Plot of the SNR vs. sine wave amplitude of the asynchronous delta sigma converter chip (the sine wave frequency is khz, the converter signal bandwidth is 6 khz, and 0 dbfs refers to 0.2 V full scale amplitude) Plot of the SNR vs. sine wave frequency of the asynchronous delta sigma converter chip (the sine wave amplitude is -2.5 dbfs) x

11 7 6 Plots of the DNL and INL from the sine wave histogram test of the asynchronous delta sigma converter chip Integrator implementation with -bit DAC Block diagram of the Schmitt trigger Delay unit of the schmidtt trigger Layout of the asynchronous delta sigma converter chip Plot of the SNR vs. sine wave amplitude of the asynchronous delta sigma converter chip Plot of the SNR vs. sine wave frequency of the asynchronous delta sigma converter chip Plot of the DNL and INL from the sine wave histogram test of the asynchronous delta sigma converter chip Reference voltage waveform, capacitor voltages and spikes for clocked neuron models Reconstruction of the globally clocked neuron. (a) Spike train and Vref waveform. (b) Original and reconstructed signals Reconstruction of the locally clocked neuron. (a) Spike train and Vref waveform. (b) Original and reconstructed signals Reconstruction of the level crossing sampling TB-ADC. (a) Spike train and Vref waveform. (b) Original and reconstructed signals Reconstruction of the sawtooth wave crossing sampling TB-ADC. (a) Spike train and Vref waveform. (b) Original and reconstructed signals xi

12 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy TIME-BASED ANALOG-TO-DIGITAL CONVERTERS By Dazhi Wei August 2005 Chair: John G. Harris Major Department: Electrical and Computer Engineering We present the concept and some implementations of time-based analog-todigital converters (TB-ADCs). The TB-ADC employs a fundamentally different architecture from the conventional ADC and achieves data conversion by representing signals as a series of discrete time events. This novel architecture trades off simpler analog circuitry on the front end for more complex digital circuitry on the back end, and is very promising for low power applications. We show that theoretically we can use the weighted low-pass kernel (WLPK) method to perfectly reconstruct the signal for the TB-ADCs. This method can also be extended to solve general nonuniform sampling problems. We investigate the effect of different low-pass kernels such as Sinc and Gaussian on the reconstruction performance and computation cost. We also extensively analyze the fundamental performance limitation of the spiking neuron TB-ADC due to nonidealities such as frequency aliasing, leaky integration, thermal noise, signal-dependent threshold variation, and time jitter. Much of this analysis can be extended to other TB- ADC implementations. We also discuss some other TB-ADC variations including clocked neurons and level-mode TB-ADCs. Test results of several prototype chips xii

13 implemented in 0.5 um CMOS technology process suggest that high resolution and low power consumption TB-ADCs are achievable in practice. xiii

14 CHAPTER INTRODUCTION. Background The scaling trends of very large scale integration (VLSI) CMOS processes have continued to bring us higher speed and lower power digital circuitry every year. The international technology road map for semiconductors (2003 edition) has predicted that this scaling trend will continue until well into the next decade. For example, the transistor minimum gate length and the power supply voltage are predicted to reach 7nm and 0.5V respectively by 208 []. Since this scaling is optimized mostly for the performance improvement of digital circuitry, some analog design issues such as voltage swing, intrinsic device gain and noise are severely compromised, and high performance analog circuitry will be difficult to design [2]. Therefore the signal processing trend is to continue to move more and more functionality from analog circuitry to digital circuitry. The design of analog-to-digital converters (ADCs) also follows the same trend. Analog-to-digital converters are employed to acquire and digitize analog signal so that the signal can be processed by digital processors. Conventional ADCs are realized based on the design scheme of sample, hold and amplitude quantization. The resolution of conventional ADCs is determined in the amplitude, or voltage domain. Because the available voltage swing continues to shrink due to the VLSI process scaling, high resolution ADC design based on conventional design schemes faces more and more challenges. Although synchronous delta sigma modulation is a successful technique to improve the ADC performance [3, 4], its oversampling nature demands high power consumption and limits its application.

15 2 New ADC implementations based on time quantization have been investigated to alleviate drawbacks such as the reduced voltage swing, and to take advantage of the high speed circuitry brought about by the VLSI scaling [5 7]. One common feature in these implementations is that the signal is represented in the time domain during data conversion. These implementations are called time-based ADCs since their r esolution is determined in the time domain, which is a marked difference from conventional ADCs. Allier et al. have designed a new class of asynchronous ADCs based on level-crossing sampling and time quantization [5]. The ADC power consumption is observed to be one order of magnitude less than conventional ADCs for similar performance. However a reconstruction algorithm is not discussed in the implementation to convert the nonuniformly sampled sequence to the uniformly sampled sequence. Roza previously proposed an ADC implementation using asynchronous delta-sigma modulation and time quantization [6]. The implementation uses an inherent direct low-pass filtering method to reconstruct the signal. To achieve some specific ADC performance, a large oversampling ratio is needed to suppress higher order harmonic distortions. Lazar and Toth have realized an iterative algorithm method based on nonuniform sampling theory to theoretically achieve perfect signal reconstruction from the asynchronous delta-sigma modulation [7]. This method is not easy to apply to other general time-based ADC implementations, and the effects of nonidealities on the ADC performance were not extensively studied..2 Motivation The first motivation of this dissertation is to investigate possibilities of time-based ADC implementations. The signal reconstruction algorithm is a key component to determine the performance of the implementations. We will develop a general algorithm that can be efficiently applied to all time-based ADC architectures.

16 3 The second motivation is to characterize the effects of nonidealities on the ADC performance. Effects of nonidealities on conventional ADC performance have been extensively studied. However, due to different sampling and quantization scheme, these nonidealities have different effects on time-based ADC performance and need to be investigated to guide practical designs. The third motivation is to strive for the high resolution and low power TB- ADC circuit implementations. Novel architecture and circuit design techniques need to be studied to achieve better ADC performance..3 Dissertation Structure This dissertation consists of nine chapters and is organized as follows. In Chapter we introduce the background of the ADC implementations and present some motivations of this dissertation. Chapter 2 reviews the architecture of the conventional ADCs, gives the definition and architecture of the time-based ADC, and summarizes comparison between these two types of ADCs. In Chapter 3 we will talk about the spiking neuron models which can serve as the encoder in the time-based ADC implementations. Biological neuron models will also be briefly reviewed. Chapter 4 introduces a theoretically perfect signal reconstruction algorithm which can be applied to general time-based ADC architectures. The performance of the algorithm is verified through signal reconstruction from different types of spiking neuron models. In Chapter 5 we investigate effects of some nonidealities on the performance of the time-based ADC. For the spiking neuron encoding component we consider the frequency aliasing of the input signal, finite DC gain of the integrator, thermal noise of the spiking neuron, and the signal dependent threshold of the comparator.

17 4 For the DSP reconstruction component, we consider the timing jitter of the time quantizer, the kernel selection and the windowing of the DSP algorithm. In Chapter 6 we present the circuit implementation of the spiking neuron timebased ADC. We consider some practical issues and make some tradeoffs during the implementation. The performance of the neuron chip is measured based on the IEEE ADC test standard. Chapter 7 will present a time-based ADC implementation based on the asynchronous delta-sigma modulation which includes the architecture, the detailed circuit implementation, the signal reconstruction algorithm, and the measured chip performance. In Chapter 8 we will discuss other time-based ADC variations and give some simulation results of the implementations. Finally, the conclusions will be given in Chapter 9.

18 CHAPTER 2 TIME-BASED ANALOG-TO-DIGITAL CONVERTERS 2. Introduction In this chapter we first review different types of signal representations. Based on different transient signal representations used during data conversion, we give definitions of the conventional and the time-based ADCs. Finally we conclude this chapter with a comparison between these two types of ADCs. 2.2 Signal Representation The signal being processed by ADCs is typically a one-dimensional signal which can be represented by a voltage or current amplitude varying in time. Based on whether the amplitude and time variables are continuous or discrete, ADCs may deal with 4 types of signals during data conversion, i.e., analog signals, sample-and-hold signals, asynchronous digital signals and digital signals, which are shown in Figure 2 (a), (b), (c) and (d), respectively. The black dots in the figure represent the sample points of the signal. ADCs are used to convert the analog signal, which is continuous in both amplitude and time, to a digital signal, which is discrete in both amplitude and time. Signals with discrete amplitude can be more accurately restored through buffering in a noisy environment; therefore the digital signal and the asynchronous digital signal are more robust to noise. The digital signal and the sample and hold signal are usually uniformly sampled sequences, and can be reconstructed back to an analog signal through simple low-pass filtering based on Nyquist sampling theory. Therefore, the sample and hold signal is easy to reconstruct but sensitive to the noise while the asynchronous digital signal is robust to noise but difficult to be reconstructed because of the nonuniform sampling. The sample and hold signal and the asynchronous digital signal are two possible 5

19 6 Continuous Time Discrete Continuous Amplitude Amplitude Discrete Amplitude Amplitude (a) Time Amplitude (b) Time (c) Time (d) Time Figure 2 : Signal representations. (a) Analog signal. (b) Sample and hold signal. (c)asynchronous digital signal. (d)digital signal transient signal representations that can be used during data conversion. The characteristics of ADCs are determined by different transient signal representations used in implementations. 2.3 Conventional Analog-to-digital Converters (C-ADCs) The conventional ADC (C-ADC) realizes the data conversion through the scheme of clock sampling and amplitude quantization. Figure 2 2 shows a typical architecture of the conventional ADC [2]. The sampling frequency f s, i.e., the clock Analog signal S/H signal Digital signal Antialiasing Filter Sampling Circuit Amplitude Quantizer Encoder f s Analog circuitry Digital circuitry Figure 2 2: Block diagram of the conventional ADC

20 7 frequency, must be larger than two times the maximum signal frequency to avoid frequency aliasing according to Nyquist sampling theory. Therefore an antialiasing filter is strictly required to remove frequency components higher than f s /2 from the input analog signal. The sampling circuit samples the filter output by recording the amplitudes at integer numbers of the clock period. This sampling method is called amplitude sampling. The resulting sample-and-hold signal perfectly represents the filter output without any information loss based on the Nyquist sampling theory. Later the signal amplitude is approximated with fixed reference levels by an amplitude quantizer and then converted to a digital signal by an encoder. This approximation error, which is also called quantization noise, determines that the filter output cannot be perfectly reconstructed from the digital signal, resulting in the finite resolution of the ADC. In practice besides the amplitude quantization noise there are many other error sources such as thermal noise and nonlinear distortions during the data conversion. The difference between the original filter output and the reconstructed signal from the digital signal is due to the effect of all these error sources. In this dissertation we do not differentiate the difference among these error sources and use the word noise to represent all of them. The resolution of the ADC is related to the signal to noise ratio (SNR) as described below: SNR = P Signal P Noise = (6.02N +.76)dB (2.) where N is the effective number of bits resolution of the ADC. The definition of the SNR in this dissertation is equivalent to definitions such as the signal to error ratio (SER), or the signal to noise and distortion ratio (SINAD) in other literatures. There is another class of conventional ADC called synchronous delta sigma ADC which is based on oversampling and noise shaping techniques. It shares a similar block diagram as shown in Figure 2 2. The analog signal is sampled using such a high sampling frequency f s that only a small part of the amplitude

21 8 Analog signal Asynchronous digital signal Digital signal Antialiasing Filter Encoder Time Quantizer DSP Reconstruction Analog circuitry T c Digital circuitry Figure 2 3: Block diagram of the time-based ADC quantization noise falls into the signal band, and then the noise is shaped by a negative feedback in such a way that most of the noise is pushed out of the signal band while preserving the in-band signal. A decimation filter (the encoder in Figure 2 2) is needed to low-pass and downsample the quantizer output to obtain the digital signal at the Nyquist rate. In this way the constraints on the quantizer are relaxed while achieving high SNR at the cost of additional complexity on the encoder. 2.4 Time-based Analog-to-digital Converters (TB-ADCs) From above we see that C-ADCs quantize amplitude at predefined time intervals. On the other hand, time-based ADCs (TB-ADCs) achieve data conversion through a scheme of quantizing time at predefined amplitude intervals. The TB- ADC block diagram is shown in Figure 2 3. An antialiasing filter works in the same way as that in the C-ADC to make sure the filter output is a bandlimited signal. An encoder performs the sampling operation and converts the filter output to a asynchronous digital signal. The encoder records the time stamps whenever the amplitude of the filter output, or the amplitude of the transformation of the filter output, crosses some predefined references. This sampling method is called time sampling. Examples using time sampling method are level-crossing sampling (amplitude is the reference level when the sampling happens), and pulse position modulation (amplitude is the sawtooth wave value at the sampling instant). The asynchronous digital signal is then synchronized to a time quantizer, i.e., a clock,

22 9 Table 2 : Characteristics of the C-ADC and the TB-ADC C-ADC TB-ADC Sampling method Amplitude sampling Time sampling Amplitude Quantized Exactly known Time Exactly known Quantized and the sample time stamps are approximated to the nearest integer number of clock periods T c. This approximation error, or time quantization noise, determines the finite resolution of the ADC. Since the digital signal to be processed by current DSP technology is uniformly sampled, a DSP reconstruction algorithm is required to convert the nonuniform samples with time quantization to the uniformly sampled digital signal. Obviously the efficiency of the DSP reconstruction algorithm is expected to affect the resolution of the ADC. Similar to conventional ADCs although maybe in different ways, other error sources during data conversion also degrade the ADC performance. Again we use the word noise to represent the total effect due to these nonidealities. The signal-to-noise ratio is defined and related to the resolution of the ADC in a similar way as in Equation Comparison Between the C-ADC and the TB-ADC Table 2 summarizes the different characteristics of the C-ADC and the TB-ADC we have discussed in previous sections. This characteristic difference is mainly due to the different transient signals (sample and hold signal, asynchronous digital signal) used by the C-ADCs and the TB-ADCs during data conversion. For C-ADCs the sample time is exactly known and the signal information is encoded in the unknown and quantized amplitude. On the contrary, for TB-ADCs the sample amplitude is exactly known and the signal information is encoded in the unknown and quantized time. That is the reason why we may call the TB-ADC a dual case of the C-ADC [5]. Clearly the implementations of the C-ADCs and TB-ADCs have different characteristics.

23 0 The first difference between C-ADC and TB-ADC is the position of the quantizer in the ADC implementation. From Figures 2 2 and 2 3 it is clearly seen that quantization of TB-ADC uses conventional digital circuitry while C- ADC is quantized with conventional analog circuitry. Analog circuitry faces more difficult tradeoffs among power, noise and resolution compared to digital circuitry. This difference means the TB-ADC can better utilize the high speed and low power digital circuitry to obtain improved ADC performance while relaxing the requirement on the analog circuitry. The second difference is that TB-ADC can be split into a transmitter side and a receiver side while C-ADC can only be used in the transmitter side. The asynchronous digital signal in TB-ADC is already discrete in amplitude and robust to noise and thus suitable for long distance transmission, while the sample and hold signal in C-ADC is continuous in amplitude and not suitable for transmission. This means TB-ADC is capable of saving power on the transmitter side and thus a better candidate for power limited applications. The third difference is that TB-ADC uses a signal driven sampling method while C-ADC uses a signal independent sampling method. The sampling frequency of the C-ADC is a constant and equals to the clock frequency. Even when the signal is negligible the C-ADC still outputs at the same sampling frequency and consumes unnecessary power. Since TB-ADC uses a signal driven sampling method, the ADC may be implemented to output at a low sampling frequency in regions of low interest. One example of the signal driven sampling method is that stronger signals trigger more samples while weaker signals trigger fewer samples. This can further reduce power consumption wasted in sampling negligible signals. The last difference is that the reconstruction part of the TB-ADC is a nonuniform sampling problem while that of C-ADC is a uniform one. Good reconstruction performance can be achieved by simple low-pass filtering for C-ADC. It will be

24 seen that for the TB-ADC simple low-pass filtering leads to poor reconstruction performance, and a more complicated reconstruction algorithm should be carefully implemented to avoid degrading the performance of the ADC. In summary, the TB-ADC trades off simpler analog circuitry for more complex digital circuitry, which is reasonable since high speed and powerful digital circuitry is easily realized. This tradeoff is also a good way to deal with the challenges brought about by VLSI scaling.

25 CHAPTER 3 SPIKING NEURON SIGNAL REPRESENTATION 3. Introduction The neuron is a fundamental unit of biological nervous systems [8, 9]. Since these systems are characterized by incredible pattern recognition performance with ultra low power consumption, it is wise to understand these strategies in the design of low power engineering systems. Thus the study in neural encoding is expected to provide some hints to build more efficient man-made devices such as ADCs. In this chapter we first introduce the structure and the encoding processing of the biological neuron, and then present several simplified spiking neuron models which can serve as the encoders in TB-ADC structures. 3.2 Biological Neuron Most information in this section is from van Schaik s PhD dissertation [0] and Mead s book []. Figure 3 shows the structure of a typical biological neuron. Nearly all neurons use spikes to communicate with one other. The spike, or action potential, is a voltage pulse. All neural spikes share a similar shape and thus the information is believed to be encoded in the spike time. The neuron receives spikes from other neurons axons by synapses on its dendrites and cell body, and the cell body processes the information and generates its own spikes at the axon hillock which then travel along its axon to other neurons. Spike generation is a very important component of neural encoding. Hodgkin and Huxley developed a model to describe the spike generation in the squid axon in 952 [2]. The inside of the neuron is high in potassium concentration while the outside extracellular liquid is high in sodium concentration. The cell membrane contains many potassium and sodium channels, and in the resting 2

26 3 Dendrites Axon hillock Nucleus within the cell body Axon Synapses Figure 3 : Structure of a typical biological neuron state the potential of the intercellular fluid is around 80 mv with respect to the ground potential of the extracellular liquid. The spikes from other neurons release some charge into the neuron through the synapses and increases the membrane potential. Experiments show if the membrane potential can be increased above 40mV, the neuron can generate spikes, otherwise the potential slowly decays back to its resting state. This phenomenon is caused by dependence of the opening and close of the potassium and sodium channels on the the membrane potential. When the potential is increasing and above 40 mv, the rapid opening of the sodium channels brings positive sodium ions inside the neuron and further increases the potential. The positive feedback loop quickly raises the potential to +40 mv. Meanwhile, the sodium channel is inactivated slowly, and most importantly a delayed opening of potassium channels causes the positive potassium charge flow out of the neuron, which results in the quick decrease of the potential back to the resting state. The total effects of the sodium and potassium channels cause the active potential. After an action potential there is a refractory period during which no spikes can be generated. This is due to the fact that the sodium channels are inactivated and the potassium channels are open for some extra time after spiking.

27 4 x(t) V mem Spike C V ref Figure 3 2: Structure of the IF neuron 3.3 Integrate-and-fire Neuron Models Although the Hodgkin-Huxley model successfully describes the spike generation of the biological neuron, it is too complicated for a compact circuit implementation. Spiking neuron models based on the integrate-and-fire mechanism also capture the essentials of the spike generation, and are easily implemented in silicon Integrate-and-fire Neuron Model The structure of the integrate-and-fire (IF) neuron model is shown in Figure 3 2. The effect of the charge released by other neurons spikes is modelled by a current source x(t). The membrane is modelled by a passive capacitor C. The current is integrated over the capacitor C and increases the capacitor voltage V mem. Once V mem is above the threshold voltage V ref of the comparator, a spike is generated and V mem is then reset to ground and another integration period begins. The shapes of V mem and the spike are shown in Figure 3 3 where t ib and t ie are the timings for the falling and rising edges of the spike. Obviously the signal information is encoded in the integration period. Equations 3., 3.2 and 3.3

28 5 Spike tib tie t V mem V ref tib tie t Figure 3 3: Shapes of the V mem and the spike of the IF neuron describe this encoding process. C dv mem dt = x(t) (3.) V mem (t ib ) = 0 (3.2) V mem (t ie ) = V ref (3.3) We can also use one equation to describe this encoding process. tie t ib x(t)dt = CV ref = θ, i (3.4) If we assume the spike width is infinitely small, we obtain spike timings t i = t ib and t i+ = t (i+)b = t ie, and Equation 3.4 simplifies to ti+ t i x(t)dt = θ, i (3.5)

29 6 If we also define the integral of the signal as f(t) = t t 0 x(s)ds where t 0 is the beginning of the first integration period, Equation 3.5 is equivalent to f(t i ) = iθ, i (3.6) This shows us another view of the encoding process which records the time whenever the integral of the signal crosses the level of integer number of θ. This interpretation places the integrate-and-fire neuron in the class of TB-ADCs defined in Chapter Leaky Integrate-and-fire Neuron with Refractory Period Model As mentioned in Section 3.2 the spike generation of biological neurons shows some features of leaky integration and the refractory period. When the IF neuron in Section 3.3. is implemented in circuitry, the finite output impedance of the current source and other parasitic resistances in parallel with the capacitor lead to a leaky integration, and meanwhile the finite slope of the spike falling edge causes some refractory period. To model the leaky conductance a resistor R is introduced in parallel with the capacitor C. The spike generation is similar to the IF neuron case, and the shapes of V mem and the spike are shown in Figure 3 4 where T r represents the refractory period. Similarly this encoding process can be described by Equations 3.7, 3.8 and 3.9. C dv mem dt + V mem R = x(t) (3.7) V mem (t ib + T r ) = 0 (3.8) V mem (t ie ) = V ref (3.9) We can also use one equation to describe this encoding process. tie t ib +T r x(t)e tie t RC dt = CVref = θ, i (3.0)

30 7 Spike tib tie t V mem V ref tib tib T r tie t Figure 3 4: Shapes of the V mem and the spike waveform of the LIF neuron We can notice that Equation 3.0 is consistent with Equation 3.4 when the leaky resistance R takes on an infinite value Integrate-and-fire Neuron with Threshold Adaptation Biological neurons also exhibit some adaptive properties when generating spike trains [9, 3, 4]. When a strong stimulus is applied to the neuron, the neuron firing rate will initially be high and then adapt to a lower value. The adaptive mechanism may serve to save power and improve dynamic range. These adaptive properties can be utilized in low power ADC applications. Threshold adaptation is one way to introduce adaptive properties into the neuron model [4]. The threshold decays exponentially and is incremented after an action potential by an amount determined by previous firing patterns. The Equations below describe the encoding processing. C dv mem = x(t) ifv mem (t) < S(t) (3.) dt ds dt = S r S ifv mem (t) < S(t) (3.2) τ s V mem (t + ib ) = 0 ifv mem(t ib ) = S(t ib ) (3.3)

31 8 Spike tib tie t S(t) 0 V mem (t) tib tie t Figure 3 5: Shapes of the V mem, S(t) and the spike waveform of the IF neuron with threshold adaptation S(t + ib ) = S 0 + αs(t ib ) ifv mem (t ib ) = S(t ib ) (3.4) where τ s is the time constant of the threshold, S r is the steady state value of the threshold in the absence of firing and α is a positive number less than. Figure 3 5 shows the waveforms of the capacitor voltage V mem, the threshold S(t), and the spike train for the neuron with threshold adaptation. We can see that if S r = S 0 = V ref and α = 0, the adaptive neuron reduces the ideal IF neuron with constant threshold. 3.4 Summary In this chapter we introduced a typical biological neuron and some integrateand-fire neuron models. These neuron models represent information in spike timings and therefore can serve as the encoder in the TB-ADC architecture. In the following chapter we will show the DSP algorithm which can be used to reconstruct signals from these spike timings.

32 CHAPTER 4 RECONSTRUCTION FROM SPIKING NEURON MODELS 4. Introduction As mentioned in Chapter 2 the performance of the TB-ADC also depends on the reconstruction algorithm. Poor reconstruction methods can degrade the ADC performance dramatically even when the signal is accurately encoded by the encoder. This chapter describes the method to perfectly reconstruct the signal from the spiking neuron. 4.2 Direct Low-pass Filtering Reconstruction Method The effort to reconstruct signals from the neuron spike train can be recalled back to as early as 968, when Bayly gave a spectral analysis of the spike train from IF neuron with single sinusoidal input [5]. His results show that in some cases the signal can be reconstructed with some tolerable distortion from the spike train using direct low-pass filtering. We assume the threshold voltage is V ref = θ C and the spike train is modelled as an unit-area impulse train with t i as the firing times, Equations 3., 3.2 and 3.3 then can be simplified as θ = ti+ t i x(t)dt (4.) f 0 m 0J0( f m f ) m 2 m f0j( f m )( f f m 0 ) f J 2m ) 0 0( f m f m 0 f m f0 2f0 f Figure 4 : Spectrum of the spike train from the IF neuron 9

33 20 Considering the simple case where the input to the IF neuron is a sinusoidal signal x(t) = m 0 + m cos(2πf m t), and one of the spikes happens at t = 0, the spectral description of the spike train from Bayly s analysis is given as: p(t) = f 0 + m θ cos(2πf mt) + 2f 0 J n ( km )( + nf m ) cos(2π(kf 0 + nf m )t) (4.2) θf m kf 0 k= n= where f 0 = m 0 /θ is the fundamental frequency which is equivalent to the average spike firing rate, and J n is a Bessel function of the first kind of order n. The first two terms in Equation 4.2 are directly from the input signal x(t) scaled by θ, the other terms kf 0 + nf m are the frequency components cross modulated between f 0 and f m. The spectrum can be seen more clearly in Figure 4. For the spectrum of the spike train generated from multi-tone input signal, the result is similar to Equation 4.2 except more complicated cross modulated frequency components [6]. The direct low-pass filtering reconstruction method is to pass the spike train through a low-pass filter with cutoff frequency equal to the maximum signal frequency to remove cross modulated components. It can be clearly seen from Equation 4.2 or Figure 4 that no matter how large the average firing rate f 0 is, there are always some cross modulated components kf 0 + nf m falling into the signal band [ f m, f m ] which can not be filtered out even using ideal low-pass filter. This means perfect signal reconstruction can not be achieved using this method. In practical signal reconstruction, the cross modulated components in the signal band usually have non-negligible magnitude, and thus the reconstruction performance of direct low-pass filtering is not acceptable for most applications. 4.3 WLPK Reconstruction Method The signal reconstruction from TB-ADC is a non-uniform sampling problem. Developments in the non-uniform sampling theory have shown that perfect signal reconstruction can be achieved in some cases [7, 8]. We have developed the

34 2 weighted low-pass kernel method (WLPK) to realize perfect signal reconstruction [9]. The method is described below: From non-uniform sampling theory we can derive the claim: any bandlimited signal can be expressed as a low-pass filtered version of an appropriately weighted sum of delayed impulse functions [7], [8]. Assuming that x(t) is bandlimited to [ Ω s, Ω s ], and s j s are the timings of the impulse train and the maximum adjacent sample timing distance is less than the Nyquist period T = π/ω s, then we have x(t) = h(t) j w j δ(t s j ) = j w j h(t s j ) (4.3) where w j are scalar weights, h(t) is the impulse response of the low-pass filter and denotes the convolution operator. The impulse response of the ideal low-pass filter is given by the Sinc function: h(t) = sin(ω s t)/(ω s t) (4.4) Now the signal reconstruction problem is simplified as how to calculate the appropriate weights. If s j = jt is a uniform sampling sequence, standard sampling theory can be used to show that the impulse weight reduces to the sampled value of signal x(t) at the timing s j, i.e., w j = x(s j ). But generally the weights need to be calculated using the encoding information Reconstruction from the IF neuron We first consider the reconstruction from the integrate-and-fire neuron without any refractory period. The firing times must satisfy: tie x(t)dt = θ i, i (4.5) t ib where θ i = θ for constant threshold, and t ib and t ie are the falling edge and the rising edge of the spike. Let us assume that x(t) is bandlimited to [ Ω s, Ω s ], and

35 22 t ib, i Z and t ie, i Z are timing sequences with maximum adjacent interval (t (i+)b t ib ) < T, (t (i+)e t ie ) < T, where the Nyquist period T = π/ω s. We can create an impulse train with timing s j = (t jb + t je )/2 with maximum adjacent timing interval which is less than the Nyquist period T, and then x(t) can be expressed as in Equation 4.3. Substituting Equation 4.3 into Equation 4.5, we obtain θ i = tie t i b x(t)dt = tie t ib = j = j w j h(t s j )dt j tie w j h(t s j )dt t ib w j c ij (4.6) where c ij are constants that can be numerically computed with: c ij = tie t ib h(t s j )dt (4.7) The resulting set of linear equations is given by C W = θ in matrix form where W is a column vector with w j as the jth row element, C is a square matrix with c ij as the ith row jth column element, and θ is a column vector with θ i as the ith row element. Unfortunately, C is usually ill-conditioned necessitating the use of a SVD-based pseudo-inverse conditioning technique [20] or other matrix regulation techniques to calculate the weights. The computation cost is estimated assuming the use of the Gaussian elimination method as discussed in later chapters [2, 22]. Thus we can obtain the weight vector W: W = C + θ (4.8) Now we can substitute the weight vector to Equation 4.3 to numerically calculate the reconstructed signal x(t) to within machine precision. In order to facilitate later discussions we may further simplify the expression of the reconstructed signal

36 23 2 (a) 0 x 0-6 A (b) 2 Original Reconstructed 0 2 x 0- A (c) Time (S) x 0-3 Figure 4 2: Reconstruction results from the IF neuron. (a) The spike train. (b) The original and reconstructed signals. (c) The error between the original and the reconstructed signals x(t): x(t) = [h(t s j )][c + ji ][θ i] = [ j h(t s j )c + ji ][θ i] = [h i (t)][θ i ] = i h i (t)θ i (4.9) where c + ji is the jth row ith column element of the inverse matrix C+, [ ] denotes a matrix with element, and h i (t) = j h(t s j )c + ji (4.0) Figure 4 2 shows a reconstructed signal using the WLPK method for an integrateand-fire neuron. The input signal is a Gaussian random noise signal bandlimited to [ 3000π, 3000π] rad/s, and the corresponding Nyquist period T = /3 ms. The DC current is 800 na, the capacitance C = 8 pf, the reference voltage V ref = 3 V, the

37 24 spike width is 6.6 us. Since the maximum adjacent spike interval (0.5 ms) is less than T, this method can be used to reconstruct the input signal. The simulation results show the effective signal to noise ratio (SNR) of the reconstruction is 07.6 db. SNR is computed as the power of the input signal divided by the power of the error between the original and the reconstructed signals Reconstruction from LIF neuron with refractory period Equations 3.7, 3.8 and 3.9 describe the encoding operation of the leaky integrate-and-fire neuron with the current input. They are used to generate a linear system of equation in a similar fashion to the ideal integrate-and-fire neuron discussed in Section 4.3., except the coefficient matrix C element c ij = tie t ib +T r h(t s j ) e (t t ie)/(rc) dt (4.) which is the leaky integration of h(t s j ) over the time period [t ib + T r, t ie ]. Equation 4. is consistent with Equation 4.7 when the leaky resistance R takes on an infinite value. We can use Equation 4.8 to calculate the weights for each impulse at s j, then use Equation 4.3 to reconstruct the signal x(t) Reconstruction from the IF neuron with threshold adaptation To reconstruct the signal from the IF neuron with threshold adaptation we have to know the integration of the input signal over the ith integration period, i.e., the threshold at the time t ie. Assuming the threshold does not change from t (i )e to t ib, from Equations 3.2, 3.4 we can obtain the threshold value at t ie : θ i = S(t ie ) = (S 0 + αs(t (i )e ) S r )e t ib t ie τs + S r = S(t (i )e )αe t ib t ie τs + S r + (S 0 S r )e t ib t ie τs (4.2) which can be determined if we know the previous threshold value at t (i )e. Therefore if the initial threshold value is given, we can calculate the exact following threshold values using Equation 4.2, and then use Equations 4.7, 4.8, and 4.3 to

38 25 reconstruct the signal. If the initial threshold value is not given, some estimation error will be introduced into the reconstruction. However, it is believed that the estimation error decays with time. This is due to the fact that the coefficient αe t ib t ie τs in Equation 4.2 is a number less than. 4.4 Discussion of Other Reconstruction Methods Previous simulation results show that the WLPK method achieves much better performance than the direct low pass filtering method. Besides these two methods, there are also other methods which can be used for the signal reconstruction from the spiking neuron. Noguchi et al. found one method based on the integral mechanism of the neuron encoding and claimed the reconstruction performance is better than simple low pass filtering [23, 24]. Their method uses B-spline interpolation to approximate the integration function of the original signal x(t) and then differentiate it to obtain the original input x(t). The reconstructed signal is not perfect since the approximation error can not be avoided. Lazar et al. realized an iterative algorithm method based on nonuniform sampling theory to theoretically achieve perfect signal reconstruction from the asynchronous delta-sigma modulation [7]. Since the IF neuron has a similar integral mechanism of the asynchronous sigma-delta converters, this method is also applicable to the IF neuron. The problem with Noguchi s and Lazar s methods is that they are not easy to be applied to more complicated model such as the leaky IF with refractory period or threshold adaptation, see Gerstner [3] for more neuron models. This seriously limits their application since practical IF neuron circuit always has some leaky and refractory period features which need to be considered in the reconstruction for better performance. The WLPK method we discussed is better in that it can be applied to general time-based ADC architecture.

39 CHAPTER 5 PRACTICAL ISSUES RELATED TO SPIKING NEURON TB-ADC IMPLEMENTATION 5. Introduction In this chapter, we first introduce a spiking neuron TB-ADC implementation using the spiking neuron model discussed in Chapter 3, and the DSP reconstruction algorithm block discussed in Chapter 4. Since the actual building components used are not perfect, we then investigate effects of some nonidealities on the performance of the analog to digital conversion. For the spiking neuron encoding component we consider the frequency aliasing of the input signal, leaky integration of the integrator, thermal noise of the spiking neuron, and the signal dependent threshold of the comparator. For the DSP reconstruction component, we consider the timing jitter of the time quantizer, the kernel selection, and the windowing of the DSP algorithm. 5.2 Implementation of Spiking Neuron TB-ADC Figure 5 shows an implementation of the spiking neuron TB-ADC. The detailed circuit implementation will be discussed in Chapter 6. The components inside the dashed box form an integrate-and-fire neuron encoder which was previously discussed in Chapter 3. Compared to the previous structure in Figure 3 2, a transconductor G m block is used to convert a voltage signal V (t) to a current signal x(t) = G m V (t) since the input signal for many analog to digital applications is in voltage form. If the input is a current signal, the G m block is obviously not needed and the ADC design is simplified. The neuron encodes the analog signal waveform in the transition timings of the spiking signal. The time quantizer quantizes the transition timings of the spiking signal with a clock period T c. The 26