Dual, 200mA, Low-I Q Low-Dropout Regulator for Portable Devices

Transcription

1 1 TLV71 TLV mm x 1.5mm SON-6 (TOP VIEW) TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 Dual, 2mA, Low-I Q Low-Dropout Regulator for Portable Devices 1FEATURES DESCRIPTION 2 Very Low Dropout: The TLV71 and TLV711 series of dual, low-dropout 15mV at I OUT = 2mA and V OUT = 2.8V (LDO) linear regulators are low quiescent current 75mV at I devices with excellent line and load transient OUT = 1mA and V OUT = 2.8V performance. These LDOs are designed for 4mV at I OUT = 5mA and V OUT = 2.8V power-sensitive applications. These devices provide 2% Accuracy Over Temperature a typical accuracy of 2% over temperature. Low I Q of 35mA per Regulator The TLV711 series provides an active pulldown Multiple Fixed Output Voltage Combinations circuit to quickly discharge the outputs. Possible from 1.2V to 4.8V In addition, the TLV711-D series of devices have High PSRR: 7dB at 1kHz pull-down resistors at the EN pins. This design helps Stable with Effective Capacitance of.1mf (1) in disabling the device when the signal-driving EN pins are in a weak, indeterminate state (for example, Over-Current and Thermal Protection the GPIO of a processor that might be three-stated Dedicated V REF for Each Output Minimizes during startup). The pull-down resistor pulls the Crosstalk voltage to the EN pins down to V, thus disabling the Available in 1.5mm 1.5mm SON-6 Package device. (1) See the Input and Output Capacitor Requirements in the Application Information section The TLV71 and TLV711 series are available in a APPLICATIONS Wireless Handsets, Smart Phones, PDAs MP3 Players and Other Handheld Products 1.5mm x 1.5mm SON-6 package, and are ideal for handheld applications. EN1 1 6 OUT1 IN 2 5 OUT2 EN2 3 4 GND Typical Application Circuit V IN IN OUT1 V OUT1 C IN ON OFF ON OFF EN1 EN2 GND OUT2 C OUT2 V OUT2 1 F Ceramic COUT1 1 F Ceramic Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 21, Texas Instruments Incorporated

2 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT V OUT (2) TLV71xxyyqwwwz TLV711xxyyqwwwz XX is nominal output voltage of channel 1 (for example 18 = 1.8V). YY is nominal output voltage of channel 2 (for example 28 = 2.8V). Q is optional. Use "U" for devices with EN pin pull-up resistor, and "D" for devices with EN pin pull-down resistor. WWW is package designator. Z is package quantity. Use "R" for reel (3 pieces), and "T" for tape (25 pieces). (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on. (2) Output voltages from 1.2V to 4.8V in 5mV increments are available through the use of innovative factory OTP programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At T J = 4 C to +125 C (unless otherwise noted). VALUE MIN MAX UNIT IN V Voltage (2) EN.3 V IN +.3 V OUT V Current OUT Internally limited A Output short-circuit duration Indefinite s Temperature Operating junction, T J C Storage, T stg C Human body model (HBM) QSS 9-15 (JESD22-A114A) 2 kv Electrostatic Discharge Rating Charged device model (CDM) QSS (JESD22-C11B.1) 5 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages with respect to ground. THERMAL INFORMATION (1) TLV71, TLV711 THERMAL METRIC (2) DSE UNITS 6 PINS y JT Junction-to-top characterization parameter 6 C/W (1) See the Power Dissipation section for more details. (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

3 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 ELECTRICAL CHARACTERISTICS At T J = +25 C, V IN = V OUT(TYP) +.5V or 2.V (whichever is greater), I OUT = 1mA, V EN1 = V EN2 =.9V, and C OUT1 = C OUT2 = 1mF, unless otherwise noted. TLV71, TLV711 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IN Input voltage range V V O Output voltage range V V OUT DC output accuracy 4 C T J +125 C 2 +2 % ΔV O /ΔV IN Line regulation V OUT(NOM) +.5V V IN 5.5V 1 5 mv ΔV O /ΔI OUT Load regulation ma I OUT 2mA 5 15 mv V DO Dropout voltage V IN =.98V V OUT(NOM), I OUT = 2mA, 2V V OUT < 2.4V V IN =.98V V OUT(NOM), I OUT = 2mA, 2.4V V OUT < 2.8V V IN =.98V V OUT(NOM), I OUT = 2mA, 2.8V V OUT < 3.3V V IN =.98V V OUT(NOM), I OUT = 2mA, 3.3V V OUT 4.8V mv mv mv 14 2 mv I CL Output current limit V OUT =.9V V OUT(NOM) ma V EN1 = high, V EN2 = low, I OUT1 = ma 35 ma I Q Quiescent current V EN1 = low, V EN2 = high, I OUT2 = ma 35 ma V EN1 = high, V EN2 = high, I OUT = ma 7 11 µa I GND Ground pin current I OUT1 = I OUT2 = 2mA 36 µa I SHUTDOWN Shutdown current V EN1,2.4V, 2.V V IN 4.5V ma f = 1Hz 8 db f = 1Hz 75 db PSRR Power-supply rejection ratio V OUT = 1.8V f = 1kHz 7 db f = 1kHz 7 db f = 1kHz 5 db V N Output noise voltage BW = 1Hz to 1kHz, V OUT = 1.8V 48 mv RMS t STR Startup time (1) C OUT = 1.mF, I OUT = 2mA 1 ms V HI Enable high (enabled).9 V IN V V LO Enable low (shutdown).4 V I EN Enable pin current, enabled TLV71, TLV711.4 ma TLV71-D, TLV711-D 6 ma UVLO Undervoltage lockout V IN rising 1.9 V T J Operating junction temperature C T SD Thermal shutdown temperature (1) Startup time = time from EN assertion to.98 x V OUT(NOM). Shutdown, temperature increasing +165 C Reset, temperature decreasing +145 C Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 3

4 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 FUNCTIONAL BLOCK DIAGRAM TLV711 and TLV711-D only 12 Bandgap TLV71-D and TLV711-D only UVLO Thermal Shutdown Current Limit EN1 EN2 IN 15k Enable and Power Control Logic Thermal Shutdown UVLO Current Limit OUT1 OUT2 TLV71-D and TLV711-D only Bandgap 12 TLV711 and TLV711-D only GND 4 Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

5 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 PIN CONFIGURATION DSE PACKAGE 1.5mm x 1.5mm SON-6 (TOP VIEW) EN1 1 6 OUT1 IN 2 5 OUT2 EN2 3 4 GND PIN DESCRIPTIONS NAME PIN NO. DESCRIPTION EN1 1 IN 2 EN2 3 GND 4 Ground pin. Enable pin for regulator 1. Driving EN1 over.9v turns on regulator 1. Driving EN below.4v puts regulator 1 into shutdown mode. Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Enable pin for regulator 2. Driving EN2 over.9v turns on regulator 2. Driving EN2 below.4v puts regulator2 into shutdown mode. Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure OUT2 5 stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure OUT1 6 stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 5

6 TLV71 Series SBVS142A JULY 21 REVISED AUGUST I OUT1 = 1mA I OUT2 = 1mA TYPICAL CHARACTERISTICS Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. LINE REGULATION: V OUT1 (TLV711828) LINE REGULATION: V OUT2 (TLV711828) I OUT1 = 1mA I OUT2 = 1mA Figure 1. Figure LINE REGULATION: V OUT1 (TLV711828) I OUT1 = 2mA I OUT2 = ma LINE REGULATION: V OUT2 (TLV711828) I OUT1 = ma I OUT2 = 2mA Figure 3. Figure LINE REGULATION: V OUT1 (TLV713333) I OUT1 = 1mA I OUT2 = 1mA LINE REGULATION: V OUT2 (TLV713333) I OUT1 = 1mA I OUT2 = 1mA Figure 5. Figure 6. 6 Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

7 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C LINE REGULATION: V OUT1 (TLV713333) I OUT1 = 2mA I OUT2 = ma LINE REGULATION: V OUT2 (TLV713333) I OUT1 = ma I OUT2 = 2mA Figure 7. Figure LINE REGULATION: V OUT1 (TLV ) I OUT1 = 1mA I OUT2 = 1mA LINE REGULATION: V OUT2 (TLV ) I OUT1 = 1mA I OUT2 = 1mA Figure 9. Figure LINE REGULATION: V OUT1 (TLV ) I OUT1 = 2mA I OUT2 = ma LINE REGULATION: V OUT2 (TLV ) I OUT1 = ma Figure 11. Figure 12. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 7

8 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C LOAD REGULATION: V OUT1 (TLV711828) V = 3.3V IN I OUT (ma) LOAD REGULATION: V OUT2 (TLV711828) V = 3.3V IN I OUT (ma) Figure 13. Figure LOAD REGULATION: V OUT1 (TLV713333) V = 3.8V IN I OUT (ma) LOAD REGULATION: V OUT2 (TLV713333) V = 3.8V IN I OUT (ma) Figure 15. Figure LOAD REGULATION: V OUT1 (TLV ) V = 3.V IN I OUT (ma) LOAD REGULATION: V OUT2 (TLV ) V = 3.V IN I OUT (ma) Figure 17. Figure Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

9 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. 7 6 DROPOUT VOLTAGE vs INPUT VOLTAGE V OUT1 = V OUT2 = 4.8V I OUT = 5mA 12 1 DROPOUT VOLTAGE vs INPUT VOLTAGE V OUT1 = V OUT2 = 4.8V I OUT = 1mA V DO (mv) V DO (mv) Figure 19. Figure 2. V DO (mv) DROPOUT VOLTAGE vs INPUT VOLTAGE V OUT1 = V OUT2 = 4.8V I OUT = 15mA V DO (mv) DROPOUT VOLTAGE vs INPUT VOLTAGE V OUT1 = V OUT2 = 4.8V I OUT = 2mA Figure 21. Figure 22. V DO (mv) DROPOUT VOLTAGE vs OUTPUT CURRENT: V OUT2 (TLV711828) I OUT (ma) V DO (mv) DROPOUT VOLTAGE vs OUTPUT CURRENT: V OUT1 /V OUT2 (TLV713333) I OUT (ma) Figure 23. Figure 24. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 9

10 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. V DO (mv) DROPOUT VOLTAGE vs OUTPUT CURRENT: V OUT2 (TLV ) I OUT (ma) OUTPUT VOLTAGE vs TEMPERATURE: V OUT1 (TLV711828) V = 3.3V IN 1mA 15mA 2mA Junction Temperature ( C) Figure 25. Figure OUTPUT VOLTAGE vs TEMPERATURE: V OUT2 (TLV711828) V = 3.3V IN 1mA 15mA 2mA Junction Temperature ( C) OUTPUT VOLTAGE vs TEMPERATURE: V OUT1 (TLV713333) V = 3.8V IN 1mA 15mA 2mA Junction Temperature ( C) Figure 27. Figure OUTPUT VOLTAGE vs TEMPERATURE: V OUT2 (TLV713333) V = 3.8V IN 1mA 15mA 2mA Junction Temperature ( C) OUTPUT VOLTAGE vs TEMPERATURE: V OUT1 (TLV ) V = 3.V IN 1mA 15mA 2mA Junction Temperature ( C) Figure 29. Figure Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

11 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C OUTPUT VOLTAGE vs TEMPERATURE: V OUT2 (TLV ) V = 3.V IN 1mA 15mA 2mA Junction Temperature ( C) 125 I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q1 (TLV711828) V = 3.3V IN Figure 31. Figure 32. I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q2 (TLV711828) I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q1 (TLV713333) Figure 33. Figure 34. I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q2 (TLV713333) I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q1 (TLV ) Figure 35. Figure 36. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 11

12 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. I GND ( A) GROUND PIN CURRENT vs INPUT VOLTAGE: I Q2 (TLV ) I GND ( A) GROUND PIN CURRENT vs LOAD: I Q1 (TLV711828) V = 3.3V IN I OUT (ma) Figure 37. Figure 38. GROUND PIN CURRENT vs LOAD: I Q2 (TLV713333) GROUND PIN CURRENT vs LOAD: I Q1 (TLV ) 35 3 V = 3.8V IN 35 3 V = 3.V IN I GND ( A) 2 15 I GND ( A) I OUT (ma) I OUT (ma) Figure 39. Figure 4. SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV711828) SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV713333) I SHDN ( A) I SHDN ( A) Figure 41. Figure Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

13 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. I SHDN ( A) SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV ) I LIM (ma) CURRENT LIMIT vs INPUT VOLTAGE: I CL1 (TLV711828) Figure 43. Figure I LIM (ma) CURRENT LIMIT vs INPUT VOLTAGE: I CL2 (TLV711828) I LIM (ma) CURRENT LIMIT vs INPUT VOLTAGE: I CL1 (TLV713333) Figure 45. Figure I LIM (ma) CURRENT LIMIT vs INPUT VOLTAGE: I CL2 (TLV713333) I LIM (ma) CURRENT LIMIT vs INPUT VOLTAGE: I CL1 (TLV ) Figure 47. Figure Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 13

14 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. CURRENT LIMIT vs INPUT VOLTAGE: I CL2 PSRR (db) PSRR (db) I OUT2 = 3mA I OUT2 = 15mA I LIM (ma) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV711828) 1 1 1k 1k 1k 1M 1M Frequency (Hz) I OUT2 = 3mA I OUT2 = 15mA Figure 49. I OUT1 = 3mA V IN = 3.3V V OUT = 2.8V I OUT1 = 3mA V IN = 3.V V OUT = 2.5V 1 1 1k 1k 1k 1M 1M Frequency (Hz) (TLV ) PSRR (db) Output Spectral Noise Density ( V/ Hz) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV713333) I OUT2 = 3mA I OUT1 = 3mA V IN = 3.8V V OUT = 3.3V I OUT2 = 15mA 1 1 1k 1k 1k 1M 1M Frequency (Hz) Figure 5. Figure 51. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV ) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV711828) V IN = 3.3V V OUT2 = 2.8V I OUT2 = 3mA 1 1 1k 1k 1k 1M 1M Frequency (Hz) Figure 52. Figure Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

15 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. Output Spectral Noise Density ( V/ Hz ) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV713333) V IN = 3.8V V OUT2 = 3.3V I OUT2 = 3mA 1 1 1k 1k 1k 1M 1M Frequency (Hz) Output Spectral Noise Density ( V/ Hz) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV ) V IN = 3.V V OUT1 = 1.5V I OUT1 = 3mA 1 1 1k 1k 1k 1M 1M Frequency (Hz) Figure 54. Figure 55. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE V OUT1 = 1.2V, V OUT2 = 1.2V V OUT1 = 1.2V, V OUT2 = 1.2V 1V/div 3.V Slew Rate = 1V/ s I OUT = 3mA 5.5V Slew Rate = 1V/ s I OUT = 3mA 2.V V IN 2V/div 2.V V IN 5mV/div V OUT1 5mV/div V OUT1 5mV/div V OUT2 5mV/div V OUT2 Time (2 s/div) Time (2 s/div) Figure 56. Figure 57. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE V OUT1 = 1.8V, V OUT2 = 2.8V V OUT1 = 1.8V, V OUT2 = 2.8V 4.3V Slew Rate = 1V/ s I OUT = 3mA 5.5V Slew Rate = 1V/ s I OUT = 3mA 1V/div 3.3V V IN 1V/div 3.3V V IN 5mV/div V OUT1 5mV/div V OUT1 5mV/div V OUT2 5mV/div V OUT2 Time (2 s/div) Time (2 s/div) Figure 58. Figure 59. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 15

16 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. LINE TRANSIENT RESPONSE V OUT1 = 4.8V, V OUT2 = 4.8V 5.5V Slew Rate = 1V/ s I OUT = 3mA 1V/div 5.3V V IN 5mV/div V OUT1 5mV/div V OUT2 Time (2 s/div) Figure 6. LOAD TRANSIENT RESPONSE AND CROSSTALK LOAD TRANSIENT RESPONSE AND CROSSTALK V OUT1 = 1.2V, V OUT2 = 1.2V V OUT1 = 1.2V, V OUT2 = 1.2V 2mA Slew Rate = 1V/ s V IN = 2.V 2mA Slew Rate = 1V/ s V IN = 2.V 1mA/div ma I OUT1 1mA/div 5mA I OUT1 5mV/div V OUT1 5mV/div V OUT1 1mV/div V OUT2 1mV/div V OUT2 Time (5 s/div) 2mA Slew Rate = 1V/ s V IN = 3.3V 1mA/div Time (5 s/div) Figure 61. Figure 62. LOAD TRANSIENT RESPONSE AND CROSSTALK LOAD TRANSIENT RESPONSE AND CROSSTALK V OUT1 = 1.8V, V OUT2 = 2.8V V OUT1 = 1.8V, V OUT2 = 2.8V 2mA Slew Rate = 1V/ s V IN = 3.3V 5mA I OUT2 1mA/div ma I OUT2 5mV/div V OUT1 2mV/div V OUT2 V OUT2 5mV/div 5mV/div V OUT1 Time (5 s/div) Time (5 s/div) Figure 63. Figure Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

17 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of T J = 4 C to +125 C, V EN1 = V EN2 = V IN, C IN = 1mF, C OUT1 = 1mF, and C OUT2 = 1mF, unless otherwise noted. Typical values are at T J = +25 C. LOAD TRANSIENT RESPONSE AND CROSSTALK LOAD TRANSIENT RESPONSE AND CROSSTALK V OUT1 = 4.8V, V OUT2 = 4.8V V OUT1 = 4.8V, V OUT2 = 4.8V 2mA Slew Rate = 1V/ s V IN = 5.3V 2mA Slew Rate = 1V/ s V IN = 5.3V 1mA/div ma I OUT1 5mA/div 5mA I OUT1 5mV/div V OUT1 5mV/div V OUT1 5mV/div V OUT2 5mV/div V OUT2 Time (5 s/div) Time (5 s/div) Figure 65. Figure 66. V IN RAMP UP, RAMP DOWN RESPONSE V IN RAMP UP, RAMP DOWN RESPONSE V OUT1 = 1.2V, V OUT2 = 1.2V V OUT1 = 1.8V, V OUT2 = 2.8V VIN/ VEN I OUT = 3mA VIN/ VEN I OUT = 3mA 1V/div 1V/div V OUT2 V OUT1/VOUT2 V OUT1 Time (2ms/div) VIN/ VEN I OUT = 3mA Time (2ms/div) Figure 67. Figure 68. V IN RAMP UP, RAMP DOWN RESPONSE V OUT1 = 4.8V, V OUT2 = 4.8V 1V/div V OUT1/VOUT2 Time (2ms/div) Figure 69. Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 17

18 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 APPLICATION INFORMATION The TLV71 and TLV711 series of devices belong to a new family of next generation, value LDO BOARD LAYOUT RECOMMENDATIONS TO regulators. These devices consume low quiescent IMPROVE PSRR AND NOISE PERFORMANCE current and deliver excellent line and load transient Input and output capacitors should be placed as performance. These features, combined with low close to the device pins as possible. To improve ac noise, very good PSRR with little (V IN to V OUT ) performance such as PSRR, output noise, and headroom, make these devices ideal for RF portable transient response, it is recommended that the board applications. This family of LDO regulators offers be designed with separate ground planes for V IN and current limit and thermal protection, and is specified V OUT, with the ground plane connected only at the from 4 C to +125 C. GND pin of the device. In addition, the ground connection for the output capacitor should be INPUT AND OUTPUT CAPACITOR connected directly to the GND pin of the device. High REQUIREMENTS ESR capacitors may degrade PSRR. 1.mF X5R- and X7R-type ceramic capacitors are recommended because they have minimal variation INTERNAL CURRENT LIMIT in value and equivalent series resistance (ESR) over The TLV71 and TLV711 internal current limits help temperature. protect the regulator during fault conditions. During However, the TLV71 and TLV711 are designed to current limit, the output sources a fixed amount of be stable with an effective capacitance of.1mf or current that is largely independent of output voltage. larger at the output. Thus, the device would also be In such a case, the output voltage is not regulated, stable with capacitors of other dielectrics, as long as and is V OUT = I LIMIT R LOAD. the effective capacitance under operating bias The PMOS pass transistor dissipates (V IN V OUT ) voltage and temperature is greater than.1mf. This I LIMIT until thermal shutdown is triggered and the effective capacitance refers to the capacitance that device is turned off. As the device cools down, it is the device sees under operating bias voltage and turned on by the internal thermal shutdown circuit. If temperature conditions (that is, the capacitance after the fault condition continues, the device cycles taking bias voltage and temperature derating into between current limit and thermal shutdown. See the consideration.) Thermal Information section for more details. The In addition to allowing the use of cost-effective PMOS pass element in the TLV71 and TLV711 has dielectrics, these devices also enable using smaller a built-in body diode that conducts current when the footprint capacitors that have a higher derating in voltage at OUT exceeds the voltage at IN. This size-constrained applications. current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of Note that using a.1mf rating capacitor at the output rated output current is recommended. of the LDO regulator does not ensure stability because the effective capacitance under operating SHUTDOWN conditions would be less than.1mf. The maximum ESR should be less than 2mΩ. The enable pin (EN) is active high. The device is enabled when EN pin goes above.9v. This Although an input capacitor is not required for relatively lower value of voltage needed to turn the stability, it is good analog design practice to connect LDO regulator on can be used to enable the device a.1mf to 1.mF low ESR capacitor across the IN with the GPIO of recent processors whose GPIO and GND pins of the regulator. This capacitor voltage is lower than traditional microcontrollers. counteracts reactive input sources and improves transient response, noise rejection, and ripple The device is turned off when the EN pin is held at rejection. A higher-value capacitor may be necessary less than.4v. When shutdown capability is not if large, fast-rise-time load transients are anticipated, required, the EN pin can connected to the IN pin. or if the device is not located near the power source. The TLV711 has internal pull-down circuitry that If source impedance is more than 2Ω, a.1mf input discharges output with a time constant of: capacitor may be necessary to ensure stability. = 12 R L 12 + R L C OUT Where: R L = load resistance C OUT = output capacitor (1) 18 Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

19 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 DROPOUT VOLTAGE use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least The TLV71 and TLV711 use a PMOS pass +35 C above the maximum expected ambient transistor to achieve low dropout. When (V IN V OUT ) condition of the particular application. This is less than the dropout voltage (V DO ), the PMOS configuration produces a worst-case junction pass device is in the linear region of operation and temperature of +125 C at the highest expected the input-to-output resistance is the R DS(ON) of the ambient temperature and worst-case load. PMOS pass element. V DO scales approximately with the output current because the PMOS device The internal protection circuitry of the TLV71 and behaves as a resistor in dropout. TLV711 has been designed to protect against overload conditions. It was not intended to replace As with any linear regulator, PSRR and transient proper heatsinking. Continuously running the response are degraded as (V IN V OUT ) approaches TLV71/ TLV711 into thermal shutdown degrades dropout. device reliability. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. The TLV71 and TLV711 each have a dedicated V REF. Consequently, crosstalk from one channel to the other as a result of transients is close to V. POWER DISSIPATION The ability to remove heat from a die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. UNDERVOLTAGE LOCKOUT (UVLO) Performance data for the TLV71 evaluation module (EVM) are shown in Table 1. The EVM is a 2-layer The TLV71 and TLV711 use an undervoltage board with 2 ounces of copper per side. The lockout circuit to keep the output shut off until the dimension and layout are shown in Figure 7 and internal circuitry is operating properly. Figure 71. Using heavier copper increases the effectiveness of removing heat from the device. The THERMAL INFORMATION addition of plated through-holes in the heat-dissipating layer also improves the heatsink Thermal protection disables the output when the effectiveness. Power dissipation depends on input junction temperature rises to approximately +165 C, voltage and load conditions. allowing the device to cool. When the junction temperature cools to approximately +145 C, the Power dissipation (P D ) is equal to the product of the output circuitry is again enabled. Depending on power output current and the voltage drop across the output dissipation, thermal resistance, and ambient pass element, as shown in Equation 2: temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of P D = (V IN V OUT ) I OUT PACKAGE MOUNTING (2) overheating. Solder pad footprint recommendations for the TLV71 Any tendency to activate the thermal protection circuit and TLV711 are available from the Texas Instruments indicates excessive power dissipation or an Web site at. The recommended land inadequate heatsink. For reliable operation, junction pattern for the DSE (SON-6) package is shown in temperature should be limited to +125 C maximum. Figure 72. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; Table 1. TLV71 EVM Dissipation Ratings PACKAGE R qja T A < +25 C T A = +7 C T A = +85 C DSE 17 C/W 585mW 32mW 235mW Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 19

20 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 33mm 27mm Figure 7. Top Layer 33mm 27mm Figure 71. Bottom Layer 2 Submit Documentation Feedback Copyright 21, Texas Instruments Incorporated

21 TLV71 Series SBVS142A JULY 21 REVISED AUGUST 21 Figure 72. Land Pattern Drawing for DSE (SON-6) Package Copyright 21, Texas Instruments Incorporated Submit Documentation Feedback 21

22 PACKAGE OPTION ADDENDUM 5-Oct-217 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan TLV711828DSER ACTIVE WSON DSE 6 3 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU Level-1-26C-UNLIM -4 to 125 QW Device Marking (4/5) Samples TLV711828DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 QW TLV713318DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UE TLV713318DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UE TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 BT TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 BT TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 TP TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 TP TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 WH TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 WH TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 YY TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 YY TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UT TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UT TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 YD TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 YD TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 BS Addendum-Page 1

23 PACKAGE OPTION ADDENDUM 5-Oct-217 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU Level-1-26C-UNLIM -4 to 125 BS Device Marking (4/5) Samples TLV711183DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 GB TLV711183DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 GB TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UQ TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UQ TLV711193DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 CV TLV711193DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 CV TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 TM TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 TM TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 SX TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 SX TLV DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 9M TLV DSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 9M TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 WV TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 WV TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UU TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 UU TLV711325DSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 BR Addendum-Page 2

24 PACKAGE OPTION ADDENDUM 5-Oct-217 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan TLV711325DSET ACTIVE WSON DSE 6 25 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU Level-1-26C-UNLIM -4 to 125 BR Device Marking (4/5) Samples TLV71133DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 WS TLV71133DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 WS TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 VW TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 VW TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 YE TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 YE TLV711333DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 WZ TLV711333DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU Level-1-26C-UNLIM -4 to 125 WZ TLV DDSER ACTIVE WSON DSE 6 3 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 RV TLV DDSET ACTIVE WSON DSE 6 25 Green (RoHS CU NIPDAU CU NIPDAUAG Level-1-26C-UNLIM -4 to 125 RV (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 1 RoHS substances, including the requirement that RoHS substance do not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS79B low halogen requirements of <=1ppm threshold. Antimony trioxide based flame retardants must also meet the <=1ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 3

25 PACKAGE OPTION ADDENDUM 5-Oct-217 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV71 : Automotive: TLV71-Q1 NOTE: Qualified Version Definitions: Automotive - Q1 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4

26 PACKAGE MATERIALS INFORMATION 17-Feb-218 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A B K P1 W Pin1 Quadrant TLV711828DSER WSON DSE Q2 TLV711828DSET WSON DSE Q2 TLV713318DSER WSON DSE Q2 TLV713318DSET WSON DSE Q2 TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 Pack Materials-Page 1

27 PACKAGE MATERIALS INFORMATION 17-Feb-218 Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A B K P1 W Pin1 Quadrant TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV711183DSER WSON DSE Q2 TLV711183DSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV711193DSER WSON DSE Q2 TLV711193DSET WSON DSE Q2 TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV DSER WSON DSE Q2 TLV DSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV711325DSER WSON DSE Q2 TLV711325DSET WSON DSE Q2 TLV71133DDSER WSON DSE Q2 TLV71133DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV DDSET WSON DSE Q2 TLV711333DDSER WSON DSE Q2 TLV711333DDSER WSON DSE Q2 TLV711333DDSET WSON DSE Q2 TLV711333DDSET WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSER WSON DSE Q2 TLV DDSET WSON DSE Q2 Pack Materials-Page 2

28 PACKAGE MATERIALS INFORMATION 17-Feb-218 Device Package Type Package Drawing Pins SPQ Reel Diameter Reel Width W1 A B K P1 W Pin1 Quadrant TLV DDSET WSON DSE Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length Width Height TLV711828DSER WSON DSE TLV711828DSET WSON DSE TLV713318DSER WSON DSE TLV713318DSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE Pack Materials-Page 3

29 PACKAGE MATERIALS INFORMATION 17-Feb-218 Device Package Type Package Drawing Pins SPQ Length Width Height TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV711183DSER WSON DSE TLV711183DSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE TLV711193DSER WSON DSE TLV711193DSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV DSER WSON DSE TLV DSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE TLV711325DSER WSON DSE TLV711325DSET WSON DSE TLV71133DDSER WSON DSE TLV71133DDSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE TLV DDSET WSON DSE TLV DDSET WSON DSE TLV711333DDSER WSON DSE TLV711333DDSER WSON DSE TLV711333DDSET WSON DSE TLV711333DDSET WSON DSE TLV DDSER WSON DSE TLV DDSER WSON DSE Pack Materials-Page 4

30 PACKAGE MATERIALS INFORMATION 17-Feb-218 Device Package Type Package Drawing Pins SPQ Length Width Height TLV DDSET WSON DSE TLV DDSET WSON DSE Pack Materials-Page 5

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