Comparison of High Power Non-Isolated Multilevel DC-DC Converters for Medium-Voltage Battery Storage Applications

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1 Comprison of High Power NonIsolted Multilevel DCDC Converters for MediumVoltge Bttery Storge Applictions M. Stojdinovic nd J. Biel Lbortory for High Power Electronic Systems ETH Zurich, Physikstrsse 3, CH89 Zurich, Switzerlnd Emil: Abstrct In this pper 4level neutrlpointclmped (4LNPC), 4level flyingcpcitor (4LFC) nd 4level neutrlpointclmped Ćuk (4LNPCCuk) converter topologies for multilevel DCDC buckboost converter for mediumvoltge bttery storge pplictions re compred with respect to efficiency nd power density. The comprehensive comprison is performed with multi domin models nd optimiztion procedures. For the converters, pretofronts re clculted for different operting frequencies in order to find the optiml design with respect to the specified minimum efficiency. 1 Introduction In the lst decdes there hs been n increse in number nd size of power systems tht generte DC. Among these systems re renewble energy sources, minly wind turbines nd PV plnts. Wind turbines, due to voltile nture of the wind, generte vrible frequency AC voltges, nd so the conversion to DC is necessry. As consequence of the dispersed nture of renewble energy systems, this implies tht there will be distributed genertion of electric power. Since most of the distributed electricl energy sources do not provide their electric power t line frequency nd voltge, DC bus is useful common connection for severl sources [1]. One of the possible concepts is using n intermedite medium voltge DC (MVDC) grid for connecting wind turbines []. There the MVDC level is typiclly in rnge from ±.6kV to ±15kV. This MVDC is then steppedup to HVDC. A similr concept cn be used for PV pplictions [3]. Another interesting ppliction for MVDC re offshore drilling pltforms, tht could be connected to locl MVDC grid from offshore wind turbines, s proposed in [4]. This concept might help to void power qulity problems tht re present in offshore drilling pltforms. Since renewble energy sources re fluctuting it is necessry to include storge system in these MVDC grids to meet the demnd of the consumers during periods of lower power genertion. Storge systems bsed on btteries re compct nd flexible solution for this ppliction [5]. In such bttery storge system, bidirectionl DCDC converter is required for interfcing the bttery (Fig. 1). Besides sttionry systems, there re lso number of mediumvoltge mobile systems tht could use highpower DCDC converters with bttery storge for supplying the electricl propulsion drives (e.g. in trins, ships or hul trucks in mining). In Fig. 1 possible structure of MVDC grid for energy distribution is illustrted. In this pper, the focus is on the highpower DCDC converter which links the low voltge bttery with the MVDCbus (dshed box in Fig. 1). The highpower DCDC converter used s bttery interfce is required to work with wide voltge rnge in buck nd boost mode, llowing chrging of btteries s well s providing the energy to the lod. The specifictions of the considered system re listed in Tble 1. The topologies in Figs. to 4 tht re investigted in this pper hve lredy been presented [6 9], but were not optimized nd compred in detil. This pper focuses on the optiml Bttery Storge Bidirectionl DCDC Converter PV Plnt DCDC Converter MVDC ACDC Multilevel Rectifier DCAC Multilevel Inverter Wind Turbine Utility Figure 1: Structure of the MVDC grid system for energy distribution. The dshed line encloses the prt of the system tht is investigted. Tble 1: Specifictions of the considered converter systems. Bttery Voltge V in 53V..98V DC Link Voltge V out 8V System Power 4MW Module Power 5kW Module Input Current 51A..943A Module Output Current 178A..333A Efficiency > 95% Current Ripple t Bttery < 5% Ambient Temperture 45 C Cooling Medium Temp. 5 C

2 S 6 L S 6 S 5 D 6 D 5 D c3 C 1 S 6 S 5 D 6 D 5 C 1 D c6 D c3 S 5 S 4 C S 4 L S 1 S V in S 3 D 4 D c6 D c D c5 R V out C 1 D 1 D c1 D D c4 C 1 D 3 Auxiliry diodes Figure : 4LNPC converter. V in S 4 L S 1 S S 3 D 4 D 1 D D 3 C 1 C C 3 R Figure 3: 4LFC converter. V out D C c5 1 D c4 C 1 D c D c1 Auxiliry diodes S 1 S S 3 L 1 C 3 V in R V out Figure 4: 4LNPCCuk converter with coupled inductors. design of the DCDC converters nd comprison of the topologies, nd lso gives results for the sensitivity nd sclbility of the converters. The trditionl buckboost topology serves s reference point for the comprison. Since the output voltge of the investigted system is reltively high, employing multilevel bidirectionl DCDC concepts enbles using fster semiconductor devices. Higher switching frequencies in turn, result in volume reduction of the mgnetics which re the bulkiest component of the system. The 4level neutrlpointclmped (4LNPC) converter concept [6] hs been used extensively nd in highvoltge AC drive systems in the lst decdes. However, in this pper the NPC topology is considered s solution for DC DC power conversion (Fig. ). When used for DCDC conversion the NPC topology works in level opertion, while the uxiliry diodes re used only for clmping, i.e. the switch voltge limittion. Fig. 3 shows the 4level flyingcpcitor (4LFC) bidirectionl converter. The boost version of this topology ws introduced in [7]. The min feture of the flying cpcitor topology is the frequency multipliction of the inductor current ripple with respect to the switching frequency, which leds to substntil size reduction even t reltively low switching frequencies. The Ćuk converter with coupled inductors is well known concept widely discussed in literture, e.g. [8 13]. The min feture of this topology is the possibility to reduce the current ripple on one of the inductors by coupling the input nd the output inductor. In order to use the Ćuk topology for medium voltge pplictions, the switching prt of the circuit is relised s multilevel neutrl point clmped topology s shown in Fig. 4. Section of this pper summrises the operting principles of the considered topologies, followed by the design procedure given in section 3. In sections 4 nd 5 results of the comprison bsed on pretofronts re presented, showing the best design in the power density efficiency plne (ρηplne). Finlly, in section 6, conclusions on the presented results re outlined. Operting Principles Before the optimiztion procedures for the design of the system re presented in section 3, the operting principles of the considered multilevel DCDC topologies for mediumvoltge bttery storge ppliction re summrised, nd for the 4level NPC Ćuk concept detiled circuit model for stedy stte opertion is derived..1 4Level NeutrlPointClmped Converter (4LNPC) The considered DCDC opertion mode of the 4LNPC (Fig. ) is level opertion, i.e. only S 1, S nd S 3 re switched during boost mode nd the uxiliry diodes D c1 D c6 re used only for clmping purposes. Switches S 1,S,S 3 re turned on with short dely between them in order to hve low (theoreticlly zero) current through the low power clmping diodes. For designing the 4LNPC converter, the stndrd eqution for boost converter cn be used. For the ske of completeness, the expressions for the voltge conversion rtio, DC input current, nd inductnce nd cpcitnce vlues re listed: V out V in = 1 1 D ; I in = I out 1 1 D ; L 4L NPC = V in(v out V in ) f S V out I L ; C = 3V out f S V out (1 D) (1) where I L nd V C re the pektopek vlues of the input current nd output voltge ripples respectively, nd C is the cpcitnce of ech of the three output cpcitors.. 4Level Flying Cpcitor Converter (4LFC) The operting principle of the multilevel FC circuit s boost converter is nlysed in [7]. The mjor benefit of the 4L version of the circuit is tht the frequency of the inductor current ripple is 3 times higher thn the

3 Switching Stte 1 () (b) (c) () Switching Stte (d) (e) (f) Figure 5: Switching sttes of the 4LFC converter. (b) Figure 6: Switching sttes of the 4LNPC Cuk converter. converter switching frequency, resulting in significnt reduction of the inductor volume compred to the 4LNPC topology operting t the sme switching frequency. Six distinct switching sttes which describe the opertion of the considered circuit re illustrted in Fig. 5. Becuse the energy trnsfer from the input to the output is performed in stges, the topology is sometimes clled threestge flyingcpcitor converter. Stedy Stte Anlysis: The expressions for the voltge gin rtio nd the DC input current of the 4LFC converter re the sme s for the 4LNPC converter. The shpe of the inductor current nd cpcitor voltges re shown in Figs. 7 to 9. The required inductnce of the inductor for the desired current ripple nd the cpcitnce vlue of the cpcitors for the derived voltge ripple cn be clculted with: L 4L FC = V in(v out 3V in ) 6 f S V out I L ; C 1 = V out RV C1 f S ; C = V out RV C f S ; C 3 = V out(1 D) 6RV out f S () The voltge ripple on the intermedite cpcitors V C1, V C must be chosen so tht the mximum voltge on these devices does not exceed the blocking voltge of the switching components. It is lso noteworthy to mention tht the verge voltges on cpcitors C 1 nd C need to be equl to one third nd two third of the output voltge, respectively. If the circuit is to be operted in boost mode, this condition imposes tht the input voltge must be smller thn the voltge on cpcitor C 1, i.e. smller thn one third of the output voltge..3 4Level NeutrlPointClmped Ćuk Converter (4LNPCCuk) The multilevel NPC Ćuk converter topology (Fig. 6) enbles the use of devices with lower brekdown voltge compred to regulr Ćuk topology. The other dvntge is the possibility to reduce the current ripple of one of the inductors by coupling the input nd the output inductor. Coupling of the inductors lso leds to n overll volume reduction of the inductors [9]. Equtions of the 4LNPCCuk topology with reluctnce model nd inductor mutul current ripple dependnce re derived in more detil, s they re not given previously elsewhere. Switching Sttes: The switching sequence during one switching period in boost mode opertion is: A. Stte 1: Inductor Chrging ( < t < DT S ) During the turn on intervl, switches S 1,S,S 3 re turned on sequentilly nd the inductor current is incresing. Fig. 6() illustrtes the current pths in the circuit during this stte. The voltges/currents in stte 1 re: V L1 = V in ; V L = V C1 V C ; I C1 = I C = I C3 = I L ; I C4 = I L1 I L I in ; I C5 = I in I L1 V out R (3) i L (t) I L DT S 3 V in L V in V out /3 L T S (1D)T S T S (D)T S T S ΔI L Figure 7: 4LFC inductor current wveform. t v C (t) V C DT S 3 I L C I L C T S (1D)T S T S (D)T S T S ΔV C Figure 8: 4LFC intermedite stge cpcitor voltge wveform. t v C (t) V out DT S 3 V out RC I L V out /R C T S (1D)T S T S (D)T S T S ΔV out Figure 9: 4LFC output cpcitor voltge wveform. t

4 b i out i C3 V out R C 3 v C3 c g d f i in i 1 Φ 1 R m1 R m i v 1 N R 1 i 1 δ N i v Φ V in C1 C i C1 v C1 S 1 S v C i C Figure 1: Mgnetic structure of the coupled inductor Figure 11: Schemtic of the Ćuk converter with reluctnce model of the coupled inductors. B. Stte : Energy Trnsfer to Cpcitors C 1,C,C 3 (DT S < t < T S ) In the nd switching stte, switches S 1,S,S 3 re turned off sequentilly, nd diodes D 4,D 5,D 6 strt conducting (Fig. 6(b)). The voltges/currents re: V L1 = V in V out ; V L = V C ; I C1 = I C = I C3 = I L1 ; I C4 = I L1 I L I in ; I C5 = I in I L1 V out R (4) Stedy Stte Anlysis: Bsed on the operting principles outlined in the previous section, the stedy stte model is obtined. The mgnetic structure of the coupled inductor is illustrted in Fig. 1. For low current ripple (or zeroripple) nd low sensitivity to tolernces in the mnufcturing process (refer to [1 1] for more detil) it is required tht t lest one winding hs high lekge inductnce. In the given core geometry, the middle yoke is used s lekge pth tht cn be controlled by modifying the ir gp length. In order to get the chrcteristic stedy stte prmeters, reluctnce model for the inductor is used (Fig. 11). For the mgnetic reluctnce model in Fig. 11, the following equtions cn be derived: N 1 i 1 = R m1 Φ 1 R δ (Φ 1 Φ ) (5) N i = R m Φ R δ (Φ Φ 1 ) (6) From the (6), flux Φ cn be expressed s function of flux Φ 1. Φ = N i R δ Φ 1 R m R δ Replcing the vlue for Φ in (5), the vlue of flux Φ 1 is derived s function of currents i 1 nd i. A similr expression is derived for flux Φ. Φ 1 = N 1 (R m R δ ) i 1 N R δ N i ; Φ = N 1R δ i 1 N (R m1 R δ ) i (8) where = R m1 R m R m1 R δ R m R δ. From the well known equtions for the voltges on primry nd secondry side of the trnsformer nd by replcing the expressions for fluxes Φ 1,Φ, the voltges cn be represented s: v 1 = N 1 dφ 1 dt Integrting (9) results in: = N 1 (R m R δ ) di 1 dt N 1N R δ di dt ; v dφ = N = N 1N R δ di 1 dt dt N (R m1 R δ ) (7) di dt. (9) TS TS DTS v 1 dt = V 1 dt = N 1 (R m R δ ) I1 i 1 I 1 i 1 DTS v dt = following results cn be obtined: di 1 N 1N R δ V dt = N (R m1 R δ ) I i di I i N 1N R δ I i I i I1 i 1 di I 1 i 1 di 1, (1) V 1 D T S = N 1 (R m R δ )i 1 N 1 N R δ i ; V D T S = N 1 N R δ i 1 N (R m1 R δ )i (11) Rerrnging (11), the expression for the current ripple on the primry side s function of the secondry side ripple current nd the voltge difference is obtined: i 1 = N N (R m1 R δ ) N 1 R δ D V 1 V i N 1 N 1 (R m R δ ) N R δ N1 (R (1) m R δ ) N R δ f S

5 Specifiction of the Prmeters V IN / V Out / P Out / D Mx T T,mx / T Core,mx / T A / R th,igbt Initil Vlue Switching Frequency f sw ν L1 ν L i L Time [ms] Figure 1: Voltge wveforms on the two ports of the coupled inductor (v 1, v ) nd current wveform of the inductor L 1 when cpcitnce C 1 is equl to 1µF. Inner Optimiztion Loop Modifiction of the Vlues Electricl Model of the Converter Currents / Voltges / Flux Density Winding & Core Losses in the Inductor s Function of Geometry Minimiztion of Ind. Losses Constrints: B B mx Vol Vol mx // J J mx Inductor Therml Model T<T mx Losses in Semiconductors Het Sink Scling : R th R th,mx Globl Optimiztion Algorithm Minimiztion of Losses nd Volume of the System Optiml Design Figure 13: Optimiztion procedure with n inner loop for inductor optimiztion. Modifiction of the Vlues Idelly, the voltges on the two sides of the coupled inductor should be equl, nd the current ripple on one side cn be expressed solely s function of the current ripple on the second side. However, the instntneous vlue of the two voltges, v 1 nd v, cn vry significntly s cn be seen in Fig. 1, which depicts simulted voltge wveforms on the two ports of the coupled inductors. By the nture of the circuit, voltge ripple originting on the cpcitor is visible on the inductor ports during the two switching intervls. Using the equtions for the circuit s operting modes, the voltge nd current rtios of the NPC Ćuk converter cn be obtined. These rtios re the sme s the rtios for the regulr NPC converter. From the equtions for the cpcitor currents Equtions (3) nd (4), the vlues for the inductor currents re obtined: D I 1 = I out 1 D ; I = I out. The intermedite cpcitnce C 1 is clculted from expression: C 1 = V outd f S RV C1, where V C1 is the pektopek vlue of the voltge ripple. The ripple component of the current of inductor L is flowing through cpcitors C nd C 3, nd thus in order to clculte the voltge ripple on these cpcitors the current ripple of L must be tken into ccount. A chnge in the cpcitor voltge cn be relted to the totl chrge q contined in the positive portion of the cpcitor current wveform [14]. The sum of the cpcitnce vlues (C C 3 ) is given by: (13) (14) C C 3 = i 8 f S V out, (15) where V out = V C = V C3, i.e. the voltge ripples on cpcitors C nd C 3 re equl nd uniquely defined by the sum of the cpcitnce vlues. Since the instntneous vlue of the input current is given s: i in = i 1 i i C (16) it cn be seen tht if the ripple component of i is flowing through C, the input current ripple will be equl to the ripple current of the primry inductor. As consequence of this feture, cpcitnce C should be much higher thn C 3, nd the sum of the two cpcitnces should be set tht they stisfy the output voltge ripple requirements. 3 Optiml Converter Design The flow chrt of the generl design procedure is illustrted in Fig. 13, with n inner loop for optimizing the inductor. The procedure cn be pplied for ll converter topologies, but the electricl model must be exchnged.

6 Core b b Air gp length Winding c R th,ca R th,cw R th,w / R th,w / R th,wa T T 1 T A d g d P C P W c Figure 14: Boost inductor geometry. Core gp Winding Ambient Figure 15: Therml equivlent circuit of the boost inductor shown in Fig. 14. The results of the electricl converter model, i.e. currents, voltges nd flux density re pssed to the inductor optimiztion loop nd to the semiconductor loss model, which re then minimized by the globl optimiztion lgorithm. In the following, the models used in the design procedure re explined. 3.1 Power Semiconductors nd Cooling System Since the output voltge of the considered system is.8kv nd the verge input current is 943A, FZ16R17HP4 IGBT modules from Infineon were chosen, with nominl voltge of 17V nd nominl current of 16A. Prior to mking the choice of the semiconductor device, ABB, Dynex nd Infineon IGBT modules were evluted nd compred. Infineon switches were chosen becuse of the lowest switching losses mong the considered modules. The power losses in the switching devices re clculted from dtsheets using the energy loss curves. Het Sink Model: The model used for clculting the therml resistnce of the wter cooling is bsed on the AAVFIN LIQUID COLD PLATE from Avid Thermloy [15]. The thickness of the het sink is tken to be constnt, nd is ssumed tht only the cold plte re influences the therml resistnce. This wy, the volume of the het sink with the required therml resistnce cn be clculted by scling the mnufcturer s dt. 3. Inductor Optimiztion In lmost every converter, the design of the mgnetic components is n importnt prt of the overll design. Due to the high number of degrees of freedom (e.g. geometric prmeters) this is often performed with the help of optimiztion procedures (Fig. 13 Inner Optimiztion Loop). With the input prmeters like voltges, currents, frequency etc, clculted with the electricl model, the losses re clculted with loss models of the core nd the windings. Afterwrds, these losses re hnded to therml model of the mgnetic component which returns ll criticl tempertures. These re then compred with mximum llowed component tempertures. At the end of every design, the component temperture is vlue determining the prcticl fesibility of the design. The geometry under considertion is shelltype inductor (Fig. 14) with litz wire winding, split in two prts, one on ech yoke. Core Power Losses: For clculting the core losses the Improved Generlized Steinmetz Eqution (igse) procedure presented in [16] hs been used. This procedure tkes into ccount the derivtive of the flux wveform, s well s the pektopek vlue of the flux in order to clculte the instntneous core losses. Winding Power Losses: If the switching frequency is in the rnge of few kilohertz nd higher, high frequency effects known s eddy currents hve to be considered when clculting the conduction losses. The winding losses cn be reduced by using litzwire. Procedures for clculting losses in litzwire re bsed on the models for round conductors with the ssumption of orthogonlity between skin nd proximity effects [17]. Expressions for skineffect losses s well s the internl nd externl proximity losses in litzwire windings with n rbitrry number of strnds cn be found in [18]. When clculting the proximity effect losses, the externl mgnetic field strength in every conductor hs to be known. To tht end, the impct of mgneticlly conducting mteril cn be modeled with the method of imges, i.e. the surfces of the core (with n ssumed idel mgnetic conductivity) re replced by mirrored currents nd the Hfield is then obtined nlyticlly [19].

7 System Efficiency [%] khz 4.14mH Buck Boost 1Hz 6.mH 3kHz.76mH 4LNPC 3kHz.7mH 5kHz 1.66mH 6kHz 1.38mH 4LNPCCuk khz 4LFC 7mH 3kHz 18mH 135mH 5kHz 5kHz 6kHz 18mH Power Density [kw/dm 3 ] Figure 16: Pretofronts of the high power multilevel converter topologies. The operting conditions re the sme for ll topologies, i.e. the output power is ssumed to be mximum (4MW) nd the input voltge miniml (53V), corresponding to the mximum current. The power density is clculted with the sum of the boxed component volumes, excluding the volume of dditionl components, e.g. wter pumps for cooling. Volume [dm³] f S = 6kHz L = 1.38mH Inductor Volume Cpcitor Bnk IGBT Modules Het Sink Inductor Volume f S = 6kHz Cpcitor Bnk IGBT Modules Het Sink f S = 5kHz L = 18µH Inductor Volume Cpcitor Bnk IGBT Modules L NPC 4L NPC CUK 4L FC Figure 17: Component volumes of the considered converter topologies. Results re given for the designs with mximum power density with respect to the specified minimum efficiency, nd re mrked in Fig. 16 for ech topology. The inductnce vlue is missing in the cse of 4LNPCCuk topology becuse the current ripple is clculted on different premises, i.e. mutul dependence of the coupled inductor current ripples nd difference in instntneous vlues of the coupled inductor primry nd secondry voltge. Het Sink Therml Modeling: The het generted in the core/winding is trnsferred to the surfce nd then further to the mbient by rdition nd convection. The volume reduction for higher power density lso reduces the cooling surfce nd consequently the temperture rises. Therefore, in highpower density inductors the temperture rise is most often restricting vrible. The bsic equivlent nodl network is illustrted in Fig. 15. The individul therml resistnces re: R th,w is the therml resistnce from the center of the windings to the outer winding surfce. This therml resistnce is clculted using the nlogy between the electrosttic field nd the therml flow field []. R th,c A is the therml resistnce between core nd mbient. R th,w A represents the therml resistnce from the surfce of the winding to the mbient. 4 Optimiztion Results In order to hve n overview of the considered topologies, the pretofronts of the different systems re shown in Fig. 16 for different switching frequencies. The power density is clculted with the sum of the boxed component volumes (boxed volume of inductor, cpcitor bnk, semiconductors with het sink nd control bord with gte drivers), excluding the volume of dditionl components, e.g. wter pumps for cooling. Since the clculted power density does not tke into ccount the component plcement nd clernce, for rel system the power density must be reduced pproximtely by fctor > 1.5 [1]. The component volumes for ech topology re illustrted in Fig. 17. The inductnce vlue is missing in the cse of 4LNPCCuk topology becuse the current ripple is clculted on different premises, i.e. mutul dependence of the coupled inductor current ripples nd difference in instntneous vlues of the coupled inductor primry nd secondry voltge. As cn be seen the flying cpcitor topology hs the highest overll power density. The system consists of eight interleved modules, ech module is designed for n output power of 5 kw. By interleving the modules, the input filter to the converter cn be eliminted. In cse of interleving, the current ripple t ech module is kept below 15%, i.e. the current ripple t the bttery is idelly less thn %. A simplified mechnicl drwing of the 4LFC system (8 interleved modules) is shown in Fig. 18, nd in Tble the prmeters of the presented system design re given. The mechnicl drwing nd description of the individul components of one system module re depicted in Fig Sensitivity Anlysis & Scling Sensitivity Anlysis: In order to be ble to identify the technologies, which hinder higher power density, the limiting fctors for n increse of power density with incresing switching frequency re identified. Different technology vlues/limittions in the optimiztion model re modified nd the impct on the system performnce is identified. The modified technology vlues re listed in Tble 3. The optimiztion of the system is performed with only one prmeter modified while the rest re kept constnt. The preto front of the 4LFC converter system is given in Fig., with the points dded for ech of the modified prmeter. The originl design is lso shown for comprison. For ll of the investigted mteril technologies, the

8 18 cm Gte Driver / Control Bord 77 cm Core Winding 35 cm Het Sink Figure 18: Simplified mechnicl drwing of the designed 4LFC converter system, consisting of 8 interleved modules. A single module is shown in Fig. 19. Semiconductors Cpcitor Bnk Figure 19: Simplified mechnicl drwing of single module of the interleved system from Fig. 18. Tble : Prmeters of the 4LFC converter system. Tble 3: Modified technologies for the sensitivity nlysis. Prmeter Vlue Input Voltge Rnge 53V..89V Output Voltge 8V Switching Frequency 5Hz Power (8 5kW) 4MW System Volume 438dm 3 Approximte Weight 1.t Efficiency Rnge 95.4%..97.4% Power Density 9.13kW/dm 3 Prmeter Het Trnsfer Coefficient Therml Conductivity of Core Mteril Therml Conductivity of Winding Core Losses Semiconductor Conduction Losses Semiconductor Switching Losses Temperture of the Ambient nd Cooling Wter Chnge increse increse increse decrese decrese decrese = 6 C 45 C T wter = 6 C 5 C temperture specifiction of the mbient nd cooling wter is kept t 6 C. Similr preto fronts re obtined in cse of the 4LNPCCuk converter (Fig. 1). As cn be seen, significnt increse in the power density cn be chieved by investing in better cooling system nd reducing the losses in the switching components which re the mjor prt of the converter losses. Evlution of Silicon Crbide (SiC) Switching Devices: Modifiction of the technology vlues in the previous re minly seen s hypotheticl, i.e. wht improvements cn be chieved if investing in new technologies. However, for reducing the semiconductor switching loss, the enbling technology is lredy present. The 1.7 kv SiC MOSFETs re commercilly vilble from CREE. These devices (CAS3M17BM) were used to compre the optiml converter designs with SI switching device technologies in respect to power densities. The topologies included in the comprison re 4LNPC nd 4LFC. For the 4LFC topology, the increse in the power density is System Efficiency [%] No Modifictions 5Hz 1.15mH 1kHz 574mH 1.5kHz 38mH khz 87mH.5kHz 3mH.5kHz, 3mH Therml Conductivity of Core Mteril n.5khz, 3mH Therml Conductivity of Winding Isoltion n, 143mH Conduction Losses 1/n.5kHz, 3mH Core Losses 1/n 5kHz, 115mH Switching Losses 1/n Ambient nd Wter Temp. 3kHz 191mH 143mH.5kHz, 3mH Convection Coef. n 5kHz 115mH System Efficiency [%] kHz No Modifictions 1.5kHz khz.5khz.5khz Therml Conductivity of Winding Isoltion n.5khz Therml Conductivity of Core Mteril n Conduction Losses 1/n 3kHz.5kHz Core Losses 1/n 4.5kHz Switching Losses 1/n Ambient nd Wter Temp. 5kHz.5kHz Convection Coef. n 6kHz Power Density [kw/dm 3 ] Figure : Preto front with the dded points resulting from the technology vlue modifictions for the 4LFC converter. The component volumes included re s ssumed in Fig Power Density [kw/dm 3 ] Figure 1: Preto front with the dded points resulting from the technology vlue modifictions for the 4LNPCCuk converter. The component volumes included re s ssumed in Fig. 16.

9 Tble 4: Operting points used for the sclbility nlysis of the considered topologies. Topology Bttery Voltge [V] Output Voltge [V] Switch Voltge [V] Module Power [kw] 4LNPCCuk 4L FC in the rnge of % to 3%. The reson for such smll volume reduction is the limited switching frequency, i.e. the inductor current ripple hs 3 higher frequency thn the fundmentl switching frequency due to multipliction property of the circuit. After certin frequency (highly depending on ppliction), the totl losses in the inductor begin to rise gin due to AC nd core losses, which results in higher volume required to chieve therml specifiction. On the other hnd, with the 4LNPC topology the pplicble fundmentl switching frequencies re in higher rnge ( ) which resulted in power density increse of to 3 times, minly due to volume reduction of the inductor. Sclbility: After the identifiction of the performnce limits, the operting prmeters re modified, in order to evlute the impct of the operting voltge s well s the power level per module on the chievble system power density. Two dditionl cses with different module power levels re considered, i.e. module power of 1 kw nd of 5kW. For these module power levels the system power ws kept constnt (4MW), nd thus the number of interleved modules is incresing. The ripple current t single module is kept on the sme level (15%) in both cses. Further, n dditionl output voltge level ws investigted (14V). All of the considered operting points re listed in Tble 4. In order to hve fir comprison between the systems with different operting prmeters, the semiconductor modules re scled ccording to the requirements for ech operting point. For exmple, the originl design with.8 kv output voltge nd 5 kw power per module, employed Infineon FZ16R17HP4 semiconductors with voltge/current rting of 1.7 kv/16 A. For the operting points hving the sme output voltge nd different power levels, the scling ws performed by reducing the number of chips in the module to meet the new current rtings, with the spcing for screw terminls nd isoltion inside the module kept constnt, since the voltge rting of the device is identicl. For the sclbility nlysis, optimistions were performed for ech point in Tble 4, nd the results re compred with the results of the system with the originl specifictions. In Fig. nd Fig. 3, the preto front curves with the results of the sclbility nlysis re given for the investigted topologies, i.e. 4LNPCCuk nd 4LFC topology. The tempertures of the mbient nd cooling wter re ssumed to be = 45 C, T wter = 5 C. From the results of the sclbility nlysis it cn be concluded tht the power density of the system cn be incresed by reducing the module power level for the considered ppliction. System Efficiency [%] V, 5kW 8V, 5kW 14V, 5kW 14V, 1kW 8V, 1kW 8V, 5kW System Efficiency [%] V, 5kW 14V, 5kW 14V, 5kW 14V, 1kW 8V, 1kW 8V, 5kW Power Density [kw/dm 3 ] Figure : System pretofronts for the 4LNPCCuk converter with scled operting points. The component volumes included re s ssumed in Fig Power Density [kw/dm 3 ] Figure 3: System pretofronts for the 4LFC converter with scled operting points. The component volumes included re s ssumed in Fig. 16.

10 6 Conclusion In this pper, 4LNPC, 4LFC nd 4LNPCCuk converters re evluted with respect to power density nd efficiency for mediumvoltge bttery storge pplictions. In terms of the highest power density, the 4LFC topology shows the best results, minly becuse of the frequency multipliction of the inductor current ripple with respect to the switching frequency. With the 4LNPCCuk topology significnt reduction of the inductor volume, compred to the regulr NPC topology, cn be chieved. The inductor volumes in cse of the 4LNPC nd the 4LNPCCuk topologies re 139.5dm 3 nd 5.4dm 3, respectively. The sensitivity nlysis of different technology vlues hs shown tht the biggest improvement of the power density of the overll system cn be chieved by investing in better cooling system nd reducing the losses in the switching components which comprise the mjor prt of the converter losses. The power density increse of the converter with better cooling system (i.e. reduction of the mbient nd cooling wter tempertures using e.g. irconditioning nd ctively cooled wter for wter cooling system) is. Additionlly, from the results of the sclbility nlysis it could be concluded tht the volume of the system cn be reduced by proper selecting the module power level for the considered ppliction. References [1] P Krlsson. DC Distributed Power Systems Anlysis, Design nd Control for Renewble Energy System. PhD thesis, Lund University, Sweden,. [] N. Soltu, R. U. Lenke, nd R. W. de Doncker. Highpower dcdc converter. Issue of E. ON Energy Reserch Center Series, 5, 13. [3] H.A.B. Siddique, S.M. Ali, nd R.W. De Doncker. Dc collector grid configurtions for lrge photovoltic prks. In 15th Europen Conference on Power Electronics nd Applictions (EPE), Sept 13. [4] G.F. Reed, B.M. Gringer, A.R. Sprcino, nd ZhiHong Mo. Ship to grid: Mediumvoltge dc concepts in theory nd prctice. Power nd Energy Mgzine, IEEE, 1(6):7 79, Nov 1. [5] R. Crnegie, D. Gothm, D. Nderitu, nd P. V. Preckel. Utility scle energy storge systems benefits, pplictions nd technologies. Technicl report, US Stte Utility Forecsting Group, 13. [6] A. Nbe, I. Tkhshi, nd H. Akgi. A new neutrlpointclmped PWM inverter. IEEE Trnsctions on Industry Applictions, [7] H. Keyhni nd H.A. Toliyt. Flyingcpcitor boost converter. In 7th IEEE Applied Power Electronics Conference nd Exposition (APEC), 1. [8] S. Cuk. A new zeroripple switching dctodc converter nd integrted mgnetics. IEEE Trnsctions on Mgnetics, 19():57 75, Mr [9] Slobodn Cuk nd R.D. Middlebrook. Advnces in switchedmode power conversion prt i. IEEE Trnsctions on Industril Electronics, IE3(1):1 19, Feb [1] Abrhm A. Duhjre. Modelling nd Estimtion of Lekge Phenomen in Mgnetic Circuits. PhD thesis, Cliforni Institute of Technology, Psden, Cliforni, [11] Zhe Zhng. CoupledInductor Mgnetics in Power Electronics. PhD thesis, Cliforni Institute of Technology, Psden, Cliforni, [1] Enrico Snti. Mgnetics nd Control in Power Electronics: I: Modeling of Coupled Inductors; II: OneCycle Control of Switching Converters. PhD thesis, Cliforni Institute of Technology, Psden, Cliforni, [13] J.W. Kolr, H. Sree, N. Mohn, nd Frnz C. Zch. Novel spects of n ppliction of zero ripple techniques to bsic converter topologies. In 8th IEEE Power Electronics Specilists Conference, volume 1, pges , Jun [14] R. W. Erickson nd D. Mksimovic. Fundmentls of Power Electronics. Kluwer Acdemic Publishers, 4. [15] [16] K. Venktchlm, C.R. Sullivn, T. Abdllh, nd H. Tcc. Accurte prediction of ferrite core loss with nonsinusoidl wveforms using only steinmetz prmeters. In IEEE Workshop on Computers in Power Electronics,. [17] J.A. Ferreir. Approprite modelling of conductive losses in the design of mgnetic components. In 1st IEEE Power Electronics Specilists Conference, 199. [18] J. A. Ferreir. Electromgnetic Modelling of Power Electronic Converters. Kluwer Acdemics Publishers, [19] A. V. den Bossche nd V. C. Vlchev. Inductors nd Trnsformers for Power Electronics. CRC Press, 5. [] M. Jritz nd J. Biel. Anlyticl model for the therml resistnce of windings consisting of solid or litz wire. IEEE 15th Europen Conference on Power Electronics nd Applictions, 13. [1] J. Biel, U. Bdstuebner, nd J.W. Kolr. Impct of power density mximiztion on efficiency of dcdc converter systems. IEEE Trnsctions on Power Electronics, 4(1):88 3, Jn 9.