EEE5026; 943/U0280 Physical Design for Nanometer ICs

Size: px
Start display at page:

Download "EEE5026; 943/U0280 Physical Design for Nanometer ICs"

Transcription

1 EEE5026; 943/U0280 Physical Design for Nanometer ICs 張耀文 Yao-Wen Chang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Spring 2018

2 Administrative Matters Time/Location: Thursdays 2:20 pm--5:30 pm; BL-114 Instructor: Yao-Wen Chang URL: Office: BL-428. (Tel) ; (Fax) Office Hours: Wednesdays 4-5pm; other times by appointment Teaching Assistant: Yu-Sheng Lu office hours: 12:30-1:30pm, Wednesdays Prerequisites: data structures, algorithms, and logic design Required Text: Either of the following two books: Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009 Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999 References: Selected reading materials from recent publications Unit 1 2

3 Teaching Assistant Yu-Sheng Lu 呂祐昇 Office: BL-406; Tel: # 6406 Office Hours: 12:30-1:30pm, Wednesdays. 2 nd -year Ph.D. student Unit 1 3

4 Course Objectives Study techniques/algorithms for physical design (converting a circuit description into a geometric description) and their comparisons Study nanometer process/electrical effects and their impacts on the development of physical design tools Study problem-solving (-finding) techniques!!! solution S1 S2 S3 S4 S5 P1 P2 P3 P4 P5 P6 problem Unit 1 4

5 Course Contents VLSI design flow/styles and technology roadmap Physical design processes Partitioning Floorplanning Placement Routing (global, detailed, clock, and power/ground routing) Post-layout optimization Timing: timing modeling, performance-driven design Signal/power integrity: crosstalk, IR drop Design for manufacturability Process variation, optical proximity correction (OPC), chemical mechanical polishing (CMP), multiple pattering, e-beam, extreme ultraviolet (EUV), directed self-assembly (DSA), nanowire, etc. Design for reliability: antenna effect, redundant via, electromigration, thermal, etc. Machine learning based layout optimization Unit 1 5

6 Grading: Grading Policy Homework assignments + quizzes: 25% Programming assignments + lab: 25% One in-class open-book, open-note exam: 30% (June 28) Final project + presentation + demo: 20% (due June 21) A 1-page project proposal is due in-class on May 24 Could be research work, implementation, and/or literature survey Default project: Problem B, C, or E of the 2018 IC/CAD Contest at (E for domestic undergraduate students) Teamwork is permitted (1--3 persons; preferably 2 persons) Bonus for class participation Homework: 30% per day penalty for late submission WWW: Academic Honesty: Avoiding cheating at all cost Unit 1 6

7 2018 CAD ICCAD Default project: Problem B, C, or E of the 2018 IC/CAD Contest at Teamwork is permitted (1--3 persons; preferably 2 persons) Unit 1 7

8 Course contents: Unit 1: Introduction Introduction to VLSI design flow/styles Introduction to physical design automation Semiconductor technology roadmap Readings W&C&C: Chapter 1 S&Y: Chapter 1 physical design fabrication Unit 1 8

9 IC Design & Manufacturing Process Unit 1 9

10 IC Design & Manufacturing Process (cont d) Unit 1 10

11 From Wafer to Chip 2, 4, 6, 8-inch wafers 8-inch vs. 1-inch ignot 12-inch wafer Apple A11 die (iphone 8) TSMC 10nm FinFET; 4.3B transistors; mm 2 18-inch wafer Wafer dicing Wire bonding chips Unit 1 11

12 Apple A9 die for iphone 6s (1.85GHz; 5B+ transistors) Die, Package, and Board TSMC 16nm FinFET mm 2 Samsung 14nm FinFET 96 mm 2 packages packages boards

13 IC Design Considerations Several conflicting considerations: Complexity: large number of devices/transistors Power: low-power consumption Performance: high-speed requirements Cost: die area, packaging, testing, etc. Time-to-market: about a 15% gain for early birds Others: manufacturability, reliability, testability, etc. Unit 1 13

14 Moore s Law: Driving Technology Advances Logic capacity doubles per IC at a regular interval (say, 18 months). G. Moore: Logic capacity doubles per IC every two years (1975). D. House: Computer performance doubles every 18 months (1975) 4Gb Itanium 2 Intel up PentiumPro Pentium 4 Itanium 2 Unit 1 14

15 Design Productivity Crisis Logic transistors per chip 10,000M 1,000M 100M 10M 1M 0.1M 0.01M 58%/yr compound complexity growth rate Complexity limiter 21%/yr compound productivity growth rate 100,000K 10,000K 1,000K 100K 10K 1K 0.1K Productivity in transistors per staff-month Human factors may limit design more than technology. Keys to solve the productivity crisis: CAD (tool & methodology), hierarchical design, abstraction, IP reuse, platform-based design, etc. Unit 1 15

16 Old (1997) Technology Roadmap for Semiconductors Source: International Technology Roadmap for Semiconductors (easier to see the past & trend with the older version; for more recent update, see Deep submicron technology: node (feature size) < 0.25 m. Nanometer Technology: node < 100 nm. 14/16 nm technology was in production in 2015; 10 nm in 2016/2017 (5nm in 2020 by EUV?) Unit 1 16

17 Nanometer Design Challenges Apple A11 (iphone 8): technology node: 10 nm FinFET, P frequency 2.39 GHz, die size mm 2, transistor count per chip 4.3B, wiring level 10+ layers, supply voltage < 1.0 V, power consumption < 16 W (?) Feature size : sub-wavelength lithography (impacts of process variation)? reliability? noise? wire coupling? Frequency, dimension : interconnect delay? electromagnetic field effects? timing closure? Chip complexity : large-scale system design methodology? Supply voltage : signal integrity (noise, IR drop, etc)? Wiring level : manufacturability? yield? 3D layout? Power consumption/density : power & thermal issues? Unit 1 17

18 Design Complexity Increases Dramatically!! Mixed-size Placement Routing & interconnect Unit 1 18

19 High IC Complexity Unit 1 19

20 Power Is a Key Limiting Factor for IC Design! Power density increases exponentially! Watts/cm Power doubles every 4 years 5-year projection: 200W total, 125 W/cm 2! i386 Hot plate i486 Pentium Nuclear Reactor Pentium III Pentium II Pentium Pro Pentium 4 Rocket Nozzle Itanium 2 Itanium 2-DC Power & Performance trade-off!! Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel.

21 Interconnect Dominates Circuit Performance!! Worst-case interconnect delay due to crosstalk Delay (ps) Interconnect delay 10 Gate delay (nm) Technology Node Source: Synopsys In 0.18μm wire-to-wire capacitance dominates (C W >>C S ) C S C W Unit 1 21

22 Manufacturing with Optical Lithography Patterns on a mask are transferred onto a wafer Light source Illumination Lens Mask Projection Lens Immersion (water) R = k 1 λ / NA Wafer 0.25 * 193 nm / 1.35 = 36 nm R: resolution; k 1 : resolution constant (>= 0.25); λ: wavelength NA: numerical aperture = f(lens, refractive index) 22

23 Sub-Wavelength Lithography Gap Sub-wavelength lithography: use light of larger wavelength (193nm) to print features of smaller sizes [S. Borkar, MICRO 04] EUV E-beam 23

24 Technology Roadmap [Aitken, 2014] EUV + DSA envm NEMS CNT Patterning VNW EUV LELE monolithic Opto Log (complexity) Interconnect Transistors SADP FinFET LELE HKMG Strain SAQP TSV MLG, CNT LELELE III-V EUV HNW We Are Here EUV + DWEB PMOS NMOS LE, ~ Planar CMOS LE, < Strong RET AI wires CU wires 10nm 7nm 5nm 3nm Source: R. ISPD 14 Keynote & S Kaufman Award dinner (with revision by ) 24

25 Most Expected Patterning Technologies Multiple patterning lithography (MPL) Extreme ultraviolet lithography (EUVL) Electron beam lithography (EBL) Directed Self- Assembly (DSA) Each technology has different difficulties and requires solutions for a breakthrough

26 Litho-Etch-Litho-Etch (LELE) Double Patterning Pro: Simpler layout decomposition into masks Con: Overlay error with misalignment between masks 40nm 20nm 20nm 80nm 20nm 80nm = + mask 1 mask 2 photoresist mask Target film substrate mask 1 mask 2 1 st exposure-etching process 2 nd exposure-etching process 26

27 Extreme Ultraviolet Lithography (EUVL) EUVL is the most invested next-generation lithography technology Its wavelength is only 13.5 nm Reflective optical components and masks are used Reflective illuminator optics (mirrors) Reflective mask EUV source Reflective projection optics (mirrors) Wafer 27

28 Electron Beam Lithography (EBL) EBL is a maskless next-generation lithography technology Maskless: no more diffraction limitation of light Can define very fine patterns Mapper Lithography 28

29 Directed Self-Assembly (DSA) Block copolymer DSA for contact/via patterning Groups of contacts/vias are patterned by guiding templates with traditional 193i lithography Self-assembly block copolymer Topographical and chemical patterns Smaller and denser patterns Mask Template Contacts Contact patterning with DSA Contact patterns formed by various DSA templates [Xiao, et al., ASP-DAC 15]

30 Cut/Via Pattering with DSA A large template can be used to pattern multiple close contacts even for sub-7nm nodes Layout close vias Vias 22nm Templates 7nm [Xiao, et al., DAC 14]

31 Reliability Becomes a 1st-Order Effect!! Reliability with 10-layer metal? m5 m1 m2 m3 m s g d Si substrate s g d [Courtesy: Dr. Patrick Groeneveld] Unit 1 31

32 3D IC TSV dielectric 3D Integration Adds Complexity! substrate device routing region heat sink thermal TSV signal TSV inter-layer dielectric metal layer device layer TSV-IO substrate tier 3 tier 2 tier 1 2.5D interposer (Xilinx Virtex-7 FPGA) Unit 1 32

33 3D Transistor: FinFET 臺大演講網胡正明院士 Lower leakage power Performance gain at lower voltage Higher drive current 3 fins Unit 1 33

34 Traditional VLSI Design Cycles 1. System specification 2. Functional design 3. Logic synthesis 4. Circuit design 5. Physical design 6. Fabrication 7. Packaging Other tasks involved: verification, simulation, testing, etc. Design metrics: area, speed, power dissipation, manufacturability, reliability, testability, design time, etc. Design revolution: interconnect (not gate) delay dominates circuit performance in deep submicron era. Interconnects are determined in physical design. Shall consider interconnections in early design stages. Unit 1 34

35 Traditional VLSI Design Cycle & verification & verification & simulation Unit 1 35

36 Traditional VLSI Design Flow (Cont'd) design Unit 1 36

37 Physical Design (PD) physical design fabrication PD converts a circuit description into a geometric description. The description is used to manufacture a chip. Physical design cycle: 1. Partitioning 2. Floorplanning 3. Placement 4. Routing (clock, power/ground, signal nets) 5. Post-layout optimization (buffering, sizing, etc.) Others: circuit extraction, timing verification and design rule checking Unit 1 37

38 Physical Design Flow B*-tree based floorplanning system Routing system Unit 1 38

39 Floorplan Examples Apple A5 with dual ARM cores Intel Pentium 4 A floorplan with interconnections Unit 1 39

40 VLSI Placement Place objects into a die s.t. no objects overlap with each other & some cost metric (e.g., wirelength) is optimized chip ISPD98 ibm01 842K cells 646 macros 868K nets 12,752 cells 247 macros A max /A min = 8416 wirings among cells/macros are not shown here!! 40

41 Routing Example 0.18um technology, two layers, pitch = 1 um, 8109 nets. Unit 1 41

42 Modern EDA & Circuit Design Challenges Scalability Multi-dimension Heterogeneity Technology

43 High complexity Example: Modern Placement Millions of objects Placement constraints Blockage, routability, density, timing, region, etc. Mixed-size placement Scalability Multi-dimension Thousands of big macros with millions of small cells Heterogeneity More: 3D IC, datapath, FPGA, etc. Technology TSV 2.5M placeable objects mixed-size design Macros have revolutionized SoC design device TSV dielectric routing region substrate

44 Design Styles Power Others Structure ASIC FPGA SPLD Unit 1 44

45 SSI/SPLD Design Style Unit 1 45

46 Full-Custom Design Style Designers can control the shape of all mask patterns. Designers can specify the design up to the level of individual transistors. Unit 1 46

47 Terminology Cell: a logic block used to build larger circuits. Pin: a wire (metal or polysilicon) to which another external wire can be connected. Nets: a collection of pins which must be electrically connected. Netlist: a list of all nets in a circuit. nets pin cells Unit 1 47

48 Standard-Cell Design Style Selects pre-designed cells (typically, of the same height) to implement logic Over-the-cell routing is pervasive in modern designs Modern designs often contain cells of different row heights (esp. with FinFET transistors) Unit 1 48

49 Standard Cell Example Over-the-cell routing is pervasive in modern designs Courtesy of Newton/Pister, UC-Berkeley Unit 1 49

50 Gate Array Design Style Prefabricates a transistor array Needs wiring customization to implement logic Unit 1 50

51 FPGA Design Style Logic and interconnects are both prefabricated. Illustrated by a symmetric arraybased fieldprogrammable gate array (FPGA) Unit 1 51

52 FPGA/CPLD Examples Xilinx XC4413 FPGA (0.35 um) Altera Stratix IV FPGA (40 nm) 52

53 FPGA Design Process Illustrated by a symmetric array-based FPGA No fabrication is needed Unit 1 53

54 Comparisons of Design Styles Full custom Standard Cell Gate array Cell size variable fixed height fixed fixed FPGA Cell type variable variable fixed programmable Cell placement variable in row fixed fixed Interconnection variable variable variable programmable Full custom Standard Cell Gate array FPGA Fabrication time Packing density Unit cost (large quantity) Unit cost (small quantity) Easy design & simulation Easy design change Timing simulation accuracy Chip speed Unit 1 54

55 Design Style Trade-offs 10 4 full custom 10 3 Turnaround Time (Days) 10 2 semicustom 10 SPLD CPLD FPGA 1 SSI optimal solution Logic capacity (Gates) Unit 1 55

56 Appendix: Structured ASIC Unit 1 56

57 Structured ASIC A structured ASIC consists of predefined metal and via layers, as well as a few of them for customization. The predefined layers support power distribution and local communications among the building blocks of the device. Advantages: fewer masks (lower cost); easier physical extraction and analysis. Popular for engineering change orders (ECO s) A structured ASIC (M5 & M6 can be customized) Faraday s 3MPCA structured ASIC (M4--M6 can be customized) Unit 1 57

58 Comparisons of Design Styles Full custom Standard Cell Gate array Structure ASIC Cell size variable fixed height fixed fixed fixed FPGA Cell type variable variable fixed fixed programmable Cell placement variable in row fixed fixed fixed Interconnection variable variable variable variable/fixed programmable Full custom Standard Cell Gate array Structure ASIC FPGA Fabrication time Packing density Unit cost (large quantity) Unit cost (small quantity) Easy design & simulation Easy design change Timing simulation accuracy Chip speed Unit 1 58

Physical Design for Nanometer ICs

Physical Design for Nanometer ICs EEE5026; 943/U0280 Physical Design for Nanometer ICs 張耀文 Yao-Wen Chang ywchang@ntu.edu.tw http://cc.ee.ntu.edu.tw/~ywchang Graduate Institute of Electronics Engineering Department of Electrical Engineering

More information

CS 6135 VLSI Physical Design Automation Fall 2003

CS 6135 VLSI Physical Design Automation Fall 2003 CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5

More information

Introduction to Electronic Design Automation

Introduction to Electronic Design Automation Introduction to Electronic Design Automation Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Spring 2014 1 Design Automation? 2 Course Info (1/4) Instructor Jie-Hong

More information

Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO

Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO Nanometer Technologies: Where Design and Manufacturing Converge Walden C. Rhines CHAIRMAN & CEO Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware

More information

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Lecture 1: Introduction Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) Course Contents Implementation of high-performance digital

More information

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D 450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology

More information

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional

More information

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Lecture 01: the big picture Course objective Brief tour of IC physical design

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

Lecture Perspectives. Administrivia

Lecture Perspectives. Administrivia Lecture 29-30 Perspectives Administrivia Final on Friday May 18 12:30-3:30 pm» Location: 251 Hearst Gym Topics all what was covered in class. Review Session Time and Location TBA Lab and hw scores to be

More information

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives Lecture 30 Perspectives Administrivia Final on Friday December 15 8 am Location: 251 Hearst Gym Topics all what was covered in class. Precise reading information will be posted on the web-site Review Session

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

Technology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to.

Technology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to. FPGAs 1 CMPE 415 Technology Timeline 1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs The Design Warrior s Guide

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

Static Power and the Importance of Realistic Junction Temperature Analysis

Static Power and the Importance of Realistic Junction Temperature Analysis White Paper: Virtex-4 Family R WP221 (v1.0) March 23, 2005 Static Power and the Importance of Realistic Junction Temperature Analysis By: Matt Klein Total power consumption of a board or system is important;

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Digital Integrated Circuits Perspectives. Administrivia

Digital Integrated Circuits Perspectives. Administrivia Lecture 30 Perspectives Administrivia Final on Friday December 14, 2001 8 am Location: 180 Tan Hall Topics all what was covered in class. Review Session - TBA Lab and hw scores to be posted on the web

More information

Kenneth R. Laker, University of Pennsylvania, updated 20Jan15

Kenneth R. Laker, University of Pennsylvania, updated 20Jan15 http://www.seas.upenn.edu/~ese570/ 1 TOPICS The Course Industry Trends Digital CMOS Basics Some VLSI Fundamentals Illustrative Design Example 2 1. Apply principles of hierarchical digital CMOS VLSI, from

More information

The future of lithography and its impact on design

The future of lithography and its impact on design The future of lithography and its impact on design Chris Mack www.lithoguru.com 1 Outline History Lessons Moore s Law Dennard Scaling Cost Trends Is Moore s Law Over? Litho scaling? The Design Gap The

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

State-of-the-art device fabrication techniques

State-of-the-art device fabrication techniques State-of-the-art device fabrication techniques! Standard Photo-lithography and e-beam lithography! Advanced lithography techniques used in semiconductor industry Deposition: Thermal evaporation, e-gun

More information

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count 18nm FinFET Double-gate structure + raised source/drain Lecture 30 Perspectives Gate Silicon Fin Source BOX Gate X. Huang, et al, 1999 IEDM, p.67~70 Drain Si fin - Body! I d [ua/um] 400-1.50 V 350 300-1.25

More information

DATASHEET CADENCE QRC EXTRACTION

DATASHEET CADENCE QRC EXTRACTION DATASHEET Cadence QRC Etraction, the industry s premier 3D fullchip parasitic etractor that is independent of design style or flow, is a fast and accurate RLCK etraction solution used during design implementation

More information

Leakage Power Minimization in Deep-Submicron CMOS circuits

Leakage Power Minimization in Deep-Submicron CMOS circuits Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance

More information

A Case Study of Nanoscale FPGA Programmable Switches with Low Power

A Case Study of Nanoscale FPGA Programmable Switches with Low Power A Case Study of Nanoscale FPGA Programmable Switches with Low Power V.Elamaran 1, Har Narayan Upadhyay 2 1 Assistant Professor, Department of ECE, School of EEE SASTRA University, Tamilnadu - 613401, India

More information

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor 2005 1 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

Scaling of Semiconductor Integrated Circuits and EUV Lithography

Scaling of Semiconductor Integrated Circuits and EUV Lithography Scaling of Semiconductor Integrated Circuits and EUV Lithography ( 半導体集積回路の微細化と EUV リソグラフィー ) December 13, 2016 EIDEC (Emerging nano process Infrastructure Development Center, Inc.) Hidemi Ishiuchi 1 OUTLINE

More information

PE713 FPGA Based System Design

PE713 FPGA Based System Design PE713 FPGA Based System Design Why VLSI? Dept. of EEE, Amrita School of Engineering Why ICs? Dept. of EEE, Amrita School of Engineering IC Classification ANALOG (OR LINEAR) ICs produce, amplify, or respond

More information

FPGA Based System Design

FPGA Based System Design FPGA Based System Design Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Why VLSI? Integration improves the design: higher speed; lower power; physically smaller. Integration reduces

More information

Newer process technology (since 1999) includes :

Newer process technology (since 1999) includes : Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks

More information

Interconnect-Power Dissipation in a Microprocessor

Interconnect-Power Dissipation in a Microprocessor 4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition

More information

Practical Information

Practical Information EE241 - Spring 2010 Advanced Digital Integrated Circuits TuTh 3:30-5pm 293 Cory Practical Information Instructor: Borivoje Nikolić 550B Cory Hall, 3-9297, bora@eecs Office hours: M 10:30am-12pm Reader:

More information

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141 EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Penn ESE 570 Spring 2016 Khanna Lecture Outline! Design Methodologies " Hierarchy, Modularity,

More information

Practical Information

Practical Information EE241 - Spring 2013 Advanced Digital Integrated Circuits MW 2-3:30pm 540A/B Cory Practical Information Instructor: Borivoje Nikolić 509 Cory Hall, 3-9297, bora@eecs Office hours: M 11-12, W 3:30pm-4:30pm

More information

LSI Design Flow Development for Advanced Technology

LSI Design Flow Development for Advanced Technology LSI Design Flow Development for Advanced Technology Atsushi Tsuchiya LSIs that adopt advanced technologies, as represented by imaging LSIs, now contain 30 million or more logic gates and the scale is beginning

More information

Lecture 9: Cell Design Issues

Lecture 9: Cell Design Issues Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the

More information

ASICs Concept to Product

ASICs Concept to Product ASICs Concept to Product Synopsis This course is aimed to provide an opportunity for the participant to acquire comprehensive technical and business insight into the ASIC world. As most of these aspects

More information

Sustaining the Si Revolution: From 3D Transistors to 3D Integration

Sustaining the Si Revolution: From 3D Transistors to 3D Integration Sustaining the Si Revolution: From 3D Transistors to 3D Integration Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA USA February 23, 2015

More information

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Multiple Patterning for Immersion Extension and EUV Insertion Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Abstract Multiple Patterning for Immersion Extension and

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY S. M. SZE National Chiao Tung University Hsinchu, Taiwan And Stanford University Stanford, California ELECTRONIC AND SEMICONDUCTOR INDUSTRIES

More information

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture

More information

Enabling Breakthroughs In Technology

Enabling Breakthroughs In Technology Enabling Breakthroughs In Technology Mike Mayberry Director of Components Research VP, Technology and Manufacturing Group Intel Corporation June 2011 Defined To be defined Enabling a Steady Technology

More information

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS LUC VAN DEN HOVE President & CEO imec OUTLINE! Industry drivers! Roadmap extension! Lithography options! Innovation through global collaboration

More information

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS -Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS Jiajun Shi, Mingyu Li and Csaba Andras Moritz Department of Electrical and Computer Engineering University of Massachusetts, Amherst, MA,

More information

1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX

1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX Threshold voltage Vt (V) and power supply (V) 1. Introduction Status of s Technology 10 5 2 1 0.5 0.2 0.1 V dd V t t OX 50 20 10 5 2 Gate oxide thickness t OX (nm) Future VLSI chip 2005 2011 CMOS feature

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 1: January 11, 2018 Introduction and Overview Where I come from! Analog VLSI Circuit Design! Convex Optimization " System Hierarchical Optimization!

More information

1 Digital EE141 Integrated Circuits 2nd Introduction

1 Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits Introduction 1 What is this lecture about? Introduction to digital integrated circuits + low power circuits Issues in digital design The CMOS inverter Combinational logic structures

More information

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology;

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Yaping Dan ( 但亚平 ), PhD Office: Law School North 301 Tel: 34206045-3011 Email: yapingd@gmail.com Digital Integrated Circuits Introduction p-n junctions and MOSFETs The CMOS

More information

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite Michael C. Smayling* a, Koichiro Tsujita b, Hidetami Yaegashi c, Valery Axelrad d Tadashi Arai b, Kenichi Oyama c, Arisa Hara c a Tela Innovations,

More information

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING Henry H. Utsunomiya Interconnection Technologies, Inc. Suwa City, Nagano Prefecture, Japan henryutsunomiya@mac.com ABSTRACT This presentation will outline

More information

White Paper Stratix III Programmable Power

White Paper Stratix III Programmable Power Introduction White Paper Stratix III Programmable Power Traditionally, digital logic has not consumed significant static power, but this has changed with very small process nodes. Leakage current in digital

More information

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011 Transistor Scaling in the Innovation Era Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W

More information

28nm and below: New Frontiers and Innovations in Design for Manufacturing. Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM

28nm and below: New Frontiers and Innovations in Design for Manufacturing. Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM 28nm and below: New Frontiers and Innovations in Design for Manufacturing Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM Outline Challenges Variability and the Limits of IC Geometrical Scaling Methodology

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978) IC Knowledge LLC, PO Box 20, Georgetown, MA 01833 www.icknowledge.com Ph: (978) 352 7610, Fx: (978) 352 3870 Linx Consulting, PO Box 384, Mendon, MA 01756 0384 www.linxconsulting.com Ph: (617) 273 8837

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture

More information

Optical Microlithography XXVIII

Optical Microlithography XXVIII PROCEEDINGS OF SPIE Optical Microlithography XXVIII Kafai Lai Andreas Erdmann Editors 24-26 February 2015 San Jose, California, United States Sponsored by SPIE Cosponsored by Cymer, an ASML company (United

More information

5. Lithography. 1. photolithography intro: overall, clean room 2. principle 3. tools 4. pattern transfer 5. resolution 6. next-gen

5. Lithography. 1. photolithography intro: overall, clean room 2. principle 3. tools 4. pattern transfer 5. resolution 6. next-gen 5. Lithography 1. photolithography intro: overall, clean room 2. principle 3. tools 4. pattern transfer 5. resolution 6. next-gen References: Semiconductor Devices: Physics and Technology. 2 nd Ed. SM

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Digital Systems Design and Test Dr. D. J. Jackson Lecture 1-1 Introduction Traditional digital design Manual process of designing and capturing circuits Schematic entry System-level

More information

Lecture 1: Digital Systems and VLSI

Lecture 1: Digital Systems and VLSI VLSI Design Lecture 1: Digital Systems and VLSI Shaahinhi Hessabi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by the book author

More information

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques. Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353/ What have you learned so far?

More information

EE 434 ASIC & Digital Systems

EE 434 ASIC & Digital Systems EE 434 ASIC & Digital Systems Dae Hyun Kim EECS Washington State University Spring 2017 Course Website http://eecs.wsu.edu/~ee434 Themes Study how to design, analyze, and test a complex applicationspecific

More information

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7

Lecture 7. Lithography and Pattern Transfer. Reading: Chapter 7 Lecture 7 Lithography and Pattern Transfer Reading: Chapter 7 Used for Pattern transfer into oxides, metals, semiconductors. 3 types of Photoresists (PR): Lithography and Photoresists 1.) Positive: PR

More information

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and

More information

Low Power Design Methods: Design Flows and Kits

Low Power Design Methods: Design Flows and Kits JOINT ADVANCED STUDENT SCHOOL 2011, Moscow Low Power Design Methods: Design Flows and Kits Reported by Shushanik Karapetyan Synopsys Armenia Educational Department State Engineering University of Armenia

More information

Datorstödd Elektronikkonstruktion

Datorstödd Elektronikkonstruktion Datorstödd Elektronikkonstruktion [Computer Aided Design of Electronics] Zebo Peng, Petru Eles and Gert Jervan Embedded Systems Laboratory IDA, Linköping University http://www.ida.liu.se/~tdts80/~tdts80

More information

Changing the Approach to High Mask Costs

Changing the Approach to High Mask Costs Changing the Approach to High Mask Costs The ever-rising cost of semiconductor masks is making low-volume production of systems-on-chip (SoCs) economically infeasible. This economic reality limits the

More information

Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap

Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap Peter De Dobbelaere Luxtera Inc. 09/19/2016 Luxtera Proprietary www.luxtera.com Luxtera Company Introduction $100B+ Shift

More information

EE141-Spring 2007 Digital Integrated Circuits

EE141-Spring 2007 Digital Integrated Circuits EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon

More information

Digital Design: An Embedded Systems Approach Using VHDL

Digital Design: An Embedded Systems Approach Using VHDL Digital Design: An Embedded Systems Approach Using Chapter 6 Implementation Fabrics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using, by Peter J. Ashenden, published

More information

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1 Assigned Reading R.H.

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

Computer Aided Design of Electronics

Computer Aided Design of Electronics Computer Aided Design of Electronics [Datorstödd Elektronikkonstruktion] Zebo Peng, Petru Eles, and Nima Aghaee Embedded Systems Laboratory IDA, Linköping University www.ida.liu.se/~tdts01 Electronic Systems

More information

! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements

! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams!

More information

BASICS: TECHNOLOGIES. EEC 116, B. Baas

BASICS: TECHNOLOGIES. EEC 116, B. Baas BASICS: TECHNOLOGIES EEC 116, B. Baas 97 Minimum Feature Size Fabrication technologies (often called just technologies) are named after their minimum feature size which is generally the minimum gate length

More information

Digital Integrated Circuits 1: Fundamentals

Digital Integrated Circuits 1: Fundamentals Digital Integrated Circuits 1: Fundamentals Atsushi Takahashi Department of Information and Communications Engineering School of Engineering Tokyo Institute of Technology 1 VLSI and Computer System VLSI

More information

An Interconnect-Centric Approach to Cyclic Shifter Design

An Interconnect-Centric Approach to Cyclic Shifter Design An Interconnect-Centric Approach to Cyclic Shifter Design Haikun Zhu, Yi Zhu C.-K. Cheng Harvey Mudd College. David M. Harris Harvey Mudd College. 1 Outline Motivation Previous Work Approaches Fanout-Splitting

More information

Course Outcome of M.Tech (VLSI Design)

Course Outcome of M.Tech (VLSI Design) Course Outcome of M.Tech (VLSI Design) PVL108: Device Physics and Technology The students are able to: 1. Understand the basic physics of semiconductor devices and the basics theory of PN junction. 2.

More information

Chapter 7 Introduction to 3D Integration Technology using TSV

Chapter 7 Introduction to 3D Integration Technology using TSV Chapter 7 Introduction to 3D Integration Technology using TSV Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Why 3D Integration An Exemplary TSV Process

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information